<bigarchive>
<archive relative="****phantomglobalvars****">
</archive>
<archive relative = "globals.xml" vhdlpkg="chip_cfg_pkg">

  
  <var name="NB_BITS_ADDR" value="28" ><comment>AHB Address bus size</comment></var>
  <var name="SYS_IFC_NB_STD_CHANNEL" value="8" >
    <comment>System Ifc Number of generic channel (range 2 to 7)
    </comment>
  </var>

  

  <var name="SYS_SRAM_ADDR_WIDTH" value="13" ><comment>The System SRam size</comment></var>
  <var name="SYS_SRAM_SIZE" value="exp2(SYS_SRAM_ADDR_WIDTH+2)" />

  <var name="SYS_NB_BITS_MASTER" value="4" ><comment>System Ahb Bus Configuration</comment></var>
  
  <enum name="Sys_Master_Id">
    <entry name="SYS_MID_DUMMY"/>
    <bound name="SYS_MID_RR_Start"><comment>After this starts the Round Robin Pool</comment></bound>
    <entry name="SYS_MID_XCPU_AHB"/>
    <entry name="SYS_MID_XCPU_TCM"/>
    <entry name="SYS_MID_DMA"/>
    <entry name="SYS_MID_IFC"/>
    <entry name="SYS_MID_AIF"/>
    <entry name="SYS_MID_VOC"/>
    <entry name="SYS_MID_GOUDA"/>
    <entry name="SYS_MID_USBC"/>
    <entry name="SYS_MID_F8"/>
    <entry name="SYS_MID_LZMA"/>
    <entry name="SYS_MID_BB2SYS"/>
    <entry name="SYS_MID_BT2SYS"/>
    <bound name="SYS_MID_RR_End"/>
  </enum>
  <var name="SYS_NB_STATIC_MASTER" value="SYS_MID_RR_Start-1"/>
  <var name="SYS_NB_MASTERS" value="SYS_MID_RR_End-1"/>

  <var name="SYS_NB_BITS_SLAVE" value="4"/>
  
  <enum name="Sys_slave_Id">
    <entry name="SYS_SID_DUMMY"/>
    <entry name="SYS_SID_ROM"/>
    <entry name="SYS_SID_RAM0"/>
    <entry name="SYS_SID_RAM1"/>
    <entry name="SYS_SID_IFC"/>
    <entry name="SYS_SID_AIF"/>
    <entry name="SYS_SID_PSRAM"/>
    <entry name="SYS_SID_SPIFLASH"/>
    <entry name="SYS_SID_MAILBOX"/>
    <entry name="SYS_SID_SYS2BB"/>
    <entry name="SYS_SID_SYS2BT"/>
    <bound name="SYS_SID_End"/>
  </enum>
  <var name="SYS_NB_SLAVES" value="SYS_SID_End-1" />

  <var name="SYS_NB_BITS_PSEL" value="5" ><comment>System Apb Bus Configuration</comment></var>
  <var name="SYS_NB_BITS_PADDR" value="12"></var>

  <var name="SYS_APB_STEP" value="exp2(SYS_NB_BITS_PADDR)"/>

  
  <enum name="Sys_Module_Id">
    <entry name="SYS_ID_SCI1"><comment>The following modules are linked to ifc dma req with 2 requests per module</comment></entry>
    <entry name="SYS_ID_SCI2"/>
    <entry name="SYS_ID_SPI1"/>
    <entry name="SYS_ID_SPI2"/>
    <entry name="SYS_ID_SPI3"/>
    <entry name="SYS_ID_DEBUG_UART"/>
    <entry name="SYS_ID_UART1"/>
    <entry name="SYS_ID_UART2"/>
    <entry name="SYS_ID_UART3"/>
    <entry name="SYS_ID_UART4"/>
    <entry name="SYS_ID_SDMMC"/>
    <entry name="SYS_ID_SDMMC2"/>
    <entry name="SYS_ID_CAMERA"/>
    <entry name="SYS_ID_RSVD13"/>
    <entry name="SYS_ID_GSM_RF_SPI"/>
    <entry name="SYS_ID_NB_RF_SPI"/>
    <entry name="SYS_ID_GPIO"/>
    <entry name="SYS_ID_PWM"/>
    <entry name="SYS_ID_KEYPAD"/>
    <entry name="SYS_ID_SEG_SCAN"/>
    <entry name="SYS_ID_I2C1"/>
    <entry name="SYS_ID_I2C2"/>
    <entry name="SYS_ID_I2C3"/>
    <entry name="SYS_ID_DMA"/>
    <entry name="SYS_ID_GOUDA"/>
    <entry name="SYS_ID_GSM_TCU"/>
    <entry name="SYS_ID_NB_TCU"/>
    <entry name="SYS_ID_COMREGS"/>
    <entry name="SYS_ID_RSVD28"/>
    <entry name="SYS_ID_LVDS"/>
    <entry name="SYS_ID_PAGE_SPY"/>
    <entry name="SYS_ID_DEBUG_HOST"/> <comment>value="exp2(SYS_NB_BITS_PSEL)-1" The debug host is placed at last PSEL31 in the IFC</comment>
    <entry name="SYS_ID_GSM_LPS"/>
    <entry name="SYS_ID_NB_LPS"/>
    <entry name="SYS_ID_IFC"/>
    <entry name="SYS_ID_IRQ"/>
    <entry name="SYS_ID_SYS_CTRL"/>
    <entry name="SYS_ID_TIMER"/>
    <entry name="SYS_ID_CALENDAR"/>
    <entry name="SYS_ID_WDT"/>
    <entry name="SYS_ID_LZMA"/>
    <entry name="SYS_ID_PSRAM8_CTRL"/>
    <entry name="SYS_ID_IOMUX"/>
    <entry name="SYS_ID_PMUC"/>
    <entry name="SYS_ID_AON_RAM"/>
    <entry name="SYS_ID_CAU_DIG"/>
    <entry name="SYS_ID_XCPU_CORE"/>
    <entry name="SYS_ID_XCPU_DBG"/>
    <entry name="SYS_ID_GEA3"/>
    <entry name="SYS_ID_F8"/>
    <entry name="SYS_ID_SPIFLASH"/>
    <entry name="SYS_ID_SPIFLASH_EXT"/>
  </enum>

  
  <enum name="Aud_Module_Id">
    <entry name="AUD_ID_IFC"/>
    <entry name="AUD_ID_AIF"/>
    <entry name="AUD_ID_CODEC"/>
    <entry name="AUD_ID_ABB"/>
  </enum>
  
  
  <enum name="Sys_Ifc_Request_IDs">
    <entry name="SYS_ID_TX_SCI1"/>      
    <entry name="SYS_ID_RX_SCI1"/>      
    <entry name="SYS_ID_TX_SCI2"/>      
    <entry name="SYS_ID_RX_SCI2"/>      
    <entry name="SYS_ID_TX_SPI1"/>      
    <entry name="SYS_ID_RX_SPI1"/>      
    <entry name="SYS_ID_TX_SPI2"/>      
    <entry name="SYS_ID_RX_SPI2"/>      
    <entry name="SYS_ID_TX_SPI3"/>      
    <entry name="SYS_ID_RX_SPI3"/>      
    <entry name="SYS_ID_TX_DEBUG_UART"/>
    <entry name="SYS_ID_RX_DEBUG_UART"/>
    <entry name="SYS_ID_TX_UART1"/>     
    <entry name="SYS_ID_RX_UART1"/>     
    <entry name="SYS_ID_TX_UART2"/>     
    <entry name="SYS_ID_RX_UART2"/>     
    <entry name="SYS_ID_TX_UART3"/>     
    <entry name="SYS_ID_RX_UART3"/>     
    <entry name="SYS_ID_TX_UART4"/>     
    <entry name="SYS_ID_RX_UART4"/>     
    <entry name="SYS_ID_TX_SDMMC1"/>    
    <entry name="SYS_ID_RX_SDMMC1"/>    
    <entry name="SYS_ID_TX_SDMMC2"/>    
    <entry name="SYS_ID_RX_SDMMC2"/>    
    <entry name="SYS_ID_TX_FREE"/>      
    <entry name="SYS_ID_RX_CAMERA"/>    
  </enum>
  
  <var name="SYS_NB_DMA_REQ" value="24"></var>
  <var name="SYS_NB_DMA_REQ_WIDTH" value="5"></var>

    
    <enum name="Sys_Irq_Id">
        <entry name="SYS_IRQ_GSM_TCU0"><comment>System IRQ IDs<br/>Pulse IRQ</comment></entry>
        <entry name="SYS_IRQ_GSM_TCU1"/>
        <entry name="SYS_IRQ_GSM_FRAME"/>
        <entry name="SYS_IRQ_NB_TCU0"/>
        <entry name="SYS_IRQ_NB_TCU1"/>
        <entry name="SYS_IRQ_NB_FRAME"/>
        <entry name="SYS_IRQ_RFSPI_MUX"/>
        <bound name="SYS_NB_IRQ_PULSE"><comment>Number of Pulse IRQ</comment></bound>
        <entry name="SYS_IRQ_COM0"><comment>Level IRQ</comment></entry>
        <entry name="SYS_IRQ_COM1"/>
        <entry name="SYS_IRQ_DMA"/>
        <entry name="SYS_IRQ_GPIO"/>
        <entry name="SYS_IRQ_KEYPAD"/>
        <entry name="SYS_IRQ_TIMER"/>
        <entry name="SYS_IRQ_OS_TIMER"/>
        <entry name="SYS_IRQ_CALENDAR"/>
        <entry name="SYS_IRQ_GSM_RFSPI"/>
        <entry name="SYS_IRQ_GSM_LPS"/>
        <entry name="SYS_IRQ_SCI1"/>
        <entry name="SYS_IRQ_SCI2"/>
        <entry name="SYS_IRQ_VOC"/>
        <entry name="SYS_IRQ_SPI1"/>
        <entry name="SYS_IRQ_SPI2"/>
        <entry name="SYS_IRQ_SPI3"/>
        <entry name="SYS_IRQ_UART1"/>
        <entry name="SYS_IRQ_UART2"/>
        <entry name="SYS_IRQ_I2C1"/>
        <entry name="SYS_IRQ_I2C2"/>
        <entry name="SYS_IRQ_I2C3"/>
        <entry name="SYS_IRQ_AUD_IFC0"/>
        <entry name="SYS_IRQ_AUD_IFC1"/>
        <entry name="SYS_IRQ_USBC"/>
        <entry name="SYS_IRQ_SDMMC"/>
        <entry name="SYS_IRQ_GOUDA"/>
        <entry name="SYS_IRQ_CAMERA"/>
        <entry name="SYS_IRQ_DEBUG_UART"/>
        <entry name="SYS_IRQ_UART3"/>
        <entry name="SYS_IRQ_UART4"/>
        <entry name="SYS_IRQ_NB_RX"/>
        <entry name="SYS_IRQ_NB_RFSPI"/>
        <entry name="SYS_IRQ_NB_LPS"/>
        <entry name="SYS_IRQ_NB_TCU_SYNC"/>
        <entry name="SYS_IRQ_F8"/>
        <entry name="SYS_IRQ_LZMA"/>
        <entry name="SYS_IRQ_SDMMC2"/>
        <entry name="SYS_IRQ_PSRAM8_CTRL"/>
        <entry name="SYS_IRQ_WCN_SOFT"/>
        <entry name="SYS_IRQ_WCN_WLAN"/>
        <entry name="SYS_IRQ_WCN_WDT"/>
        <entry name="SYS_IRQ_WCN_OSC"/>
        <entry name="SYS_IRQ_RF_SOFT"/>
        <entry name="SYS_IRQ_RF_WDT"/>
        <entry name="SYS_IRQ_GPADC"/>
        <entry name="SYS_IRQ_PMUC"/>
        <entry name="SYS_IRQ_LVDS"/>
        <bound name="SYS_IRQ_QTY"><comment>Number of IRQ handled by the production driver</comment></bound>
        <bound name="SYS_NB_IRQ"><comment>Number of IRQ</comment></bound>
    </enum>
    <var name="SYS_NB_IRQ_LEVEL" value="SYS_NB_IRQ - SYS_NB_IRQ_PULSE"><comment>Number of Level IRQ</comment></var>
    
    <range name="SYS_IRQ_GSM_TCU" left="SYS_IRQ_GSM_TCU1" right="SYS_IRQ_GSM_TCU0" />
    <range name="SYS_IRQ_NB_TCU" left="SYS_IRQ_NB_TCU1" right="SYS_IRQ_NB_TCU0" />
    <range name="SYS_IRQ_COMREG" left="SYS_IRQ_COM1" right="SYS_IRQ_COM0" />
    


  

  <var name="BB_SRAM_ADDR_WIDTH" value="13" ><comment>The Baseband SRam size</comment></var>
  <var name="BB_SRAM_SIZE" value="24*1024" />

  <var name="BB_NB_BITS_MASTER" value="3" ><comment>Baseband Ahb Bus Configuration</comment></var>
  
  <enum name="BB_Master_Id">
    <entry name="BB_MID_DUMMY"/>
    <bound name="BB_MID_RR_Start"><comment>After this starts the Round Robib Pool</comment></bound>
    <entry name="BB_MID_BCPU_AHB"/>
    <entry name="BB_MID_BCPU_TCM"/>
    <entry name="BB_MID_RF_IF"/>
    <entry name="BB_MID_DMA"/>
    <entry name="BB_MID_SYS2BB"/>
    <bound name="BB_MID_RR_End"/>
  </enum>
  <var name="BB_NB_STATIC_MASTER" value="BB_MID_RR_Start-1"/>
  <var name="BB_NB_MASTERS" value="BB_MID_RR_End-1"/>
  <var name="BB_MAX_BURST_SIZE" value="4"/>
  <var name="BB_MAX_BURST_BITS" value="2"/>
  <var name="BB_NB_BITS_SLAVE" value="3"/>

  
  <enum name="BB_slave_Id">
    <entry name="BB_SID_DUMMY"/>
    <entry name="BB_SID_ROM"/>
    <entry name="BB_SID_BB2G_RAM"/>
    <entry name="BB_SID_NB_RAM"/>
    <entry name="BB_SID_IFC"/>
    <entry name="BB_SID_BB2SYS"/>
    <entry name="BB_SID_MAILBOX"/>
    <entry name="BB_SID_PSRAM"/>
    <bound name="BB_SID_End"/>
  </enum>
  <var name="BB_NB_SLAVES" value="BB_SID_End-1" />  

  <var name="BB_NB_BITS_PSEL" value="5"><comment>BaseBand Apb Bus Configuration</comment></var>
  <var name="BB_NB_BITS_PADDR" value="12"></var>

  <var name="BB_APB_STEP" value="exp2(BB_NB_BITS_PADDR)"/>

  
  <enum name="BB_Module_Id">
    <entry name="BB_ID_XCOR"/>
    <entry name="BB_ID_CORDIC"/>
    <entry name="BB_ID_ITLV"/>
    <entry name="BB_ID_VITAC"/>
    <entry name="BB_ID_EXCOR"/>
    <entry name="BB_ID_CHOLK"/>
    <entry name="BB_ID_CIPHER"/>
    <entry name="BB_ID_CP2"/>
    <entry name="BB_ID_BCPU_CORE"/>
    <entry name="BB_ID_BCPU_DBG"/>
    <entry name="BB_ID_ROM_CTRL"/>
    <entry name="BB_ID_RF_IF"/>
    <entry name="BB_ID_IRQ"/>
    <entry name="BB_ID_COMREGS"/>
    <entry name="BB_ID_DMA"/>
    <entry name="BB_ID_RSVD15"/>
    <entry name="NB_ID_CTRL"/>
    <entry name="NB_ID_COMMON"/>
    <entry name="NB_ID_INTC"/>
    <entry name="NB_ID_CS"/>
    <entry name="NB_ID_FFT"/>
    <entry name="NB_ID_VITERBI"/>
    <entry name="NB_ID_MEAS"/>
    <entry name="NB_ID_DS_BSEL"/>
    <entry name="NB_ID_TX_PUSCH"/>
    <entry name="NB_ID_TX_CHSC"/>
    <entry name="NB_ID_TX_FE"/>
    <entry name="NB_ID_RSVD27"/>
    <entry name="NB_ID_RSVD28"/>
    <entry name="NB_ID_RSVD29"/>
    <entry name="NB_ID_RSVD30"/>
    <entry name="NB_ID_RSVD31"/>
    <entry name="BB_ID_A53"/>
    <bound name="BB_NB_PSEL"><comment></comment></bound>
  </enum>

    
    <enum name="BB_Irq_Id">
        <entry name="BB_IRQ_GSM_TCU0"><comment>Baseband IRQ IDs<br/>Pulse IRQ</comment></entry>
        <entry name="BB_IRQ_GSM_TCU1"/>
        <entry name="BB_IRQ_GSM_FRAME"/>
        <entry name="BB_IRQ_NB_TCU0"/>
        <entry name="BB_IRQ_NB_TCU1"/>
        <entry name="BB_IRQ_NB_FRAME"/>
        <entry name="BB_IRQ_A53"/>
        <bound name="BB_NB_IRQ_PULSE"><comment>Number of Pulse IRQ</comment></bound>
        <entry name="BB_IRQ_COM0"><comment>Level IRQ</comment></entry>
        <entry name="BB_IRQ_COM1"/>
        <entry name="BB_IRQ_DMA"/>
        <entry name="BB_IRQ_RFIF_DBG0"/>
        <entry name="BB_IRQ_RFIF_DBG1"/>
        <entry name="BB_IRQ_RFIF_RX"/>
        <entry name="BB_IRQ_RFIF_TX"/>
        <entry name="BB_IRQ_ITLV"/>
        <entry name="BB_IRQ_VITAC"/>
        <entry name="BB_IRQ_XCOR"/>
        <entry name="BB_IRQ_EXCOR"/>
        <entry name="BB_IRQ_CHOLK"/>
        <entry name="BB_IRQ_NB_RX"/>
        <entry name="BB_IRQ_NB_TX"/>
        <entry name="BB_IRQ_NB_ACC"/>
        <entry name="BB_IRQ_VOC"/>
        <entry name="BB_IRQ_PSRAM8_CTRL"/>
        <entry name="BB_IRQ_RF_SOFT"/>
        <bound name="BB_NB_IRQ"><comment>Number of IRQ</comment></bound>
    </enum>
    <var name="BB_NB_IRQ_LEVEL" value="BB_NB_IRQ - BB_NB_IRQ_PULSE"><comment>Number of Level IRQ</comment></var>

    
    <range name="BB_IRQ_GSM_TCU" left="BB_IRQ_GSM_TCU1" right="BB_IRQ_GSM_TCU0" />
    <range name="BB_IRQ_NB_TCU" left="BB_IRQ_NB_TCU1" right="BB_IRQ_NB_TCU0" />
    <range name="BB_IRQ_COMREG" left="BB_IRQ_COM1" right="BB_IRQ_COM0" />
    


  
  <var name="BB_SYMBOL_SIZE" value="13" ><comment>RF Input samples size (signed)</comment></var>
  <var name="VITAC_MULT_SIZE" value="14" ><comment>Vitac Multipliers size</comment></var>
  <var name="NB_DBG_SYS_SPY" value="11" ><comment>Total bits numbers of signals to spy on the SYS side</comment></var>  
  <var name="NB_DBG_BB_SPY" value="28" ><comment>Total bits numbers of signals to spy on the BB side</comment></var>  


  
  <var name="RFDIG_NB_BITS_PADDR" value="12"></var>
  <var name="RFDIG_APB_STEP" value="exp2(RFDIG_NB_BITS_PADDR)"/>

  
  <enum name="RFDIG_Module_Id">
    <entry name="RFDIG_ID_ITFC"/>
    <entry name="RFDIG_ID_RSVD1"/>
    <entry name="RFDIG_ID_DFE"/>
    <entry name="RFDIG_ID_RSVD3"/>
    <entry name="RFDIG_ID_CTRL"/>
    <entry name="RFDIG_ID_TIMER0"/>
    <entry name="RFDIG_ID_TIMER1"/>
    <entry name="RFDIG_ID_TIMER2"/>
    <entry name="RFDIG_ID_UART"/>
    <entry name="RFDIG_ID_WDT"/>
    <entry name="RFDIG_ID_RF_COMREGS"/>
    <entry name="RFDIG_ID_SYS_COMREGS"/>
    <entry name="RFDIG_ID_RFFE"/>
    <entry name="RFDIG_ID_RSVD13"/>
    <entry name="RFDIG_ID_RSVD14"/>
    <entry name="RFDIG_ID_RSVD15"/>
    <bound name="RFDIG_NB_PSEL"><comment></comment></bound>
  </enum>

  <var name="PULPCORE_NB_BITS_PADDR" value="14"></var>
  <var name="PULPCORE_APB_STEP" value="exp2(PULPCORE_NB_BITS_PADDR)"/>

  <enum name="PULPCORE_Module_Id">
    <entry name="PULPCORE_ID_DBG_UNIT"/>
    <entry name="PULPCORE_ID_RSVD0"/>
    <entry name="PULPCORE_ID_IRQ_UNIT"/>
    <entry name="PULPCORE_ID_SLEEP_UNIT"/>
    <bound name="PULPCORE_ID_NB_PSEL"><comment></comment></bound>
  </enum>


  
  <var name="WCN_NB_BITS_PADDR" value="12"></var>
  <var name="WCN_APB_STEP" value="exp2(WCN_NB_BITS_PADDR)"/>

  
  <enum name="WCN_Sys_Id">
    <entry name="WCN_ID_SYS_CTRL"/>
    <entry name="WCN_ID_DBM"/>
    <entry name="WCN_ID_SYS_IFC"/>
    <entry name="WCN_ID_BT_CORE"/>
    <entry name="WCN_ID_BT_UART"/>
    <entry name="WCN_ID_RF_IF"/>
    <entry name="WCN_ID_BT_MODEM"/>
    <entry name="WCN_ID_WLAN"/>
    <entry name="WCN_ID_WDT"/>
    <entry name="WCN_ID_TRAP"/>
    <entry name="WCN_ID_SYSTICK"/>
    <entry name="WCN_ID_BT_COMREGS"/>
    <entry name="WCN_ID_SYS_COMREGS"/>
    <bound name="WCN_NB_PSEL"><comment></comment></bound>
  </enum>

  <enum name="WCN_Aud_Id">
    <entry name="WCN_ID_AUD_IFC"/>
    <entry name="WCN_ID_RSVD1"/>
    <entry name="WCN_ID_FM_DSP"/>
  </enum>


  <cjoker>
    /// XHALT macro will send the event 0x4a17 to the debug host and
    /// will stall the XCPU.  The XCPU can be released from Coolwatcher
    /// by issuing a xrbp command.
    #define XHALT { \
        asm("nop "); \
        asm("nop "); \
        asm("nop "); \
        asm("nop "); \
        while (hwp_debugHost->event != DEBUG_HOST_EVENT0_SEMA); \
        hwp_debugHost->event = 0x4a17; \
        hwp_sysCtrl->XCpu_Dbg_BKP |= SYS_CTRL_STALLED; \
        asm("nop "); \
        asm("nop "); \
        asm("nop "); \
        asm("nop "); \
    }
  </cjoker>


</archive>

<archive relative = "global_macros.xml" asm="no">

<cjoker>

#define KSEG0(addr)     ( (addr) | 0x80000000 )
#define KSEG1(addr)     ( (addr) | 0xa0000000 )
#define KSEG01_PHY_ADDR(addr)       ((UINT32)(addr) &amp; 0x0FFFFFFF)
#define REG_ACCESS_ADDRESS(addr)    KSEG1(addr)

/* Define access cached or uncached */
#define MEM_ACCESS_CACHED(addr)     ((UINT32*)((UINT32)(addr)&amp;0xdfffffff))
#define MEM_ACCESS_UNCACHED(addr)   ((UINT32*)((UINT32)(addr)|0x20000000))

/* Register access for assembly */
#define BASE_HI(val) (((0xa0000000 | val) &amp; 0xffff8000) + (val &amp; 0x8000))
#define BASE_LO(val) (((val) &amp; 0x7fff) - (val &amp; 0x8000))


/* to extract bitfield from register value */
#define GET_BITFIELD(dword, bitfield) (((dword) &amp; (bitfield ## _MASK)) &gt;&gt; (bitfield ## _SHIFT))

#define EXP2(n) (1&lt;&lt;(n))

#define IS_IN_RANGE(value, base, size) (((value) &gt;= (base)) &amp;&amp; ((value) &lt; (base) + (size)))
#define ADDRESS_IN_HWP(address, hwp)   IS_IN_RANGE((UINT32)(address) &amp; 0x0FFFFFFF, (UINT32)(hwp) &amp; 0x0FFFFFFF, sizeof(*(hwp)))

/// XHALT macro will send the event 0x4a17 to the debug host and
/// will stall the XCPU.  The XCPU can be released from Coolwatcher
/// by issuing a xrbp command.
#define XHALT { \
    asm("nop "); \
    asm("nop "); \
    asm("nop "); \
    asm("nop "); \
    while (hwp_debugHost->event != DEBUG_HOST_EVENT0_SEMA); \
    hwp_debugHost->event = 0x4a17; \
    hwp_sysCtrl->XCpu_Dbg_BKP |= SYS_CTRL_STALLED; \
    asm("nop "); \
    asm("nop "); \
    asm("nop "); \
    asm("nop "); \
}

</cjoker>

</archive>
<archive relative = "voc_global.xml">
  
  <var name="AHB_NB_BITS_ADDR" value="28" ><comment>AHB Address bus size</comment></var>
</archive>

<archive relative="abb.xml">
  <module name="abb" category="Audio">
    <reg protect="r" name="ID">
      <bits access="r" name="ID_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ChipID" pos="15:4" rst="2747">
      </bits>
      <bits access="r" name="RevID" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="Codec_Cfg">
      <bits access="r" name="Codec_Cfg_reserved_0" pos="31:13" rst="0">
      </bits>
      <bits access="rw" name="pu_all" pos="12" rst="0">
        <comment>
          power up codec
        </comment>
      </bits>
      <bits access="rw" name="sel_bg" pos="11" rst="1">
        <comment>
          select bandgap
        </comment>
      </bits>
      <bits access="rw" name="vmic_bit" pos="10:9" rst="1">
        <comment>
          adjust the mic bias voltage
        </comment>
      </bits>
      <bits access="rw" name="vcom_mode" pos="8:6" rst="0">
        <comment>
          vcomref mode select
        </comment>
      </bits>
      <bits access="rw" name="vcombuf_sel" pos="5:2" rst="2">
        <comment>
          vcombuffer select
        </comment>
      </bits>
      <bits access="rw" name="ibias_bit" pos="1:0" rst="3">
        <comment>
          adjust bias current
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="Codec_Mode0">
      <bits access="r" name="Codec_Mode0_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rw" name="micinput_l_sel" pos="14:9" rst="0">
        <comment>
          micpga input mode select
        </comment>
      </bits>
      <bits access="rw" name="micinput_r_sel" pos="8:3" rst="0">
        <comment>
          micpga input mode select
        </comment>
      </bits>
      <bits access="rw" name="micloop_l_mode" pos="2" rst="0">
        <comment>
          micpga_l output loop mode select
        </comment>
      </bits>
      <bits access="rw" name="micloop_r_mode" pos="1" rst="0">
        <comment>
          micpga_r output loop mode select
        </comment>
      </bits>
      <bits access="rw" name="linein_mode" pos="0" rst="0">
        <comment>
          linein output mode select
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="Codec_Mode1">
      <bits access="r" name="Codec_Mode1_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="rw" name="dac_l_mode" pos="7" rst="0">
        <comment>
          dac_l output mode select
        </comment>
      </bits>
      <bits access="rw" name="dac_r_mode" pos="6" rst="0">
        <comment>
          dac_r output mode select
        </comment>
      </bits>
      <bits access="rw" name="hp_inputsel" pos="5:4" rst="1">
        <comment>
          HP input select
        </comment>
      </bits>
      <bits access="rw" name="reci_input_sel" pos="3:2" rst="0">
        <comment>
          receiver input select
        </comment>
      </bits>
      <bits access="rw" name="adc_vos_det_mode" pos="1" rst="0">
        <comment>
          adc vos detection mode
        </comment>
      </bits>
      <bits access="rw" name="adc_test_mode" pos="0" rst="0">
        <comment>
          adc test mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="Codec_Mux_Setting">
      <bits access="r" name="Codec_Mux_Setting_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="rw" name="mux_ibit" pos="3:2" rst="2">
        <comment>
          mux current
        </comment>
      </bits>
      <bits access="rw" name="mux_gain_bit" pos="1:0" rst="3">
        <comment>
          mux gain select
2'b00:: 0dB
2'b01:: 3dB
2'b10:: 6dB
2'b11:: 9dB
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="Codec_HP_Setting0">
      <bits access="r" name="Codec_HP_Setting0_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="rw" name="hp_ibit" pos="7:6" rst="1">
        <comment>
          hp current
        </comment>
      </bits>
      <bits access="rw" name="hp_pm_ibit" pos="5" rst="0">
      </bits>
      <bits access="rw" name="hp_pm_rbit" pos="4" rst="0">
      </bits>
      <bits access="rw" name="hp_gain_bit" pos="3:1" rst="5">
        <comment>
          0~18dB 3dB/step
        </comment>
      </bits>
      <bits access="rw" name="hp_gain_double_en" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="Codec_HP_Setting1">
      <bits access="r" name="Codec_HP_Setting1_reserved_0" pos="31:9" rst="0">
      </bits>
      <bits access="rw" name="hp_l_diff_mode" pos="8" rst="0">
        <comment>
          left headphone amplifier differential work mode
        </comment>
      </bits>
      <bits access="rw" name="hp_r_diff_mode" pos="7" rst="0">
        <comment>
          left headphone amplifier differential work mode
        </comment>
      </bits>
      <bits access="rw" name="hp_l_capless_mode" pos="6" rst="0">
      </bits>
      <bits access="rw" name="hp_r_capless_mode" pos="5" rst="0">
      </bits>
      <bits access="rw" name="vcombuf_capless_hp_ibit" pos="4:3" rst="1">
      </bits>
      <bits access="rw" name="vcombuf_capless_hp_fb_sel" pos="2:1" rst="0">
      </bits>
      <bits access="rw" name="vcombuf_capless_hp_doublepath_en" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ADC_Setting">
      <bits access="r" name="ADC_Setting_reserved_0" pos="31:9" rst="0">
      </bits>
      <bits access="rw" name="adc_l_gain_bit" pos="8:6" rst="0">
        <comment>
          adc_l gain select
3'b000:: mute
001~111 -3dB ~ +15dB 3dB/step
        </comment>
      </bits>
      <bits access="rw" name="adc_r_gain_bit" pos="5:3" rst="0">
        <comment>
          adc_r gain select
3'b000:: mute
001~111 -3dB ~ +15dB 3dB/step
        </comment>
      </bits>
      <bits access="rw" name="adc_ibit" pos="2:1" rst="0">
        <comment>
          adjust adc current
        </comment>
      </bits>
      <bits access="rw" name="adc_clk_inv_sel" pos="0" rst="0">
        <comment>
          select at which edge of clk_adc the input signal would be sampled
0: sampling at rising edge
1: sampling at falling edge
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DAC_Setting">
      <bits access="r" name="DAC_Setting_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="dac_gain_bit" pos="11:8" rst="1">
        <comment>
          dac gain select (fine adjust)
~0.5dB/step
        </comment>
      </bits>
      <bits access="rw" name="dac_vreg_bit" pos="7:5" rst="5">
        <comment>
          adjust dac vreg voltage
        </comment>
      </bits>
      <bits access="rw" name="dac_vos_bit" pos="4:1" rst="2">
        <comment>
          adjust dac vos
        </comment>
      </bits>
      <bits access="rw" name="dac_clk_inv_sel" pos="0" rst="0">
        <comment>
          select at which edge of clk_dac the input signal would be sampled
0: sampling at rising edge
1: sampling at falling edge
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="Micpga_Setting">
      <bits access="r" name="Micpga_Setting_reserved_0" pos="31:14" rst="0">
      </bits>
      <bits access="rw" name="micpga_l_gain_bit" pos="13:12" rst="3">
        <comment>
          micpga_l_gain select
2'b00:: 0dB
2'b01:: 9dB
2'b10:: 21dB
2'b11:: 30dB
        </comment>
      </bits>
      <bits access="rw" name="micpga_r_gain_bit" pos="11:10" rst="3">
        <comment>
          micpga_r_gain select
2'b00:: 0dB
2'b01:: 9dB
2'b10:: 21dB
2'b11:: 30dB
        </comment>
      </bits>
      <bits access="rw" name="micpga_l_ibit" pos="9:8" rst="0">
        <comment>
          adjust micpga_l current
        </comment>
      </bits>
      <bits access="rw" name="micpga_r_ibit" pos="7:6" rst="0">
        <comment>
          adjust micpga_r current
        </comment>
      </bits>
      <bits access="rw" name="micpga_l_capless_mode" pos="5" rst="0">
      </bits>
      <bits access="rw" name="micpga_l_inbias_en" pos="4:3" rst="0">
      </bits>
      <bits access="rw" name="micpga_r_capless_mode" pos="2" rst="0">
      </bits>
      <bits access="rw" name="micpga_r_inbias_en" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="Reci_Setting">
      <bits access="r" name="Reci_Setting_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="rw" name="reci_ibit" pos="7:6" rst="1">
      </bits>
      <bits access="rw" name="reci_pm_ibit" pos="5" rst="0">
      </bits>
      <bits access="rw" name="reci_pm_rbit" pos="4" rst="0">
      </bits>
      <bits access="rw" name="reci_gain_bit" pos="3:1" rst="5">
      </bits>
      <bits access="rw" name="reci_gain_double_en" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="Reset_Ctrl">
      <bits access="r" name="Reset_Ctrl_reserved_0" pos="31:7" rst="0">
      </bits>
      <bits access="rw" name="reset_micpga_l" pos="6" rst="0">
        <comment>
          reset micpga_l
        </comment>
      </bits>
      <bits access="rw" name="reset_micpga_r" pos="5" rst="0">
        <comment>
          reset micpga_r
        </comment>
      </bits>
      <bits access="rw" name="reset_adc" pos="4" rst="0">
        <comment>
          reset adc
        </comment>
      </bits>
      <bits access="rw" name="reset_mux_l" pos="3" rst="0">
        <comment>
          reset mux_l
        </comment>
      </bits>
      <bits access="rw" name="reset_mux_r" pos="2" rst="0">
        <comment>
          reset mux_r
        </comment>
      </bits>
      <bits access="rw" name="reset_hp" pos="1" rst="0">
        <comment>
          reset hp
        </comment>
      </bits>
      <bits access="rw" name="reset_reci" pos="0" rst="0">
        <comment>
          reset receiver
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="Power_Ctrl">
      <bits access="r" name="Power_Ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="pu_ivref" pos="15" rst="0">
        <comment>
          power up ivref
        </comment>
      </bits>
      <bits access="rw" name="pu_vcombuf_b" pos="14" rst="0">
        <comment>
          power up vcombuf_b
        </comment>
      </bits>
      <bits access="rw" name="pu_vcombuf_c" pos="13" rst="0">
        <comment>
          power up vcombuf_c
        </comment>
      </bits>
      <bits access="rw" name="pu_vmic" pos="12:11" rst="0">
        <comment>
          power up vmic
        </comment>
      </bits>
      <bits access="rw" name="pu_micpga_l" pos="10" rst="0">
        <comment>
          power up micpga_l
        </comment>
      </bits>
      <bits access="rw" name="pu_micpga_r" pos="9" rst="0">
        <comment>
          power up micpga_r
        </comment>
      </bits>
      <bits access="rw" name="pu_adc_l" pos="8" rst="0">
        <comment>
          power up adc_l
        </comment>
      </bits>
      <bits access="rw" name="pu_adc_r" pos="7" rst="0">
        <comment>
          power up adc_r
        </comment>
      </bits>
      <bits access="rw" name="pu_dac_l" pos="6" rst="0">
        <comment>
          power up dac_l
        </comment>
      </bits>
      <bits access="rw" name="pu_dac_r" pos="5" rst="0">
        <comment>
          power up dac_r
        </comment>
      </bits>
      <bits access="rw" name="pu_mux_l" pos="4" rst="0">
        <comment>
          power up mux_l
        </comment>
      </bits>
      <bits access="rw" name="pu_mux_r" pos="3" rst="0">
        <comment>
          power up mux_r
        </comment>
      </bits>
      <bits access="rw" name="pu_vcombuf_capless_hp" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_reci_bias" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_reci_mpath" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="vref_cal">
      <bits access="r" name="vref_cal_reserved_0" pos="31:9" rst="0">
      </bits>
      <bits access="r" name="vref_cal_ready" pos="8" rst="0">
        <comment>
          vref calibration ready
        </comment>
      </bits>
      <bits access="rw" name="resetn_vref_cal_dr" pos="7" rst="1">
        <comment>
          vref calibration resetn control:
0: hardware automatic control
1: resetn_vref_cal_reg control
        </comment>
      </bits>
      <bits access="rw" name="resetn_vref_cal_reg" pos="6" rst="0">
        <comment>
          vref calibration resetn control register
        </comment>
      </bits>
      <bits access="rw" name="vref_cal_out_polarity" pos="5" rst="0">
        <comment>
          vref calibration output polarity selection
        </comment>
      </bits>
      <bits access="rw" name="vref_cal_clk_inv" pos="4" rst="0">
        <comment>
          vref calibration clock inversion
        </comment>
      </bits>
      <bits access="rw" name="vref_cal_bit_dr" pos="3" rst="0">
        <comment>
          1'b1: use vref_cal_bit_reg control_x000D_
1'b0: use hardware calibration logic control
        </comment>
      </bits>
      <bits access="rw" name="vref_cal_bit_reg" pos="2:0" rst="3">
        <comment>
          vref calibration bits to be adjusted 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="vrefc_cal">
      <bits access="r" name="vrefc_cal_reserved_0" pos="31:9" rst="0">
      </bits>
      <bits access="r" name="vrefc_cal_ready" pos="8" rst="0">
        <comment>
          vrefc calibration ready
        </comment>
      </bits>
      <bits access="rw" name="resetn_vrefc_cal_dr" pos="7" rst="0">
        <comment>
          vrefc calibration resetn control
0: hardware automatic control
1: resetn_vrefc_cal_reg control
        </comment>
      </bits>
      <bits access="rw" name="resetn_vrefc_cal_reg" pos="6" rst="1">
        <comment>
          vrefc calibration resetn control register
        </comment>
      </bits>
      <bits access="rw" name="vrefc_cal_out_polarity" pos="5" rst="0">
        <comment>
          vrefc calibration output polarity selection
        </comment>
      </bits>
      <bits access="rw" name="vrefc_cal_clk_inv" pos="4" rst="0">
        <comment>
          vrefc calibration clock inversion
        </comment>
      </bits>
      <bits access="rw" name="vrefc_cal_bit_dr" pos="3" rst="0">
        <comment>
          1'b1: use vrefc_cal_bit_reg control_x000D_
1'b0: use hardware calibration logic control
        </comment>
      </bits>
      <bits access="rw" name="vrefc_cal_bit_reg" pos="2:0" rst="3">
        <comment>
          vrefc calibration bits to be adjusted 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="vadc_cal">
      <bits access="r" name="vadc_cal_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="r" name="vadc_cal_ready" pos="9" rst="0">
        <comment>
          vadc calibration ready
        </comment>
      </bits>
      <bits access="rw" name="resetn_vadc_cal_dr" pos="8" rst="0">
        <comment>
          vadc calibration resetn control:
0: hardware automatic control
1: resetn_vadc_cal_reg control
        </comment>
      </bits>
      <bits access="rw" name="resetn_vadc_cal_reg" pos="7" rst="1">
        <comment>
          vadc calibration resetn control register
        </comment>
      </bits>
      <bits access="rw" name="vadc_cal_out_polarity" pos="6" rst="0">
        <comment>
          vadc calibration output polarity selection
        </comment>
      </bits>
      <bits access="rw" name="vadc_cal_clk_inv" pos="5" rst="0">
        <comment>
          vadc calibration clock inversion
        </comment>
      </bits>
      <bits access="rw" name="vadc_cal_bit_dr" pos="4" rst="0">
        <comment>
          1'b1: use vadc_cal_bit_reg control_x000D_
1'b0: use hardware calibration logic control
        </comment>
      </bits>
      <bits access="rw" name="vadc_cal_bit_reg" pos="3:0" rst="8">
        <comment>
          vadc calibration bits to be adjusted 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="vdac_cal">
      <bits access="r" name="vdac_cal_reserved_0" pos="31:9" rst="0">
      </bits>
      <bits access="r" name="vdac_cal_ready" pos="8" rst="0">
        <comment>
          vdac calibration ready
        </comment>
      </bits>
      <bits access="rw" name="resetn_vdac_cal_dr" pos="7" rst="0">
        <comment>
          vdac calibration resetn control:
0: hardware automatic control
1: resetn_vdac_cal_reg control
        </comment>
      </bits>
      <bits access="rw" name="resetn_vdac_cal_reg" pos="6" rst="1">
        <comment>
          vdac calibration resetn control register
        </comment>
      </bits>
      <bits access="rw" name="vdac_cal_out_polarity" pos="5" rst="0">
        <comment>
          vdac calibration output polarity selection
        </comment>
      </bits>
      <bits access="rw" name="vdac_cal_clk_inv" pos="4" rst="0">
        <comment>
          vdac calibration clock inversion
        </comment>
      </bits>
      <bits access="rw" name="vdac_cal_bit_dr" pos="3" rst="0">
        <comment>
          1'b1: use vdac_cal_bit_reg control_x000D_
1'b0: use hardware calibration logic control
        </comment>
      </bits>
      <bits access="rw" name="vdac_cal_bit_reg" pos="2:0" rst="3">
        <comment>
          vdac calibration bits to be adjusted 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aupll_setting1">
      <bits access="r" name="aupll_setting1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="aupll_ready" pos="15" rst="0">
        <comment>
          mpll ready signal
        </comment>
      </bits>
      <bits access="r" name="aupll_lock" pos="14" rst="0">
        <comment>
          mpll lock signal
        </comment>
      </bits>
      <bits access="rw" name="aupll_digreg_range" pos="13:10" rst="8">
      </bits>
      <bits access="rw" name="aupll_band_sel" pos="9:8" rst="1">
      </bits>
      <bits access="rw" name="aupll_ready_timer" pos="7:6" rst="1">
        <comment>
          add delay between power up pll and pll ready
2'b00:: 25us
2'b01:: 50us 
2'b10:: 100us 
2'b11:: 200us
        </comment>
      </bits>
      <bits access="rw" name="aupll_rstb_dr" pos="5" rst="0">
      </bits>
      <bits access="rw" name="aupll_rstb_reg" pos="4" rst="0">
      </bits>
      <bits access="rw" name="aupll_sel_dr" pos="3" rst="0">
      </bits>
      <bits access="rw" name="aupll_sel_reg" pos="2" rst="0">
      </bits>
      <bits access="rw" name="aupll_en_dr" pos="1" rst="0">
      </bits>
      <bits access="rw" name="aupll_en_reg" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="aupll_setting2">
      <bits access="r" name="aupll_setting2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="aupll_cpbias_rbit" pos="15:13" rst="4">
      </bits>
      <bits access="rw" name="aupll_cpbias_ibit" pos="12:9" rst="4">
      </bits>
      <bits access="rw" name="aupll_cpc2_bit" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="aupll_cpr2_bit" pos="5:3" rst="4">
      </bits>
      <bits access="rw" name="aupll_pcon_mode" pos="2" rst="0">
        <comment>
          division mode control
        </comment>
      </bits>
      <bits access="rw" name="aupll_refmulti2_en" pos="1" rst="1">
        <comment>
          double ref clk
        </comment>
      </bits>
      <bits access="rw" name="aupll_sdm_clk_sel" pos="0" rst="0">
        <comment>
          select clock to output as sdm_clk
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aupll_setting3">
      <bits access="r" name="aupll_setting3_reserved_0" pos="31:14" rst="0">
      </bits>
      <bits access="rw" name="aupll_rsvd_reg" pos="13:6" rst="1">
      </bits>
      <bits access="rw" name="aupll_testsig_sel" pos="5:4" rst="0">
      </bits>
      <bits access="rw" name="aupll_int_mode" pos="3" rst="0">
      </bits>
      <bits access="rw" name="aupll_vco_low_test" pos="2" rst="0">
        <comment>
          pull vco control voltage to avss
        </comment>
      </bits>
      <bits access="rw" name="aupll_vco_high_test" pos="1" rst="0">
        <comment>
          pull vco control voltage to avdd
        </comment>
      </bits>
      <bits access="rw" name="aupll_sdm_clk_test_en" pos="0" rst="0">
        <comment>
          select clock to output as clk2p_test
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aupll_sdm_setting">
      <bits access="r" name="aupll_sdm_setting_reserved_0" pos="31:7" rst="0">
      </bits>
      <bits access="rw" name="aupll_sdm_clk_inv" pos="6" rst="0">
        <comment>
          sdm feedback polarity select
1: inverter
0: normal
        </comment>
      </bits>
      <bits access="rw" name="aupll_sdm_resetn_dr" pos="5" rst="0">
      </bits>
      <bits access="rw" name="aupll_sdm_resetn_reg" pos="4" rst="0">
        <comment>
          sdm resetn
        </comment>
      </bits>
      <bits access="rw" name="aupll_sdm_int_dec_sel" pos="3:1" rst="3">
        <comment>
          3'b100:: integer 
3'b011:: 3bit: decimal
3'b010:: 2bit: decimal
3'b001:: 1bit: decimal
3'b000:: no: decimal
        </comment>
      </bits>
      <bits access="rw" name="aupll_sdm_dither_bypass" pos="0" rst="1">
        <comment>
          1: bypass dither 
0: not bypass dither
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aupll_sdm_freq_1">
      <bits access="r" name="aupll_sdm_freq_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="aupll_sdm_freq_high" pos="15:0" rst="30973">
        <comment>
          pll division ratio, integer part is bit 31 to bit 27, fraction part is bit 26 to bit 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aupll_sdm_freq_2">
      <bits access="r" name="aupll_sdm_freq_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="aupll_sdm_freq_low" pos="15:0" rst="21092">
        <comment>
          pll division ratio, integer part is bit 31 to bit 27, fraction part is bit 26 to bit 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="osc_and_doubler_cfg">
      <bits access="r" name="osc_and_doubler_cfg_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="rw" name="pu_osc26m" pos="9" rst="1">
      </bits>
      <bits access="rw" name="clkdblr_clk_en" pos="8" rst="1">
      </bits>
      <bits access="rw" name="clkdblr_r_ctrl" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="clkdblr_vbias_ctrl" pos="4:3" rst="0">
      </bits>
      <bits access="rw" name="clkdblr_ibias_ctrl" pos="2:1" rst="0">
      </bits>
      <bits access="rw" name="pu_clkdblr" pos="0" rst="1">
        <comment>
          power up clock doubler
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_micpga_div">
      <bits access="r" name="clk_micpga_div_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="rw" name="clk_micpga_div_base" pos="10:1" rst="512">
        <comment>
          micpga clock divider base
        </comment>
      </bits>
      <bits access="rw" name="clk_micpga_en" pos="0" rst="0">
        <comment>
          micpga clock enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_adc_vos_det_div">
      <bits access="r" name="clk_adc_vos_det_div_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="rw" name="clk_adc_vos_det_div_base" pos="10:1" rst="512">
        <comment>
          adc_vos_det clock divider base
        </comment>
      </bits>
      <bits access="rw" name="clk_adc_vos_det_div_en" pos="0" rst="0">
        <comment>
          adc_vos_det clock enable
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="abb_rsvd_status">
      <bits access="r" name="abb_rsvd_status_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="r" name="abb_status" pos="7:0" rst="0">
        <comment>
          abb reserved status
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="abb_rsvd_cfg_lo">
      <bits access="r" name="abb_rsvd_cfg_lo_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="abb_cfg_lo" pos="15:0" rst="0">
        <comment>
          abb reserved cfg lo 16 bit
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="abb_rsvd_cfg_hi">
      <bits access="r" name="abb_rsvd_cfg_hi_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="abb_cfg_hi" pos="15:0" rst="255">
        <comment>
          abb reserved cfg hi 16 bit
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="hp_chg_cfg">
      <bits access="r" name="hp_chg_cfg_reserved_0" pos="31:6" rst="0">
      </bits>
      <bits access="rw" name="hp_chg_res_bit" pos="5:4" rst="3">
        <comment>
          Change the resistance of the charging resistor
        </comment>
      </bits>
      <bits access="rw" name="hp_l_chg_resp_en" pos="3" rst="0">
        <comment>
          enable the method which charge the dc blocking capacitor to Vcom through a charging resistor
        </comment>
      </bits>
      <bits access="rw" name="hp_l_chg_resn_en" pos="2" rst="0">
      </bits>
      <bits access="rw" name="hp_r_chg_resp_en" pos="1" rst="0">
      </bits>
      <bits access="rw" name="hp_r_chg_resn_en" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="denoise_pwr_cfg">
      <bits access="r" name="denoise_pwr_cfg_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rw" name="hp_l_soft_start_en" pos="14" rst="0">
        <comment>
          enable the soft start up method of the left headphone amplifier
        </comment>
      </bits>
      <bits access="rw" name="hp_r_soft_start_en" pos="13" rst="0">
        <comment>
          enable the soft start up method of the right headphone amplifier
        </comment>
      </bits>
      <bits access="rw" name="pu_hp_l_mpath" pos="12" rst="0">
        <comment>
          power up the headphone amp.rest circuit of the left channel
        </comment>
      </bits>
      <bits access="rw" name="pu_hp_r_mpath" pos="11" rst="0">
        <comment>
          power up the headphone amp.rest circuit of the right channel
        </comment>
      </bits>
      <bits access="rw" name="pu_hp_l_bias" pos="10" rst="0">
        <comment>
          power up the headphone amp.bias circuit of the left channel
        </comment>
      </bits>
      <bits access="rw" name="pu_hp_r_bias" pos="9" rst="0">
        <comment>
          power up the headphone amp.bias circuit of the right channel
        </comment>
      </bits>
      <bits access="rw" name="pu_adc_det_l" pos="8" rst="0">
        <comment>
          power up the detection adc of the left channel
        </comment>
      </bits>
      <bits access="rw" name="pu_adc_det_r" pos="7" rst="0">
        <comment>
          power up the detection adc of the right channel
        </comment>
      </bits>
      <bits access="rw" name="pu_hp_l_dac_chg" pos="6" rst="0">
        <comment>
          power up the charging dac of the left channel
        </comment>
      </bits>
      <bits access="rw" name="pu_hp_r_dac_chg" pos="5" rst="0">
        <comment>
          power up the charging dac of the right channel
        </comment>
      </bits>
      <bits access="rw" name="vref_hp_ibit" pos="4" rst="0">
      </bits>
      <bits access="rw" name="hp_dac_chg_ibit" pos="3:0" rst="1">
        <comment>
          configure the gain of the charging dac according the capacitance of dc blocking capacitor
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_elimination_dac_clk_cfg">
      <bits access="r" name="denoise_elimination_dac_clk_cfg_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="rs" name="denoise_dac_clk_ld" pos="9" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          ld denoise dac clk div
        </comment>
      </bits>
      <bits access="rw" name="denoise_dac_clk_inv" pos="8:7" rst="0">
        <comment>
          denoise dac clk inverter
        </comment>
      </bits>
      <bits access="rw" name="denoise_dac_clk_div" pos="6:0" rst="80">
        <comment>
          denoise dac clk divider base
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_adc_clk_cfg">
      <bits access="r" name="denoise_adc_clk_cfg_reserved_0" pos="31:13" rst="0">
      </bits>
      <bits access="rs" name="denoise_adc_clk_ld" pos="12" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          ld denoise adc clk div
        </comment>
      </bits>
      <bits access="rw" name="denoise_adc_clk_inv" pos="11:10" rst="0">
        <comment>
          denoise adc clk inverter
        </comment>
      </bits>
      <bits access="rw" name="denoise_adc_clk_div" pos="9:0" rst="1000">
        <comment>
          denoise adc clk divider base
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_ramp_cfg_l">
      <bits access="r" name="denoise_ramp_cfg_l_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ramp_done_l" pos="15" rst="0">
        <comment>
          indicate left channel denoise ramp is finish
        </comment>
      </bits>
      <bits access="rw" name="adc_det_th_l" pos="14:11" rst="7">
        <comment>
          left channel adc detection threshold
        </comment>
      </bits>
      <bits access="rw" name="rampdown_en_l" pos="10" rst="0">
        <comment>
          enable denoise module ramp down function
        </comment>
      </bits>
      <bits access="rw" name="rampup_cycle_l" pos="9:6" rst="1">
        <comment>
          set rampup cycle, step is 512 dac clock cycle
        </comment>
      </bits>
      <bits access="rw" name="stable_time_l" pos="5:1" rst="1">
        <comment>
          set denoise module stable time before ramp down, step is 1024 dac clock cycle
        </comment>
      </bits>
      <bits access="rw" name="start_denoise_l" pos="0" rst="0">
        <comment>
          start denoise procedure
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_rampup_cfg_l">
      <bits access="r" name="denoise_rampup_cfg_l_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="rampup_th_value_l" pos="11:0" rst="0">
        <comment>
          denoise rampup threshold value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_rampdown_cfg_l">
      <bits access="r" name="denoise_rampdown_cfg_l_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="rampdown_final_value_l" pos="11:0" rst="0">
        <comment>
          denoise rampdown final value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_ramp_cfg_r">
      <bits access="r" name="denoise_ramp_cfg_r_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ramp_done_r" pos="15" rst="0">
        <comment>
          indicate right channel denoise ramp is finish
        </comment>
      </bits>
      <bits access="rw" name="adc_det_th_r" pos="14:11" rst="7">
        <comment>
          right channel adc detection threshold
        </comment>
      </bits>
      <bits access="rw" name="rampdown_en_r" pos="10" rst="0">
        <comment>
          enable denoise module ramp down function
        </comment>
      </bits>
      <bits access="rw" name="rampup_cycle_r" pos="9:6" rst="1">
        <comment>
          set rampup cycle, step is 512 dac clock cycle
        </comment>
      </bits>
      <bits access="rw" name="stable_time_r" pos="5:1" rst="1">
        <comment>
          set denoise module stable time before ramp down, step is 1024 dac clock cycle
        </comment>
      </bits>
      <bits access="rw" name="start_denoise_r" pos="0" rst="0">
        <comment>
          start denoise procedure
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_rampup_cfg_r">
      <bits access="r" name="denoise_rampup_cfg_r_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="rampup_th_value_r" pos="11:0" rst="0">
        <comment>
          denoise rampup threshold value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_rampdown_cfg_r">
      <bits access="r" name="denoise_rampdown_cfg_r_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="rampdown_final_value_r" pos="11:0" rst="0">
        <comment>
          denoise rampdown final value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="denoise_other_cfg">
      <bits access="r" name="denoise_other_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="hp_dischg_res_bit" pos="11:10" rst="3">
        <comment>
          change the resistance of the pulldown resistor
        </comment>
      </bits>
      <bits access="rw" name="hp_l_dischg_resp_en" pos="9" rst="0">
        <comment>
          pull down the inside node voltage of the dc blocking capacitor of the left channel through a pull down resistor
        </comment>
      </bits>
      <bits access="rw" name="hp_l_dischg_resn_en" pos="8" rst="0">
      </bits>
      <bits access="rw" name="hp_r_dischg_resp_en" pos="7" rst="0">
        <comment>
          pull down the inside node voltage of the dc blocking capacitor of the right channel through a pull down resistor
        </comment>
      </bits>
      <bits access="rw" name="hp_r_dischg_resn_en" pos="6" rst="0">
      </bits>
      <bits access="rw" name="hp_l_pullup_en" pos="5" rst="0">
        <comment>
          pull up the inside node voltage of the dc blocking capacitor of left channel through a pulldown resistor
        </comment>
      </bits>
      <bits access="rw" name="hp_r_pullup_en" pos="4" rst="0">
        <comment>
          pull up the inside node voltage of the dc blocking capacitor of right channel through a pulldown resistor
        </comment>
      </bits>
      <bits access="rw" name="hp_l_idac_chg_mode" pos="3" rst="0">
      </bits>
      <bits access="rw" name="hp_l_idac_dischg_mode" pos="2" rst="0">
      </bits>
      <bits access="rw" name="hp_r_idac_chg_mode" pos="1" rst="0">
      </bits>
      <bits access="rw" name="hp_r_idac_dischg_mode" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="reci_chg_cfg">
      <bits access="r" name="reci_chg_cfg_reserved_0" pos="31:6" rst="0">
      </bits>
      <bits access="rw" name="reci_chg_res_bit" pos="5:4" rst="3">
      </bits>
      <bits access="rw" name="reci_chg_res_en" pos="3" rst="0">
      </bits>
      <bits access="rw" name="reci_dischg_res_bit" pos="2:1" rst="3">
      </bits>
      <bits access="rw" name="reci_dischg_res_en" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="reset_control">
      <bits access="r" name="reset_control_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="rw" name="denoise_l_resetn" pos="3" rst="1">
        <comment>
          reset left channel denoise module, low active
        </comment>
      </bits>
      <bits access="rw" name="denoise_r_resetn" pos="2" rst="1">
        <comment>
          reset right channel denoise module, low active
        </comment>
      </bits>
      <bits access="rw" name="Register_resetn" pos="1" rst="1">
        <comment>
          Reset register file
0: reset
        </comment>
      </bits>
      <bits access="rw" name="Soft_resetn" pos="0" rst="1">
        <comment>
          System software reset
0: reset
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mpll_setting1">
      <bits access="r" name="mpll_setting1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="mpll_ready" pos="15" rst="0">
        <comment>
          mpll ready signal
        </comment>
      </bits>
      <bits access="r" name="mpll_lock" pos="14" rst="0">
        <comment>
          mpll lock signal
        </comment>
      </bits>
      <bits access="rw" name="mpll_digreg_range" pos="13:10" rst="8">
      </bits>
      <bits access="rw" name="mpll_band_sel" pos="9:8" rst="1">
      </bits>
      <bits access="rw" name="mpll_ready_timer" pos="7:6" rst="1">
        <comment>
          add delay between power up pll and pll ready
2'b00:: 25us
2'b01:: 50us 
2'b10:: 100us 
2'b11:: 200us
        </comment>
      </bits>
      <bits access="rw" name="mpll_rstb_dr" pos="5" rst="0">
      </bits>
      <bits access="rw" name="mpll_rstb_reg" pos="4" rst="0">
      </bits>
      <bits access="rw" name="mpll_sel_dr" pos="3" rst="0">
      </bits>
      <bits access="rw" name="mpll_sel_reg" pos="2" rst="0">
      </bits>
      <bits access="rw" name="mpll_en_dr" pos="1" rst="0">
      </bits>
      <bits access="rw" name="mpll_en_reg" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="mpll_setting2">
      <bits access="r" name="mpll_setting2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="mpll_cpbias_rbit" pos="15:13" rst="4">
      </bits>
      <bits access="rw" name="mpll_cpbias_ibit" pos="12:9" rst="4">
      </bits>
      <bits access="rw" name="mpll_cpc2_bit" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="mpll_cpr2_bit" pos="5:3" rst="4">
      </bits>
      <bits access="rw" name="mpll_pcon_mode" pos="2" rst="0">
        <comment>
          division mode control
        </comment>
      </bits>
      <bits access="rw" name="mpll_refmulti2_en" pos="1" rst="1">
        <comment>
          double ref clk
        </comment>
      </bits>
      <bits access="rw" name="mpll_sdm_clk_sel" pos="0" rst="0">
        <comment>
          select clock to output as sdm_clk
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mpll_setting3">
      <bits access="r" name="mpll_setting3_reserved_0" pos="31:14" rst="0">
      </bits>
      <bits access="rw" name="mpll_rsvd_reg" pos="13:6" rst="1">
      </bits>
      <bits access="rw" name="mpll_testsig_sel" pos="5:4" rst="0">
      </bits>
      <bits access="rw" name="mpll_int_mode" pos="3" rst="0">
      </bits>
      <bits access="rw" name="mpll_vco_low_test" pos="2" rst="0">
        <comment>
          pull vco control voltage to avss
        </comment>
      </bits>
      <bits access="rw" name="mpll_vco_high_test" pos="1" rst="0">
        <comment>
          pull vco control voltage to avdd
        </comment>
      </bits>
      <bits access="rw" name="mpll_sdm_clk_test_en" pos="0" rst="0">
        <comment>
          select clock to output as clk2p_test
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mpll_sdm_setting">
      <bits access="r" name="mpll_sdm_setting_reserved_0" pos="31:7" rst="0">
      </bits>
      <bits access="rw" name="mpll_sdm_clk_inv" pos="6" rst="0">
        <comment>
          sdm feedback polarity select
1: inverter
0: normal
        </comment>
      </bits>
      <bits access="rw" name="mpll_sdm_resetn_dr" pos="5" rst="0">
      </bits>
      <bits access="rw" name="mpll_sdm_resetn_reg" pos="4" rst="0">
        <comment>
          sdm resetn
        </comment>
      </bits>
      <bits access="rw" name="mpll_sdm_int_dec_sel" pos="3:1" rst="3">
        <comment>
          3'b100:: integer 
3'b011:: 3bit: decimal
3'b010:: 2bit: decimal
3'b001:: 1bit: decimal
3'b000:: no: decimal
        </comment>
      </bits>
      <bits access="rw" name="mpll_sdm_dither_bypass" pos="0" rst="1">
        <comment>
          1: bypass dither 
0: not bypass dither
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mpll_sdm_freq_1">
      <bits access="r" name="mpll_sdm_freq_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="mpll_sdm_freq_high" pos="15:0" rst="13233">
        <comment>
          pll division ratio, integer part is bit 31 to bit 27, fraction part is bit 26 to bit 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mpll_sdm_freq_2">
      <bits access="r" name="mpll_sdm_freq_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="mpll_sdm_freq_low" pos="15:0" rst="15123">
        <comment>
          pll division ratio, integer part is bit 31 to bit 27, fraction part is bit 26 to bit 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="io_clktest">
      <bits access="r" name="io_clktest_reserved_0" pos="31:6" rst="0">
      </bits>
      <bits access="rw" name="io_clktest_mux_sel_bit" pos="5:2" rst="0">
      </bits>
      <bits access="rw" name="io_clktest_mux2_en" pos="1" rst="0">
      </bits>
      <bits access="rw" name="io_clktest_mux1_en" pos="0" rst="0">
      </bits>
    </reg>
  </module>
</archive>

<archive relative="aif.xml">
  <module name="aif" category="Audio">
    <reg protect="rw" name="data">
      <bits access="rw" name="data1" pos="31:16" rst="0">
        <comment>
          This reg contains data to be read or written by IFC. In mono mode, data1 is after data0. In stereo mode, data1 is in right channel.
        </comment>
      </bits>
      <bits access="rw" name="data0" pos="15:0" rst="0">
        <comment>
          This reg contains data to be read or written by IFC. In mono mode, data0 is before data1. In stereo mode, data0 is in left channel.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ctrl">
      <bits access="rw" name="loop_back" pos="31" rst="0">
        <comment>
          Sets the loop back mode. The feature is for debug only and can not work in DAI mode.
0:: NORMAL
1:: LOOPBACK
        </comment>
      </bits>
      <bits access="r" name="ctrl_reserved_0" pos="30:18" rst="0">
      </bits>
      <bits access="r" name="in_overflow" pos="17" rst="0">
        <comment>
        bit type is changed from rc to r.

          This bit indicates if the AIF had received some data while the Input Fifo was full. If the Fifo In is full, the newly received data will be lost. 
Write one to clear the in_overflow status bit. This bit is auto clear.
        </comment>
      </bits>
      <bits access="r" name="out_underflow" pos="16" rst="0">
        <comment>
        bit type is changed from rc to r.

          This bit indicates if the AIF had needed some data while the Out Fifo was empty. In case of data famine, the last available data will be sent again. 
Write one to clear the out_underflow status bit. This bit is auto clear.
        </comment>
      </bits>
      <bits access="r" name="ctrl_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="tx_stb_mode" pos="12" rst="0">
        <comment>
          In parallel mode, select AIF Tx Strobe mode. Reserved in serial mode. 
0:: TX_STB_MID:     edge is in middle of data. 
1:: TX_STB_ALIGN: edge is aligned to data edge.
        </comment>
      </bits>
      <bits access="rc" name="parallel_in_clr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Selects parallel audio interface connected to analog front-end. 
0:: SERL :serial input. 
1:: PARA:  parallel input.
        </comment>
      </bits>
      <bits access="rs" name="parallel_in_set" pos="10" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          Selects parallel audio interface connected to analog front-end. 
0:: SERL: serial input. 
1:: PARA:  parallel input.
        </comment>
      </bits>
      <bits access="rc" name="parallel_out_clr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Selects parallel audio interface connected to analog front-end. 
0:: SERL: serial output. 
1:: PARA: parallel output.
        </comment>
      </bits>
      <bits access="rs" name="parallel_out_set" pos="8" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          Selects parallel audio interface connected to analog front-end. 
0:: SERL: serial output. 
1:: PARA:  parallel output.
        </comment>
      </bits>
      <bits access="r" name="ctrl_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="tx_off" pos="4" rst="0">
        <comment>
          Disable AIF Tx functions. Important:: if you want to do record only, you must set this bit otherwise AIF state machine will not start. 
0:: TX_ON:    Both Tx Rx enabled. 
1:: TX_OFF:   Rx enabled only, Tx disabled.
        </comment>
      </bits>
      <bits access="r" name="ctrl_reserved_3" pos="3:1" rst="0">
      </bits>
      <bits access="rw" name="enable" pos="0" rst="0">
        <comment>
          Audio Interface Enable. 
0:: DISABLE:    if AIF_Tone[0] is also 0, AIF is disabled. 
1:: ENABLE:      AIF Enabled. If AIF_Tone[0] is also '1', Tx fifo continue to fetch and distribute data from IFC when tone is enable. However, these data are not used.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="serial_ctrl">
      <bits access="r" name="serial_ctrl_reserved_0" pos="31:29" rst="0">
      </bits>
      <bits access="rw" name="bckout_gate" pos="28" rst="0">
        <comment>
          Sets the BckOut gating. This bit decide if AIF continue to output BCK clock after 16-bit data has been sent.
0:: NO_GATE
1:: GATED
        </comment>
      </bits>
      <bits access="r" name="serial_ctrl_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="input_half_cycle_dly" pos="26" rst="0">
        <comment>
          delayed Audio input data by half cycle.
0:: NO_DLY
1:: DLY
        </comment>
      </bits>
      <bits access="rw" name="output_half_cycle_dly" pos="25" rst="0">
        <comment>
          delayed Audio output data or LRCK by half cycle.
0:: NO_DLY
1:: DLY

        </comment>
      </bits>
      <bits access="rw" name="bck_pol" pos="24" rst="0">
        <comment>
          if Master Mode, invert BCLK out. if slave Mode, invert BCLK in.
0:: NORMAL
1:: INVERT
        </comment>
      </bits>
      <bits access="r" name="serial_ctrl_reserved_2" pos="23:21" rst="0">
      </bits>
      <bits access="rw" name="bck_lrck" pos="20:16" rst="0">
        <comment>
          configure the ratio of BCK and LRCK cycle from 16 to 31. 
Voice_Mode:: "XXXX":: each sample takes 16 + "XXXX" BCLK cycle. 
Audio_Mode:: "XXXX":: each sample takes 2*(16 + "XXXX) BCLK cycle. 2 times than Voice Mode because in audio mode each sample occupies two channels.
0::   BCK_LRCK_16
1::   BCK_LRCK_17
2::   BCK_LRCK_18
3::   BCK_LRCK_19
4::   BCK_LRCK_20
5::   BCK_LRCK_21
6::   BCK_LRCK_22
7::   BCK_LRCK_23
8::   BCK_LRCK_24
9::   BCK_LRCK_25
10:: BCK_LRCK_26
11:: BCK_LRCK_27
12:: BCK_LRCK_28
13:: BCK_LRCK_29
14:: BCK_LRCK_30
15:: BCK_LRCK_31
16:: BCK_LRCK_32
17:: BCK_LRCK_33
18:: BCK_LRCK_34
19:: BCK_LRCK_35
20:: BCK_LRCK_36
21:: BCK_LRCK_37
22:: BCK_LRCK_38
23:: BCK_LRCK_39
24:: BCK_LRCK_40
25:: BCK_LRCK_41
26:: BCK_LRCK_42
27:: BCK_LRCK_43
28:: BCK_LRCK_44
29:: BCK_LRCK_45
30:: BCK_LRCK_46
31:: BCK_LRCK_47


        </comment>
      </bits>
      <bits access="r" name="serial_ctrl_reserved_3" pos="15" rst="0">
      </bits>
      <bits access="rw" name="rx_mode" pos="14" rst="0">
        <comment>
          Configure mono or stereo format for Audio data in. 
0:: STEREO_STEREO:              stereo input from pin, stereo output to IFC. 
1:: STEREO_MONO_FROM_L:  stereo input from pin, mono input to IFC selected from left channel. 
Users can change LRCK polarity to choose mono input from right channel.
        </comment>
      </bits>
      <bits access="rw" name="tx_mode" pos="13:12" rst="0">
        <comment>
          Configure mono or stereo format for Audio data out. This field is used both in serial mode or in parallel EXT mode. 
2'b00:: STEREO_STEREO:               stereo input from IFC, stereo output to pin. 
2'b01:: MONO_STEREO_CHAN_L:   mono input from IFC, stereo output in left channel to pin. This value is reserved in parallel EXT mode. 
2'b10:: MONO_STEREO_DUPLI:       mono input from IFC, stereo output duplicate in both channels to pin. 
2'b11:: STEREO_TO_MONO:            stereo input from IFC, mono output to left and right channel. This mode is only used for parallel stereo interface. 

if AIF works in DAI or Voice mode, always select "00" mode STEREO_STEREO.
        </comment>
      </bits>
      <bits access="rw" name="tx_dly_s" pos="11" rst="0">
        <comment>
          ONLY for slave mode:: configure 1 cycle supplementary Tx delay. 
0:: NO_DLY:  No supplementary Tx delay. 
1:: DLY:         One Cycle supplementary Tx delay.
        </comment>
      </bits>
      <bits access="rw" name="tx_dly" pos="10" rst="0">
        <comment>
          configure the delay between serial data out MSB and LRCK edge. 
0:: ALIGN:           Digital audio out MSB is aligned with LRCLK edge. 
1:: DLY_1:          Digital audio out MSB is 1 cycle delayed to LRCLK edge
        </comment>
      </bits>
      <bits access="rw" name="rx_dly" pos="9:8" rst="0">
        <comment>
          Indicates the delay between serial data in MSB and LRCK edge. 
2'b00:: ALIGN:    Digital audio in MSB is aligned with LRCLK edge. 
2'b01:: DLY_1:   Digital audio in MSB is 1 cycle delayed to LRCLK edge. 
2'b10:: DLY_2:   Digital audio in MSB is 2 cycle delayed to LRCLK edge. 
2'b11:: DLY_3:   Digital audio in MSB is 3 cycle delayed to LRCLK edge.
        </comment>
      </bits>
      <bits access="r" name="serial_ctrl_reserved_4" pos="7" rst="0">
      </bits>
      <bits access="rw" name="lrck_pol" pos="6" rst="0">
        <comment>
          configure LRCK polarity. 
0:: LEFT_H_RIGHT_L:    high level on LRCK means left channel, low level on LRCK means right channel. 
1:: LEFT_L_RIGHT_H:    high level on LRCK means right channel, low level on LRCK means left channel. 

Note: this bit should be set to '0' (LEFT_H_RIGHT_L) in voice mode.
        </comment>
      </bits>
      <bits access="rw" name="lsb" pos="5" rst="0">
        <comment>
          When high, the output data format is with the least significant bit first.
0:: MSB
1:: LSB

        </comment>
      </bits>
      <bits access="rw" name="master_mode" pos="4" rst="1">
        <comment>
          configure AIF works in master mode (LRCLK and BCK timing signals are generated internally) or slave mode (LRCLK and BCK timing signals are generated externally).
0:: SLAVE
1:: MASTER

        </comment>
      </bits>
      <bits access="rw" name="i2s_in_sel" pos="3:2" rst="0">
        <comment>
          Select AIF I2S input.
0:: I2S_IN_0
1:: I2S_IN_1
2:: I2S_IN_2

        </comment>
      </bits>
      <bits access="rw" name="serial_mode" pos="1:0" rst="0">
        <comment>
          Configure serial AIF mode. 
0:: I2S_PCM
1:: VOICE
2:: DAI
3:: Reserved
When mode is set DAI, the bit Master Mode should be set to '1', bit Endian_L set to '0'. Data should be sent out on falling edge, which requires either Bclk_Pol = '0' and Half_Cycle_DLY = '1' or Bclk_Pol = '1' and Half_Cycle_DLY = '0'. Bits Tx_DLY and BCKOut_Gate must be configured to '0' and '1'. 
The DAI mode must NOT be modified after AIF is enabled. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tone">
      <bits access="r" name="tone_reserved_0" pos="31:14" rst="0">
      </bits>
      <bits access="rw" name="tone_gain" pos="13:12" rst="0">
        <comment>
          Tone attenuation. The Comfort Tone or DTMF is attenuated according to this programmable gain.
0:: 0_dB
1:: m3_dB
2:: m9_dB
3:: m15_dB
        </comment>
      </bits>
      <bits access="r" name="tone_reserved_1" pos="11:10" rst="0">
      </bits>
      <bits access="rw" name="comfort_freq" pos="9:8" rst="0">
        <comment>
          Frequency of comfort tone.
0:: 425_Hz
1:: 950_Hz
2:: 1400_Hz
3:: 1800_Hz
        </comment>
      </bits>
      <bits access="rw" name="dtmf_freq_row" pos="7:6" rst="0">
        <comment>
          Frequency of the second DTMF sine wave.
0:: 697_Hz
1:: 770_Hz
2:: 852_Hz
3:: 941_Hz
        </comment>
      </bits>
      <bits access="rw" name="dtmf_freq_col" pos="5:4" rst="0">
        <comment>
          Frequency of the first DTMF sine wave.
0:: 1209_Hz
1:: 1336_Hz
2:: 1477_Hz
3:: 1633_Hz
        </comment>
      </bits>
      <bits access="r" name="tone_reserved_2" pos="3:2" rst="0">
      </bits>
      <bits access="rw" name="tone_select" pos="1" rst="0">
        <comment>
          Select whether a DTMF of a comfort tone is generated.
0:: DTMF
1:: COMFORT_TONE
        </comment>
      </bits>
      <bits access="rw" name="enable_h" pos="0" rst="0">
        <comment>
          When this bit is set, the audio interface is enabled and a comfort tone or DTMF tone is output on the audio interface instead of the regular data, even if the AIF_CTRL[0] enable bit is 0. 
0:: DISABLE:    
AIF is disabled if the AIF_CTRL[0] is also 0. 
1:: ENABLE:    
 AIF is enabled and generates a tone.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="side_tone">
      <bits access="r" name="side_tone_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="rw" name="side_tone_gain" pos="3:0" rst="0">
        <comment>
          Side Tone attenuation. The side tone is attenuated according to this programmable gain. 
4'b0000:: mute. 
4'b0001:: M36_dB
4'b0010:: M33_dB 
4'b0011:: M30_dB 
4'b0100:: M27_dB 
4'b0101:: M24_dB 
4'b0110:: M21_dB 
4'b0111:: M18_dB 
4'b1000:: M15_dB 
4'b1001:: M12_dB 
4'b1010:: M9_dB 
4'b1011:: M6_dB 
4'b1100:: M3_dB 
4'b1101:: 0_dB 
4'b1110:: 3_dB 
4'b1111:: 6_dB
        </comment>
      </bits>
    </reg>

    <reg protect="rw" name="lod_postion">
      <bits access="r" name="load_postion_reserved_1" pos="31:14" rst="0">
      </bits>
      <bits access="rw" name="tx_load_pos" pos="13:8" rst="0">
        <comment>
        </comment>
      </bits>
      <bits access="r" name="load_postion_reserved_0" pos="7:4" rst="0">
      </bits>
      <bits access="rw" name="rx_load_pos" pos="3:0" rst="0">
        <comment>
        </comment>
      </bits>
  </reg>

 <reg protect="rw" name="fm_record_enable">
    <bits access="rw" name="fm_lr_swap" pos="4" rst="0">
        <comment>i2s slave mode, receive shift data load position.
        </comment>
    </bits> 
    <bits access="rw" name="fm_record_en" pos="0" rst="0">
        <comment>i2s slave mode, receive shift data load position.
        </comment>
    </bits>
</reg>

  </module>
</archive>

<archive relative="aud_ifc.xml">
  <module name="aud_ifc" category="Audio">
    <reg protect="w" name="ch_0__control">
      <bits access="w" name="control_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="w" name="auto_disable" pos="4" rst="0">
        <comment>
          Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.
        </comment>
      </bits>
      <bits access="w" name="control_reserved_1" pos="3:2" rst="0">
      </bits>
      <bits access="w" name="disable" pos="1" rst="0">
        <comment>
          Channel Disable, write one in this bit disable the channel. 
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled.
        </comment>
      </bits>
      <bits access="w" name="enable" pos="0" rst="0">
        <comment>
          Channel Enable, write one in this bit enable the channel. 
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="ch_0__status">
      <bits access="r" name="status_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="r" name="i3_4f" pos="19" rst="0">
        <comment>
          Three Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="i4f" pos="18" rst="0">
        <comment>
          Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ihf" pos="17" rst="0">
        <comment>
          Half of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ief" pos="16" rst="0">
        <comment>
          End of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="r" name="cause_i3_4f" pos="11" rst="0">
        <comment>
          Cause interrupt Three Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_i4f" pos="10" rst="0">
        <comment>
          Cause interrupt Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ihf" pos="9" rst="0">
        <comment>
          Cause interrupt Half of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ief" pos="8" rst="0">
        <comment>
          Cause interrupt End of FIFO.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>
          When 1 the fifo is empty
        </comment>
      </bits>
      <bits access="r" name="status_reserved_3" pos="3:2" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="1" rst="0">
      </bits>
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>
          When 1 the channel is enabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ch_0__start_addr">
      <bits access="rw" name="start_addr" pos="31:2" rst="1073741823">
        <comment>
          AHB Start Address. This field represent the start address of the FIFO located in RAM.
        </comment>
      </bits>
      <bits access="r" name="start_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_0__fifo_size">
      <bits access="r" name="fifo_size_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rw" name="fifo_size" pos="14:4" rst="2047">
        <comment>
          Fifo size in bytes, max 32kBytes. 
The size of the fifo must be a multiple of 16 (The four LSB are always zero).
        </comment>
      </bits>
      <bits access="r" name="fifo_size_reserved_1" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch_0__reserved">
      <bits access="r" name="reserved_reserved_0" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_0__int_mask">
      <bits access="r" name="int_mask_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
          THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="quarter_fifo" pos="10" rst="0">
        <comment>
          QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="half_fifo" pos="9" rst="0">
        <comment>
          HALF FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="end_fifo" pos="8" rst="0">
        <comment>
          END FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="r" name="int_mask_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_0__int_clear">
      <bits access="r" name="int_clear_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rc" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Three Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="quarter_fifo" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="half_fifo" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear half of fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="end_fifo" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear end of fifo interrupt.
        </comment>
      </bits>
      <bits access="r" name="int_clear_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch_0__cur_ahb_addr">
      <bits access="r" name="cur_ahb_addr" pos="31:2" rst="1073741823">
        <comment>
          Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.
        </comment>
      </bits>
      <bits access="r" name="cur_ahb_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="w" name="ch_1__control">
      <bits access="w" name="control_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="w" name="auto_disable" pos="4" rst="0">
        <comment>
          Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.
        </comment>
      </bits>
      <bits access="w" name="control_reserved_1" pos="3:2" rst="0">
      </bits>
      <bits access="w" name="disable" pos="1" rst="0">
        <comment>
          Channel Disable, write one in this bit disable the channel. 
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled.
        </comment>
      </bits>
      <bits access="w" name="enable" pos="0" rst="0">
        <comment>
          Channel Enable, write one in this bit enable the channel. 
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="ch_1__status">
      <bits access="r" name="status_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="r" name="i3_4f" pos="19" rst="0">
        <comment>
          Three Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="i4f" pos="18" rst="0">
        <comment>
          Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ihf" pos="17" rst="0">
        <comment>
          Half of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ief" pos="16" rst="0">
        <comment>
          End of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="r" name="cause_i3_4f" pos="11" rst="0">
        <comment>
          Cause interrupt Three Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_i4f" pos="10" rst="0">
        <comment>
          Cause interrupt Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ihf" pos="9" rst="0">
        <comment>
          Cause interrupt Half of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ief" pos="8" rst="0">
        <comment>
          Cause interrupt End of FIFO.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>
          When 1 the fifo is empty
        </comment>
      </bits>
      <bits access="r" name="status_reserved_3" pos="3:2" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="1" rst="0">
      </bits>
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>
          When 1 the channel is enabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ch_1__start_addr">
      <bits access="rw" name="start_addr" pos="31:2" rst="1073741823">
        <comment>
          AHB Start Address. This field represent the start address of the FIFO located in RAM.
        </comment>
      </bits>
      <bits access="r" name="start_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_1__fifo_size">
      <bits access="r" name="fifo_size_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rw" name="fifo_size" pos="14:4" rst="2047">
        <comment>
          Fifo size in bytes, max 32kBytes. 
The size of the fifo must be a multiple of 16 (The four LSB are always zero).
        </comment>
      </bits>
      <bits access="r" name="fifo_size_reserved_1" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch_1__reserved">
      <bits access="r" name="reserved_reserved_0" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_1__int_mask">
      <bits access="r" name="int_mask_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
          THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="quarter_fifo" pos="10" rst="0">
        <comment>
          QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="half_fifo" pos="9" rst="0">
        <comment>
          HALF FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="end_fifo" pos="8" rst="0">
        <comment>
          END FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="r" name="int_mask_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_1__int_clear">
      <bits access="r" name="int_clear_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rc" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Three Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="quarter_fifo" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="half_fifo" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear half of fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="end_fifo" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear end of fifo interrupt.
        </comment>
      </bits>
      <bits access="r" name="int_clear_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch_1__cur_ahb_addr">
      <bits access="r" name="cur_ahb_addr" pos="31:2" rst="1073741823">
        <comment>
          Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.
        </comment>
      </bits>
      <bits access="r" name="cur_ahb_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="w" name="ch_2__control">
      <bits access="w" name="control_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="w" name="auto_disable" pos="4" rst="0">
        <comment>
          Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.
        </comment>
      </bits>
      <bits access="w" name="control_reserved_1" pos="3:2" rst="0">
      </bits>
      <bits access="w" name="disable" pos="1" rst="0">
        <comment>
          Channel Disable, write one in this bit disable the channel. 
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled.
        </comment>
      </bits>
      <bits access="w" name="enable" pos="0" rst="0">
        <comment>
          Channel Enable, write one in this bit enable the channel. 
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="ch_2__status">
      <bits access="r" name="status_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="r" name="i3_4f" pos="19" rst="0">
        <comment>
          Three Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="i4f" pos="18" rst="0">
        <comment>
          Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ihf" pos="17" rst="0">
        <comment>
          Half of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ief" pos="16" rst="0">
        <comment>
          End of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="r" name="cause_i3_4f" pos="11" rst="0">
        <comment>
          Cause interrupt Three Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_i4f" pos="10" rst="0">
        <comment>
          Cause interrupt Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ihf" pos="9" rst="0">
        <comment>
          Cause interrupt Half of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ief" pos="8" rst="0">
        <comment>
          Cause interrupt End of FIFO.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>
          When 1 the fifo is empty
        </comment>
      </bits>
      <bits access="r" name="status_reserved_3" pos="3:2" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="1" rst="0">
      </bits>
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>
          When 1 the channel is enabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ch_2__start_addr">
      <bits access="rw" name="start_addr" pos="31:2" rst="1073741823">
        <comment>
          AHB Start Address. This field represent the start address of the FIFO located in RAM.
        </comment>
      </bits>
      <bits access="r" name="start_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_2__fifo_size">
      <bits access="r" name="fifo_size_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rw" name="fifo_size" pos="14:4" rst="2047">
        <comment>
          Fifo size in bytes, max 32kBytes. 
The size of the fifo must be a multiple of 16 (The four LSB are always zero).
        </comment>
      </bits>
      <bits access="r" name="fifo_size_reserved_1" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch_2__reserved">
      <bits access="r" name="reserved_reserved_0" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_2__int_mask">
      <bits access="r" name="int_mask_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
          THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="quarter_fifo" pos="10" rst="0">
        <comment>
          QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="half_fifo" pos="9" rst="0">
        <comment>
          HALF FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="end_fifo" pos="8" rst="0">
        <comment>
          END FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="r" name="int_mask_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch_2__int_clear">
      <bits access="r" name="int_clear_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rc" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Three Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="quarter_fifo" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="half_fifo" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear half of fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="end_fifo" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear end of fifo interrupt.
        </comment>
      </bits>
      <bits access="r" name="int_clear_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch_2__cur_ahb_addr">
      <bits access="r" name="cur_ahb_addr" pos="31:2" rst="1073741823">
        <comment>
          Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.
        </comment>
      </bits>
      <bits access="r" name="cur_ahb_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
  </module>
</archive>

<archive relative="audio_codec.xml">
  <module name="audio_codec" category="Audio">
    <reg protect="r" name="audio_function_id">
      <bits access="r" name="audio_function_id_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="fid" pos="15:0" rst="52716">
        <comment>
          Function ID
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="codec_cfg">
      <bits access="r" name="codec_cfg_reserved_0" pos="31:9" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="fm_clk_sel" pos="8" rst="0">
        <comment>
         audio_codec clk cel 
0:: clk_codec
1:: clk_fm          
        </comment>
      </bits>      
      <bits access="rw" name="s_codec_en" pos="7" rst="0">
        <comment>
          Codec Enable
1:: enable codec dsp
        </comment>
      </bits>
      <bits access="rw" name="dac_test_mode" pos="6" rst="0">
        <comment>
          dac input is controlled by dac test input registers under dac test mode
1:: dac test mode
0:: normal mode
        </comment>
      </bits>
      <bits access="rw" name="sleep_mode" pos="5" rst="0">
        <comment>
          Sleep Mode
1:: Sleep mode 
0:: Normal mode
        </comment>
      </bits>
      <bits access="rw" name="fm_mode" pos="4" rst="0">
        <comment>
          Audio FM Mode
0:: codec mode
1:: FM mode;
        </comment>
      </bits>
      <bits access="rw" name="s_dac_1k" pos="3" rst="0">
        <comment>
          DAC 1K Sine Wave Test
        </comment>
      </bits>
      <bits access="rw" name="s_loop" pos="2" rst="0">
        <comment>
          Loop Test
        </comment>
      </bits>
      <bits access="rw" name="s_phone_sel" pos="1" rst="0">
        <comment>
          Phone Selection
        </comment>
      </bits>
      <bits access="rw" name="s_isphone" pos="0" rst="0">
        <comment>
          Phone Mode
1: phone in/out
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="adc_cfg1">
      <bits access="r" name="adc_cfg1_reserved_0" pos="31:15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="s_adc_en" pos="14" rst="0">
        <comment>
          enable adc
        </comment>
      </bits>
      <bits access="rw" name="adc_out_format" pos="13" rst="0">
        <comment>
          0:: mono output(left channel)
1:: stereo output 
        </comment>
      </bits>
      <bits access="rw" name="dig_mic_switch" pos="12" rst="0">
        <comment>
          switch dig mic L/R channel signal
        </comment>
      </bits>
      <bits access="rw" name="adc_dig_sel" pos="11" rst="0">
        <comment>
          select dig mic input for adc path
1:: select digital mic input
        </comment>
      </bits>
      <bits access="rw" name="adc_path_reset" pos="10" rst="0">
        <comment>
          ADC Path Reset
1:: Reset
        </comment>
      </bits>
      <bits access="rw" name="ana_adc_clk_inv" pos="9" rst="0">
        <comment>
          Analog ADC Clock Inverter
1: ADC clock inverted
        </comment>
      </bits>
      <bits access="rw" name="adc_clkgen_mode" pos="8" rst="1">
        <comment>
          ADC Clock Generation Mode
1:: codec generate adc clock internally
0:: codec generate adc clock based on dac path strobe(current not support)
        </comment>
      </bits>
      <bits access="rw" name="cnt_adc_clk_int" pos="7:1" rst="24">
        <comment>
          ADC Clock Divider Integer
divider number for Audio CODEC clock div to ADC clock; Integer part
        </comment>
      </bits>
      <bits access="rs" name="adc_clk_ld" pos="0" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          load adc clock divider value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="adc_cfg2">
      <bits access="r" name="adc_cfg2_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="s_adc_volume_l" pos="15:12" rst="7">
        <comment>
          Left ADC Volume
MIC Gain:
4'h0:: mute
4'h1:: -12dB
4'hF:: 16dB
Step is 2dB
        </comment>
      </bits>
      <bits access="rw" name="s_adc_volume_r" pos="11:8" rst="7">
        <comment>
          Right ADC Volume
MIC Gain:
4'h0:: mute
4'h1:: -12dB
4'hF:: 16dB
Step is 2dB
        </comment>
      </bits>
      <bits access="rw" name="adc_hpf_bypass_l" pos="7" rst="1">
        <comment>
          ADC HPF Bypass for left channel
        </comment>
      </bits>
      <bits access="rw" name="adc_lpf_bypass_l" pos="6" rst="1">
        <comment>
          ADC LPF Bypass for left channel
        </comment>
      </bits>
      <bits access="rw" name="adc_hpf_bypass_r" pos="5" rst="1">
        <comment>
          ADC HPF Bypass for right channel
        </comment>
      </bits>
      <bits access="rw" name="adc_lpf_bypass_r" pos="4" rst="1">
        <comment>
          ADC LPF Bypass for right channel
        </comment>
      </bits>
      <bits access="rw" name="s_adc_osr_sel" pos="3:0" rst="0">
        <comment>
          ADC OSR Select
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_cfg1">
      <bits access="r" name="dac_cfg1_reserved_0" pos="31:15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="s_dac_en" pos="14" rst="0">
        <comment>
          enable dac
        </comment>
      </bits>
      <bits access="rw" name="dac_path_reset" pos="13" rst="0">
        <comment>
          DAC Path Reset
        </comment>
      </bits>
      <bits access="rw" name="ana_dac_clk_inv" pos="12" rst="0">
        <comment>
          Analog DAC Clock Inverter
1:: DAC clock inverted
        </comment>
      </bits>
      <bits access="rw" name="dac_clkgen_mode" pos="11" rst="1">
        <comment>
          DAC Clock Generation Mode
1:: codec generate dac clock internally
0:: codec generate dac clock based on dac path strobe(current not support)
        </comment>
      </bits>
      <bits access="rw" name="fs_cnt_int" pos="10:1" rst="24">
        <comment>
          Sample Rate Divider Counter integer part
        </comment>
      </bits>
      <bits access="rs" name="dac_clk_ld" pos="0" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          load dac clock divider value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_cfg2">
      <bits access="r" name="dac_cfg2_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="s_dac_osr_sel" pos="15:14" rst="0">
        <comment>
          DAC OSR Select
2'b00:: 128 OSR
2'b01:: 256 OSR
2'b10:: 512 OSR
2'b11:: 1024 OSR
        </comment>
      </bits>
      <bits access="rw" name="s_dac_gain" pos="13:12" rst="0">
        <comment>
          DAC Gain
unit is 6dB
        </comment>
      </bits>
      <bits access="rw" name="s_dac_volume_l" pos="11:6" rst="49">
        <comment>
          left DAC Volume
6'h0:: mute(s_dac_gain should be 2'b00)
6'h1:: -60dB test mode(s_dac_gain should be 2'b00)
6'h2:: -25dB
6'h3F:: 5.5dB
Step is 0.5dB
        </comment>
      </bits>
      <bits access="rw" name="s_dac_volume_r" pos="5:0" rst="49">
        <comment>
          right DAC Volume
6'h0:: mute(s_dac_gain should be 2'b00)
6'h1:: -60dB test mode(s_dac_gain should be 2'b00)
6'h2:: -25dB
6'h3F:: 5.5dB
Step is 0.5dB
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_cfg3">
      <bits access="r" name="dac_cfg3_reserved_0" pos="31:15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="s_mute_l" pos="14" rst="0">
        <comment>
          DAC Mute Left
1:: mute DAC left channel output
        </comment>
      </bits>
      <bits access="rw" name="s_mute_r" pos="13" rst="0">
        <comment>
          DAC Mute Right
1:: mute DAC right channel output
        </comment>
      </bits>
      <bits access="rw" name="s_dac_volume_mute" pos="12" rst="0">
        <comment>
          DAC Volume Mute
1: mute both DAC Left &amp; Right channels
        </comment>
      </bits>
      <bits access="rw" name="s_dwa_en" pos="11" rst="1">
        <comment>
          DWA Enable
1:: enable DWA
        </comment>
      </bits>
      <bits access="rw" name="s_dither_bypass" pos="10" rst="0">
        <comment>
          Dither Bypass
1:: bypass dither
        </comment>
      </bits>
      <bits access="rw" name="dither_gain" pos="9:5" rst="8">
        <comment>
          SDM Dither Gain
        </comment>
      </bits>
      <bits access="rw" name="sdm_gain" pos="4:3" rst="2">
        <comment>
          SDM Gain
        </comment>
      </bits>
      <bits access="rw" name="s_fs_sel" pos="2:0" rst="0">
        <comment>
          DAC Ramp Sample Rate Select
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_ramp">
      <bits access="r" name="dac_ramp_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="ramp_ind" pos="15" rst="0">
        <comment>
          DAC Ramp Indicator
        </comment>
      </bits>
      <bits access="rw" name="ramp_bypass" pos="14" rst="1">
        <comment>
          DAC Ramp Bypass
        </comment>
      </bits>
      <bits access="rw" name="rampup_step" pos="13:7" rst="10">
        <comment>
          DAC Ramp Up Step
        </comment>
      </bits>
      <bits access="rw" name="rampdn_step" pos="6:0" rst="3">
        <comment>
          DAC Ramp Down Step
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="side_tone_cfg">
      <bits access="r" name="side_tone_cfg_reserved_0" pos="31:13" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="side_tone_en" pos="12" rst="0">
        <comment>
          enable side tone
        </comment>
      </bits>
      <bits access="rw" name="side_tone_sel_l" pos="11" rst="0">
        <comment>
          select side tone source for left channel
1'b0:: left mic
1'b1:: right mic
        </comment>
      </bits>
      <bits access="rw" name="side_tone_sel_r" pos="10" rst="0">
        <comment>
          select side tone source for right channel
1'b0:: left mic
1'b1:: right mic
        </comment>
      </bits>
      <bits access="rw" name="s_adc_dvst_ctl_l" pos="9:5" rst="15">
        <comment>
          Left Channel Side Tone Gain
5'b11111:: disable side tone
5'b00000:: 0dB
5'b11110:: -60dB
Step is 2dB
        </comment>
      </bits>
      <bits access="rw" name="s_adc_dvst_ctl_r" pos="4:0" rst="15">
        <comment>
          Right Channel Side Tone Gain
5'b11111:: disable side tone
5'b00000:: 0dB
5'b11110:: -60dB
Step is 2dB
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="test_ctrl">
      <bits access="r" name="test_ctrl_reserved_0" pos="31:7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="tports_out_sel" pos="6" rst="0">
        <comment>
          1: output high 16bit of tports
0: output low 16bit of tports
        </comment>
      </bits>
      <bits access="rw" name="tports_en" pos="5" rst="0">
        <comment>
          Test Ports Enable
        </comment>
      </bits>
      <bits access="rw" name="tports_sel" pos="4:0" rst="0">
        <comment>
          Test Ports Selection
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="test_port_lo">
      <bits access="r" name="test_port_lo_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="tports_lo" pos="15:0" rst="0">
        <comment>
          Test Ports low 16 bit
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="test_port_hi">
      <bits access="r" name="test_port_hi_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="tports_hi" pos="15:0" rst="0">
        <comment>
          Test Ports high 16 bit
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_ctrl">
      <bits access="r" name="eq_ctrl_reserved_0" pos="31:3" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_clock_div_bypass" pos="2" rst="0">
        <comment>
          bypass eq clock divider when eq is not used
        </comment>
      </bits>
      <bits access="rw" name="eq_bypass" pos="1" rst="1">
        <comment>
          eq bypass
        </comment>
      </bits>
      <bits access="rw" name="eq_reset" pos="0" rst="1">
        <comment>
          reset eq module
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef0_low">
      <bits access="r" name="eq_coef0_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef0_lo" pos="15:0" rst="0">
        <comment>
          1st stage EQ B0 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef0_high">
      <bits access="r" name="eq_coef0_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef0_hi" pos="7:0" rst="0">
        <comment>
          1st stage EQ B0 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef1_low">
      <bits access="r" name="eq_coef1_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef1_lo" pos="15:0" rst="0">
        <comment>
          1st stage EQ B1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef1_high">
      <bits access="r" name="eq_coef1_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef1_hi" pos="7:0" rst="0">
        <comment>
          1st stage EQ B1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef2_low">
      <bits access="r" name="eq_coef2_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef2_lo" pos="15:0" rst="0">
        <comment>
          1st stage EQ A1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef2_high">
      <bits access="r" name="eq_coef2_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef2_hi" pos="7:0" rst="0">
        <comment>
          1st stage EQ A1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef3_low">
      <bits access="r" name="eq_coef3_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef3_lo" pos="15:0" rst="0">
        <comment>
          1st stage EQ B2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef3_high">
      <bits access="r" name="eq_coef3_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef3_hi" pos="7:0" rst="0">
        <comment>
          1st stage EQ B2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef4_low">
      <bits access="r" name="eq_coef4_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef4_lo" pos="15:0" rst="0">
        <comment>
          1st stage EQ A2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef4_high">
      <bits access="r" name="eq_coef4_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef4_hi" pos="7:0" rst="0">
        <comment>
          1st stage EQ A2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef5_low">
      <bits access="r" name="eq_coef5_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef5_lo" pos="15:0" rst="0">
        <comment>
          2nd stage EQ B0 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef5_high">
      <bits access="r" name="eq_coef5_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef5_hi" pos="7:0" rst="0">
        <comment>
          2nd stage EQ B0 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef6_low">
      <bits access="r" name="eq_coef6_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef6_lo" pos="15:0" rst="0">
        <comment>
          2nd stage EQ B1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef6_high">
      <bits access="r" name="eq_coef6_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef6_hi" pos="7:0" rst="0">
        <comment>
          2nd stage EQ B1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef7_low">
      <bits access="r" name="eq_coef7_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef7_lo" pos="15:0" rst="0">
        <comment>
          2nd stage EQ A1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef7_high">
      <bits access="r" name="eq_coef7_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef7_hi" pos="7:0" rst="0">
        <comment>
          2nd stage EQ A1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef8_low">
      <bits access="r" name="eq_coef8_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef8_lo" pos="15:0" rst="0">
        <comment>
          2nd stage EQ B2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef8_high">
      <bits access="r" name="eq_coef8_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef8_hi" pos="7:0" rst="0">
        <comment>
          2nd stage EQ B2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef9_low">
      <bits access="r" name="eq_coef9_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef9_lo" pos="15:0" rst="0">
        <comment>
          2nd stage EQ A2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef9_high">
      <bits access="r" name="eq_coef9_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef9_hi" pos="7:0" rst="0">
        <comment>
          2nd stage EQ A2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef10_low">
      <bits access="r" name="eq_coef10_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef10_lo" pos="15:0" rst="0">
        <comment>
          3rd stage EQ B0 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef10_high">
      <bits access="r" name="eq_coef10_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef10_hi" pos="7:0" rst="0">
        <comment>
          3rd stage EQ B0 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef11_low">
      <bits access="r" name="eq_coef11_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef11_lo" pos="15:0" rst="0">
        <comment>
          3rd stage EQ B1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef11_high">
      <bits access="r" name="eq_coef11_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef11_hi" pos="7:0" rst="0">
        <comment>
          3rd stage EQ B1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef12_low">
      <bits access="r" name="eq_coef12_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef12_lo" pos="15:0" rst="0">
        <comment>
          3rd stage EQ A1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef12_high">
      <bits access="r" name="eq_coef12_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef12_hi" pos="7:0" rst="0">
        <comment>
          3rd stage EQ A1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef13_low">
      <bits access="r" name="eq_coef13_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef13_lo" pos="15:0" rst="0">
        <comment>
          3rd stage EQ B2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef13_high">
      <bits access="r" name="eq_coef13_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef13_hi" pos="7:0" rst="0">
        <comment>
          3rd stage EQ B2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef14_low">
      <bits access="r" name="eq_coef14_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef14_lo" pos="15:0" rst="0">
        <comment>
          3rd stage EQ A2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef14_high">
      <bits access="r" name="eq_coef14_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef14_hi" pos="7:0" rst="0">
        <comment>
          3rd stage EQ A2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef15_low">
      <bits access="r" name="eq_coef15_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef15_lo" pos="15:0" rst="0">
        <comment>
          4th stage EQ B0 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef15_high">
      <bits access="r" name="eq_coef15_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef15_hi" pos="7:0" rst="0">
        <comment>
          4th stage EQ B0 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef16_low">
      <bits access="r" name="eq_coef16_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef16_lo" pos="15:0" rst="0">
        <comment>
          4th stage EQ B1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef16_high">
      <bits access="r" name="eq_coef16_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef16_hi" pos="7:0" rst="0">
        <comment>
          4th stage EQ B1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef17_low">
      <bits access="r" name="eq_coef17_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef17_lo" pos="15:0" rst="0">
        <comment>
          4th stage EQ A1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef17_high">
      <bits access="r" name="eq_coef17_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef17_hi" pos="7:0" rst="0">
        <comment>
          4th stage EQ A1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef18_low">
      <bits access="r" name="eq_coef18_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef18_lo" pos="15:0" rst="0">
        <comment>
          4th stage EQ B2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef18_high">
      <bits access="r" name="eq_coef18_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef18_hi" pos="7:0" rst="0">
        <comment>
          4th stage EQ B2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef19_low">
      <bits access="r" name="eq_coef19_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef19_lo" pos="15:0" rst="0">
        <comment>
          4th stage EQ A2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef19_high">
      <bits access="r" name="eq_coef19_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef19_hi" pos="7:0" rst="0">
        <comment>
          4th stage EQ A2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef20_low">
      <bits access="r" name="eq_coef20_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef20_lo" pos="15:0" rst="0">
        <comment>
          5th stage EQ B0 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef20_high">
      <bits access="r" name="eq_coef20_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef20_hi" pos="7:0" rst="0">
        <comment>
          5th stage EQ B0 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef21_low">
      <bits access="r" name="eq_coef21_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef21_lo" pos="15:0" rst="0">
        <comment>
          5th stage EQ B1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef21_high">
      <bits access="r" name="eq_coef21_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef21_hi" pos="7:0" rst="0">
        <comment>
          5th stage EQ B1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef22_low">
      <bits access="r" name="eq_coef22_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef22_lo" pos="15:0" rst="0">
        <comment>
          5th stage EQ A1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef22_high">
      <bits access="r" name="eq_coef22_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef22_hi" pos="7:0" rst="0">
        <comment>
          5th stage EQ A1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef23_low">
      <bits access="r" name="eq_coef23_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef23_lo" pos="15:0" rst="0">
        <comment>
          5th stage EQ B2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef23_high">
      <bits access="r" name="eq_coef23_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef23_hi" pos="7:0" rst="0">
        <comment>
          5th stage EQ B2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef24_low">
      <bits access="r" name="eq_coef24_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef24_lo" pos="15:0" rst="0">
        <comment>
          5th stage EQ A2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef24_high">
      <bits access="r" name="eq_coef24_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef24_hi" pos="7:0" rst="0">
        <comment>
          5th stage EQ A2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef25_low">
      <bits access="r" name="eq_coef25_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef25_lo" pos="15:0" rst="0">
        <comment>
          6th stage EQ B0 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef25_high">
      <bits access="r" name="eq_coef25_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef25_hi" pos="7:0" rst="0">
        <comment>
          6th stage EQ B0 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef26_low">
      <bits access="r" name="eq_coef26_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef26_lo" pos="15:0" rst="0">
        <comment>
          6th stage EQ B1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef26_high">
      <bits access="r" name="eq_coef26_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef26_hi" pos="7:0" rst="0">
        <comment>
          6th stage EQ B1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef27_low">
      <bits access="r" name="eq_coef27_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef27_lo" pos="15:0" rst="0">
        <comment>
          6th stage EQ A1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef27_high">
      <bits access="r" name="eq_coef27_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef27_hi" pos="7:0" rst="0">
        <comment>
          6th stage EQ A1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef28_low">
      <bits access="r" name="eq_coef28_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef28_lo" pos="15:0" rst="0">
        <comment>
          6th stage EQ B2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef28_high">
      <bits access="r" name="eq_coef28_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef28_hi" pos="7:0" rst="0">
        <comment>
          6th stage EQ B2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef29_low">
      <bits access="r" name="eq_coef29_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef29_lo" pos="15:0" rst="0">
        <comment>
          6th stage EQ A2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef29_high">
      <bits access="r" name="eq_coef29_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef29_hi" pos="7:0" rst="0">
        <comment>
          6th stage EQ A2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef30_low">
      <bits access="r" name="eq_coef30_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef30_lo" pos="15:0" rst="0">
        <comment>
          7th stage EQ B0 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef30_high">
      <bits access="r" name="eq_coef30_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef30_hi" pos="7:0" rst="0">
        <comment>
          7th stage EQ B0 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef31_low">
      <bits access="r" name="eq_coef31_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef31_lo" pos="15:0" rst="0">
        <comment>
          7th stage EQ B1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef31_high">
      <bits access="r" name="eq_coef31_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef31_hi" pos="7:0" rst="0">
        <comment>
          7th stage EQ B1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef32_low">
      <bits access="r" name="eq_coef32_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef32_lo" pos="15:0" rst="0">
        <comment>
          7th stage EQ A1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef32_high">
      <bits access="r" name="eq_coef32_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef32_hi" pos="7:0" rst="0">
        <comment>
          7th stage EQ A1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef33_low">
      <bits access="r" name="eq_coef33_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef33_lo" pos="15:0" rst="0">
        <comment>
          7th stage EQ B2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef33_high">
      <bits access="r" name="eq_coef33_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef33_hi" pos="7:0" rst="0">
        <comment>
          7th stage EQ B2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef34_low">
      <bits access="r" name="eq_coef34_low_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef34_lo" pos="15:0" rst="0">
        <comment>
          7th stage EQ A2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eq_coef34_high">
      <bits access="r" name="eq_coef34_high_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="eq_coef34_hi" pos="7:0" rst="0">
        <comment>
          7th stage EQ A2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="coef_a1_lo">
      <bits access="r" name="coef_a1_lo_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="hpf_coef_a1_lo" pos="15:0" rst="0">
        <comment>
          adc hpf a1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="coef_a1_hi">
      <bits access="r" name="coef_a1_hi_reserved_0" pos="31:4" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="hpf_coef_a1_hi" pos="3:0" rst="0">
        <comment>
          adc hpf a1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="coef_a2_lo">
      <bits access="r" name="coef_a2_lo_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="hpf_coef_a2_lo" pos="15:0" rst="0">
        <comment>
          adc hpf a2 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="coef_a2_hi">
      <bits access="r" name="coef_a2_hi_reserved_0" pos="31:4" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="hpf_coef_a2_hi" pos="3:0" rst="0">
        <comment>
          adc hpf a2 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="coef_b1_lo">
      <bits access="r" name="coef_b1_lo_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="hpf_coef_b1_lo" pos="15:0" rst="0">
        <comment>
          adc hpf b1 coef lo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="coef_b1_hi">
      <bits access="r" name="coef_b1_hi_reserved_0" pos="31:4" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="hpf_coef_b1_hi" pos="3:0" rst="0">
        <comment>
          adc hpf b1 coef hi
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_test_input_l_lo">
      <bits access="r" name="dac_test_input_l_lo_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dac_tst_in_l_lo" pos="15:0" rst="0">
        <comment>
          dac test input lo 16bit for left channel
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_test_input_l_hi">
      <bits access="r" name="dac_test_input_l_hi_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dac_tst_in_l_hi" pos="7:0" rst="0">
        <comment>
          dac test input hi 8bit for left channel
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_test_input_r_lo">
      <bits access="r" name="dac_test_input_r_lo_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dac_tst_in_r_lo" pos="15:0" rst="0">
        <comment>
          dac test input lo 16bit for right channel
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_test_input_r_hi">
      <bits access="r" name="dac_test_input_r_hi_reserved_0" pos="31:8" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dac_tst_in_r_hi" pos="7:0" rst="0">
        <comment>
          dac test input hi 8bit for right channel
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_l_dc_cancelling">
      <bits access="r" name="dac_l_dc_cancelling_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dac_l_dc_offset" pos="15:0" rst="0">
        <comment>
          dac left channel dc offset
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_r_dc_cancelling">
      <bits access="r" name="dac_r_dc_cancelling_reserved_0" pos="31:16" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dac_r_dc_offset" pos="15:0" rst="0">
        <comment>
          dac right channel dc offset
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative = "bb2g_ram.xml">
  <var name="BB2G_RAM_SIZE"   value="32*4096" />    

  
  <module name="bb2g_ram" category="Baseband">
    <memory name="ram_array" size="BB2G_RAM_SIZE">
      <comment>BB2G Ram Space
        <br/> This RAM is used in 2G mode as ACC buffer and code space.
        <br/> In NB mode, it can also be used as TCM memory space.
      </comment>
    </memory>
  </module>


</archive>
<archive relative = "bb_cp2.xml">
<module name="bb_cp2" category="Baseband">
    <reg name="ctrl" protect="rw">
        <bits name="First Poly" pos="2:0" access="rw" rst="0x7" display="hex">
            <comment>This field is used for setting the first polynomial to encode 
                     or the CRC computation
                    <br/>First polynomial to encode :
                    <br/>000 = G0
                    <br/>001 = G1
                    <br/>010 = G2
                    <br/>011 = G3
                    <br/>100 = G4
                    <br/>101 = G5
                    <br/>110 = G6
                    <br/>111 = No polynomial code used (input connected to output)
                    <br/>Cyclic code :
                    <br/>000 = D8 + D4 + D3 + D2 + 1
                    <br/>001 = D3 + D + 1
                    <br/>010 = D14 + D13 + D5 + D3 + D2 +1
                    <br/>011 = D6 + D5 + D3 + D2 + D1 + 1
                    <br/>100 = D10 + D8 + D6 + D5 + D4 + D2 + 1
                    <br/>101 = D16 + D12 + D5 + 1
                    <br/>110 = (D23 + 1)*(D17 + D3 + 1)
                    <br/>111 = reserved
            </comment>
        </bits>
        <bits name="Second Poly" pos="5:3" access="rw" rst="0x7" display="hex">
            <comment>Second polynomial to encode :
                    <br/>000 = G0
                    <br/>001 = G1
                    <br/>010 = G2
                    <br/>011 = G3
                    <br/>100 = G4
                    <br/>101 = G5
                    <br/>110 = G6
                    <br/>111 = No polynomial code used (input connected to output)
            </comment>
        </bits>
        <bits name="Third Poly" pos="8:6" access="rw" rst="0x7" display="hex">
            <comment>Third polynomial to encode:
                    <br/>000 = G0
                    <br/>001 = G1
                    <br/>010 = G2
                    <br/>011 = G3
                    <br/>100 = G4
                    <br/>101 = G5
                    <br/>110 = G6
                    <br/>111 = No polynomial code used (input connected to output)
            </comment>
        </bits>
        <bits name="Fourth Poly" pos="11:9" access="rw" rst="0x7" display="hex">
            <comment>Fourth polynomial to encode:
                    <br/>000 = G0
                    <br/>001 = G1
                    <br/>010 = G2
                    <br/>011 = G3
                    <br/>100 = G4
                    <br/>101 = G5
                    <br/>110 = G6
                    <br/>111 = No polynomial code used (input connected to output)
            </comment>
        </bits>
        <bits name="Fith Poly" pos="14:12" access="rw" rst="0x7" display="hex">
            <comment>Fith polynomial to encode:
                    <br/>000 = G0
                    <br/>001 = G1
                    <br/>010 = G2
                    <br/>011 = G3
                    <br/>100 = G4
                    <br/>101 = G5
                    <br/>110 = G6
                    <br/>111 = No polynomial code used (input connected to output)
            </comment>
        </bits>
        <bits name="Sixth Poly" pos="17:15" access="rw" rst="0x7" display="hex">
            <comment>Sixth polynomial to encode:
                    <br/>000 = G0
                    <br/>001 = G1
                    <br/>010 = G2
                    <br/>011 = G3
                    <br/>100 = G4
                    <br/>101 = G5
                    <br/>110 = G6
                    <br/>111 = No polynomial code used (input connected to output)
            </comment>
        </bits>
        <bits name="RSC Poly" pos="20:18" access="rw" rst="0x7" display="hex">
            <comment>RSC (Recursive Systematic Convolutional) polynomial code:
                    <br/>000 = G0
                    <br/>001 = G1
                    <br/>010 = G2
                    <br/>011 = G3
                    <br/>100 = G4
                    <br/>101 = G5
                    <br/>110 = G6
                    <br/>111 = No RSC
            </comment>
        </bits>
        <bits name="NB Poly" pos="23:21" access="rw" rst="0x7" display="hex">
            <comment>Number of polynomial code to process:
                    <br/>0x0 = 0
                    <br/>0x1 = 1 (First Poly)
                    <br/>0x2 = 2 (First poly and second Poly)
                    <br/>0x3 = 3 (First poly, second poly, third Poly)
                    <br/>0x6 = 6 (first Poly to sixth Poly)
                    <br/>0x7 = reserved
            </comment>
        </bits>
        <bits name="Enable Puncturing" pos="24" access="rw" rst="1">
            <comment>Enable Puncturing
                    <br/>0 = No puncturing (puncturing disabled)
                    <br/>1 = Enable puncturing
            </comment>
        </bits>
    </reg>
    
    <reg name="bit number" protect="rw">
        <bits name="Bit number" pos="8:0" access="rw" rst="0x1FF" display="hex">
            <comment>Number of inputs bits to process
                <br/>0x01 = 1
                <br/>0x02 = 2
                <br/>0x03 = 3
                <br/>...
                <br/>0xFD = 253
                <br/>0xFE = 254
                <br/>0xFF = 255
                <br/>0x100 = 256
                <br/>...
                <br/>0x1BF = 447
                <br/>0x1C0 = 448
            </comment>
        </bits>
    </reg>
    
    <reg name="Status" protect="r">
        <bits name="Enable" pos="0:0" access="r" rst="0">
            <comment>When 1 the bb_cp2 is running
            </comment>
        </bits>
    </reg>
    
    <reg name="lram_addr" protect="rw">
        <bits name="LRAM Address" pos="4:0" access="rw" rst="0x0" display="hex">
            <comment>LRAM address for the next access
                <br/>Automatically incremented after each access
            </comment>
        </bits>
        <bits name="LRAM Select" pos="5" access="rw" rst="0x1">
            <comment>Select LRAM for the next access
                <br/>0 = Puncturing LRAM
                <br/>1 = Data LRAM
            </comment>
        </bits>
    </reg>

    <reg name="CRC code LSB" protect="r">
        <bits name="CRC code" pos="31:0" access="r" rst="0xFFFFFFFF" display="hex">
            <comment>CRC code LSB bits
            </comment>
        </bits>
    </reg>

    <reg name="CRC code MSB" protect="r">
        <bits name="CRC code" pos="7:0" access="r" rst="0x03" display="hex">
            <comment>CRC code MSB bits
            </comment>
        </bits>
    </reg>
    
    <hole size="800" />
    
    <reg name="CP2_Select_REG" protect="rw">
        <bits name="CP2 Select" pos="0" access="rw" rst="1">
            <comment>CP2 register access selection bit
                <br/>0= All registers are only accessible through the APB bus
                <br/>1= All registers are only accessible by the BCPU through the CP2 bus
            </comment>
        </bits>
    </reg>

    <reg name="LRAM_Data_REG" protect="rw">
        <bits name="LRAM Data" pos="31:0" access="rw" rst="no" display="hex">
            <comment>LRAM Data. This register is used for access to the 
                     puncturing LRAM or to the Data LRAM.
                <br/>All access into this register, increment the LRAM_ADDR register.
            </comment>
        </bits>
    </reg>

</module>

<cjoker>
// changing xml generated defines
#undef BB_CP2_ENABLE_PUNCTURING
#undef BB_CP2_LRAM_DATA
#undef BB_CP2_BIT_NUMBER

#define BB_CP2_ENABLE_PUNCTURING(n) (((n)&amp;1)&lt;&lt;24)

/// BB_CP2 address mapping
#define BB_CP2_CTRL                              0
#define BB_CP2_BIT_NUMBER                        1
#define BB_CP2_STATUS                            2
#define BB_CP2_LRAM_ADDR                         3
#define BB_CP2_CRC_CODE_LSB                      4
#define BB_CP2_CRC_CODE_MSB                      5
#define BB_CP2_LRAM_DATA                         0
#define BB_CP2_LRAM_PUNC                         (0&lt;&lt;5)
#define BB_CP2_DATA_LRAM                         (1&lt;&lt;5)

/* BB_CP2 ACCESSES */
// macro for converting a constant to a string
#define CT_CONVERT_TO_STRING(x) #x
// control register -> GPR
#define CT_BB_CP2_RD_CTRL_REG(regaddr, n)       asm volatile("cfc2 %0, $" CT_CONVERT_TO_STRING(regaddr) :"=r"((n)))
//              GPR -> control register
#define CT_BB_CP2_WR_CTRL_REG(regaddr, n)       asm volatile("ctc2 %0, $" CT_CONVERT_TO_STRING(regaddr) ::"r"((n)))
// general register -> GPR
#define CT_BB_CP2_RD_GNRL_REG_GPR(regaddr, n)   asm volatile("mfc2 %0, $" CT_CONVERT_TO_STRING(regaddr) :"=r"((n)))
//              GPR -> general register
#define CT_BB_CP2_WR_GNRL_REG_GPR(regaddr, n)   asm volatile("mtc2 %0, $" CT_CONVERT_TO_STRING(regaddr) ::"r"((n)))
// general register -> memory
#define CT_BB_CP2_RD_GNRL_REG_MEM(regaddr, out)	asm volatile("swc2 $" CT_CONVERT_TO_STRING(regaddr) ", 0(%0)"::"r"((out)))
//           memory -> general register
#define CT_BB_CP2_WR_GNRL_REG_MEM(regaddr, in) 	asm volatile("lwc2 $" CT_CONVERT_TO_STRING(regaddr) ", 0(%0)"::"r"((in)))


</cjoker>

</archive>
<archive relative = "bb_irq.xml">

<include file="globals.xml"/>

<module name="bb_irq" category="Baseband">
    
    
    <enum name="BCPU_Irq_Lines">
        <entry name="BCpu_Main_Irq_Line"><comment>BCPU Irq Lines</comment></entry>
        
        <entry name="BCpu_Debug_Irq_Line" value="4"/>
        <entry name="BCpu_Host_Irq_Line"/>
    </enum>


    <reg name="Cause" protect="r">
        <comment>If cause is not null and interrupt are enabled then the interrupt line 0 is driven on the system CPU.
            <br/>The cause for the Irq sources, one bit for each module's irq source.
            <br/>The cause is the actual Irq source masked by the mask register.
        </comment>
        <bits name="Cause" pos="BB_NB_IRQ-1:0" access="r" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>

    <hole size="32" />

    <reg name="Status" protect="r">
        <comment>The status for the level Irq sources, one bit for each module's irq source.
            <br/>The status reflect the actual Irq source.
        </comment>
        <bits name="Status" pos="BB_NB_IRQ-1:0" access="r" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>

    <hole size="32" />

    <reg name="Mask_Set" protect="rw">
        <comment>Writing '1' sets the corresponding bit in the mask register to '1'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Mask_Set" pos="BB_NB_IRQ-1:0" access="rs" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>

    <hole size="32" />

    <reg name="Mask_Clear" protect="rw">
        <comment>Writing '1' clears the corresponding bit in the mask register to '0'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Mask_Clr" pos="BB_NB_IRQ-1:0" access="rc" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>

    <hole size="32" />

    <reg name="NonMaskable" protect="rw">
        <bits name="Main_IRQ" pos="10" access="r" rst="0">
            <comment>This is the Main Irq source it drive the system CPU interrupt line 0.
                <br/>This bit comes from the modules irq and is masked by the Mask and SC registers.
            </comment>
        </bits>
        
        <bits name="Debug_IRQ" pos="14" access="rw" rst="0">
            <comment>This is the debug Irq source, the value written here drives the system CPU interrupt line 4.
            </comment>
        </bits>
        <bits name="Host_IRQ" pos="15" access="r" rst="0">
            <comment>This is the Host Irq source it drive the system CPU interrupt line 5.
                <br/>This bit is controlled by the host internal register.
            </comment>
        </bits>
        <bits name="IntEnable_Status" pos="31" access="r" rst="1">
            <comment>Status of the Interrupt enable semaphore bit.
            </comment>
        </bits>
   </reg>
    <reg name="SC" protect="">
        <bits name="IntEnable" pos="0" access="rw" rst="1">
            <comment>Interrupt enable semaphore, used for critical section.
                <br/>Read returns its value and then clears it to '0' disabling interrupts.
                <br/>Write the read value to restore the previous state, this will exit the critical section.
            </comment>
        </bits>
    </reg>
    <reg name="WakeUp_Mask" protect="rw">
        <comment>Each bit to '1' in that registers allows the correcponding interrupt to wake up the System CPU (i.e.: Reenable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section)
        </comment>
        <bits name="WakeUp_Mask" pos="BB_NB_IRQ-1:0" access="rw" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>

    <hole size="32" />

    <reg name="Cpu_Sleep" protect="w">
        <bits name="Sleep" pos="0" access="w" rst="0">
            <comment>Writing '1' to this bit will put the BCPU to sleep (i.e.: Disable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section)
            </comment>
        </bits>
    </reg>
    <reg name="Pulse_Mask_Set" protect="rw">
        <comment>Writing '1' sets the corresponding bit in the mask register to '1'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Pulse_Mask_Set" pos="BB_NB_IRQ_PULSE-1:0" access="rs" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Pulse_Mask_Clr" protect="rw">
        <comment>Writing '1' clears the corresponding bit in the mask register to '0'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Pulse_Mask_Clr" pos="BB_NB_IRQ_PULSE-1:0" access="rc" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Pulse_Clear" protect="rw">
        <comment>Writing '1' clears the corresponding Pulse IRQ.
            <br/>Pulse IRQ are set by the modules and cleared here.
        </comment>
        <bits name="Pulse_Clr" pos="BB_NB_IRQ_PULSE-1:0" access="c" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Pulse_Status" protect="r">
        <comment>The status for the Pulse Irq sources, one bit for each module's irq source.
            <br/>The status reflect the actual Irq source.
        </comment>
        <bits name="Status" pos="BB_NB_IRQ_PULSE-1:0" access="r" rst="0" cut="1" cutprefix="" cutenum="BB_Irq_Id" cutstart="0"/>
    </reg>


</module>

</archive>
<archive relative = "bb_rom.xml">
  <var name="BB_ROM_SIZE"   value="128*1024" /> 
  <var name="NB_BB_PATCH"   value="16" />       
  <var name="BB_PATCH_SIZE" value="64*32" />    

  
  <module name="bb_rom" category="Baseband">
    <memory name="rom_array" size="BB_ROM_SIZE">
      <comment>BB Rom Space
        <br/>This rom is used for BCPU.
      </comment>
    </memory>
  </module>

  
  <module name="bb_rom_ctrl" category="Baseband">
    
    <reg name="rom_patch" count="NB_BB_PATCH" protect="rw">
        <bits name="block_addr" pos="16:4" access="rw" rst = "0">
            <comment>Base address of block in int_Rom patched (corresponding data are read from int_SRam)
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="patch_en"  pos="31"    access="rw" rst="0">
            <options>
                <option name="Enable" value="1"/>
                <option name="Disable" value="0"/>
            </options>
        </bits>
    </reg>
    
    <hole size="1536"/>
      
    <memory name="ram_array" size="BB_PATCH_SIZE">
      <comment>BB Rom patch Ram Space
        <br/> Used for store the patch instead of rom, when patch is valid
      </comment>
    </memory>
  </module>





</archive>
<archive relative = "calendar.xml">
<module name="calendar" category="System">

    <reg name="Ctrl" protect="rw">

        <bits name="Interval" pos="1:0" access="rw" rst="0">
            <options>
                <default/>
                <option name="DISABLE" value="0"/>
                <option name="PER SEC" value="1"/>
                <option name="PER MIN" value="2"/>
                <option name="PER HOUR" value="3"/>
            </options>
            <comment>These 2 bits configure the interval of generating an IRQ status.
            </comment>
        </bits>
    </reg>
    
    <reg name="Cmd" protect="rw">
        <bits name="Calendar_Load" pos="0" access="rs" rst="0">
            <comment>When write, command to program calendar with a new value (sec, min, hour, day, month, year, day of week) previously written in registers Calendar_LoadVal_H and Calendar_LoadVal_L. This bit is auto cleared.
                <br/>'1' = load calendar timer.  
                <br/>
                <br/>When read, Calendar timer load status.
                <br/>'1' = Calendar load has not finished.
                <br/>'0' = Calendar load has finished.
            </comment>
        </bits>
        <bits name="Alarm_Load" pos="4" access="rs" rst="0">
            <comment>When write, command to program alarm with a new value (sec, min, hour, day, month, year, day of week) prviously written in registers AlarmVal_H and AlarmVal_L. This bit is auto cleared. 
                <br/>'1' = load alarm.
                <br/>
                <br/>When read, alarm load status.
                <br/>'1' = alarm load has not finished.
                <br/>'0' = alarm load has finished.
            </comment>
        </bits>
        <bits name="Alarm_Enable_Set" pos="5" access="rs" rst="0">
            <comment>command to enable alarm. When alarm is triggered, it will generate a wakup.
                <br/>'1' = enable alarm.
                <br/>
                <br/>When read, alarm enable status.
                <br/>'1' = alarm enable operation is on going, not finished.
                <br/>'0' = alarm is enabled.                  
            </comment>
        </bits>
        <bits name="Alarm_Enable_Clr" pos="6" access="rc" rst="0">
            <comment>command to disable alarm.
                <br/>'1' = disable alarm.
                <br/>
                <br/>When read, alarm enable status.
                <br/>'1' = alarm disable operation is on going, not finished.
                <br/>'0' = alarm is disabled.                  
            </comment>
        </bits>
        <bits name="Alarm_Clr" pos="8" access="rc" rst="0">
            <comment>writing '1', clear Alarm triggered signal (connect to wakeup) and alarm triggered IRQ.
                <br/>
                <br/>When read, get alarm clear status.
                <br/>'1' = alarm clear operation is on going, not finished.
                <br/>'0' = alarm is cleared.                  
            </comment>
        </bits>
        <bits name="Itv_Irq_Clr" pos="9" access="c" rst="0">
            <comment>writing '1', clear interval IRQ.
            </comment>
        </bits>
        <bits name="Itv_Irq_Mask_Set" pos="16" access="rs" rst="0">
            <comment>When write '1', Set interval Irq Mask. 
                <br/>When read, get interval Irq mask.
            </comment>
        </bits>        
        <bits name="Itv_Irq_Mask_Clr" pos="17" access="rc" rst="0">
            <comment>When write '1', Clear interval Irq Mask. 
                <br/>When read, get inteval Irq mask.
            </comment>
        </bits>               
        <bits name="Calendar_Not_Valid" pos="31" access="rs" rst="1">
            <comment>When write '1', mark calendar value to be not valid.
                <br/>
                <br/>When read, Indicate if the Calendar value is valid or not.
                <br/>The calendar value is not valid in case of mismatch between the calendar counter and the APB register,
                    which is the case of wakeup the phone after shut down. This mismatch disappear after one RTC cycle or 
                    after re-porgramming a new calendar value. 
                <br/>'1' = not valid.
            </comment>
        </bits>        
    </reg>

    <reg name="Status" protect="r">
        
        <bits name="Itv_Irq_Cause" pos="0" access="r" rst="0">
            <comment>Interval Irq Cause. 
            </comment>
        </bits>    
        <bits name="Alarm_Irq_Cause" pos="1" access="r" rst="0">
            <comment>Alarm Irq Cause. 
            </comment>
        </bits> 
        <bits name="Force_Wakeup" pos="8" access="r" rst="0">
             <comment>Force Wakeup status. After set "Force_Wakeup" to '1' in sys_ctrl, the real
                 force_wakeup is not set immediatly, this bit indicates when the force wakeup is 
                 really set. This bits also indicates if the interface between Calendar domain and
                 Core domain is enabled. 
                <br/>'1': force wakeup set.
            </comment>
        </bits>           
        <bits name="Chg_Mask" pos="12" access="r" rst="0">
             <comment>Charger Mask status. After set "Chg_Mask" to '1' in sys_ctrl, the real
                 Chg_Mask line is not set immediatly, this bit indicates when the Chg_Mask line is
                 really set.                
                <br/>'1': Chg_Mask line set.
            </comment>
        </bits>           
        <bits name="Itv_Irq_Status" pos="16" access="r" rst="0">
            <comment>Interval Irq Status. 
            </comment>
        </bits>        
        <bits name="Alarm_Enable" pos="20" access="r" rst="0">
            <comment>Alarm Enable Status. 
                <br/> Note: When calendar is not programmed, Alarm can be enabled or not. 
                <br/> It is suggested to clear Alarm Enable when program RTC. 
            </comment>
        </bits>          
        <bits name="Calendar_Not_Prog" pos="31" access="r" rst="0">
            <comment>'1' = Calendar has not been programmed. 
                <br/>This bit keep value '0' after the calendar is programmed once.
            </comment>
        </bits>
    </reg>

    <reg name="Calendar_LoadVal_L" protect="rw">
        <bits name="Sec" pos="5:0" access="rw" rst="-">
            <comment>Second value loaded to calendar, ranged from 0 to 59. 
            </comment>
        </bits>         
        <bits name="Min" pos="13:8" access="rw" rst="-">
            <comment>Minute value loaded to calendar, ranged from 0 to 59. 
            </comment>
        </bits>          
        <bits name="Hour" pos="20:16" access="rw" rst="-">
            <comment>Hour value loaded to calendar, ranged from 0 to 23. 
            </comment>
        </bits>         
    </reg>

    <reg name="Calendar_LoadVal_H" protect="rw">
        <bits name="Day" pos="4:0" access="rw" rst="-">
            <comment>Day value loaded to calendar, ranged from 1 to 31. 
            </comment>
        </bits>         
        <bits name="Mon" pos="11:8" access="rw" rst="-">
            <comment>Month value loaded to calendar, ranged from 1 to 12. 
            </comment>
        </bits>          
        <bits name="Year" pos="22:16" access="rw" rst="-">
            <comment>Year value loaded to calendar, ranged from 0 to 127. 
                <br/>Represent year 2000 to 2127.
            </comment>
        </bits>
        <bits name="WeekDay" pos="26:24" access="rw" rst="-">
            <comment>Day of the week value loaded to calendar, ranged from 1 to 7.
                <br/>Represent Monday, Tuesday etc.
            </comment>
        </bits>
    </reg>

    <reg name="Calendar_CurVal_L" protect="r">
        <bits name="Sec" pos="5:0" access="r" rst="-">
            <comment>Current Second value of calendar, ranged from 0 to 59. 
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="Min" pos="13:8" access="r" rst="-">
            <comment>Current Minute value of calendar, ranged from 0 to 59. 
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>          
        <bits name="Hour" pos="20:16" access="r" rst="-">
            <comment>Current Hour value of calendar, ranged from 0 to 23. 
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>         
    </reg>
    
    <reg name="Calendar_CurVal_H" protect="r">
        <bits name="Day" pos="4:0" access="r" rst="-">
            <comment>Current Day value of calendar, ranged from 1 to 31. 
                <br/>Maximum number of days in each month are stored in the module,
                and leap year is supported, so February can have 28 or 29 days.  
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>         
        <bits name="Mon" pos="11:8" access="r" rst="-">
            <comment>Current Month value of calendar, ranged from 1 to 12. 
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>          
        <bits name="Year" pos="22:16" access="r" rst="-">
            <comment>Current Year value of calendar, ranged from 0 to 127. 
                <br/>Represent year 2000 to 2127.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="WeekDay" pos="26:24" access="r" rst="-">
            <comment>Current Day of the week value of calendar, ranged from 1 to 7.
                <br/>Represent Monday, Tuesday etc.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
    </reg>
     
    <reg name="AlarmVal_L" protect="rw">
        <bits name="Sec" pos="5:0" access="rw" rst="-">
            <comment>Second value loaded to alarm, ranged from 0 to 59. 
            </comment>
        </bits>         
        <bits name="Min" pos="13:8" access="rw" rst="-">
            <comment>Minute value loaded to alarm, ranged from 0 to 59. 
            </comment>
        </bits>          
        <bits name="Hour" pos="20:16" access="rw" rst="-">
            <comment>Hour value loaded to alarm, ranged from 0 to 23. 
            </comment>
        </bits>         
    </reg>

    <reg name="AlarmVal_H" protect="rw">
        <bits name="Day" pos="4:0" access="rw" rst="-">
            <comment>Day value loaded to alarm, ranged from 1 to 31. 
            </comment>
        </bits>         
        <bits name="Mon" pos="11:8" access="rw" rst="-">
            <comment>Month value loaded to alarm, ranged from 1 to 12. 
            </comment>
        </bits>          
        <bits name="Year" pos="22:16" access="rw" rst="-">
            <comment>Year value loaded to alarm, ranged from 0 to 127. 
                <br/>Represent year 2000 to 2127.
            </comment>
        </bits>
    </reg>
    <reg name="Calib_Cfg" protect="rw">
        <bits name="Interval_Min" pos="5:0" access="rw" rst="0">
        </bits>
        <bits name="Interval_Hour" pos="10:6" access="rw" rst="0">
        </bits>
        <bits name="Trig_Enable" pos="31" access="rw" rst="0">
        </bits>
    </reg>
    
    
</module>



</archive>

<archive relative = "camera.xml">
<var name="FIFORAM_SIZE" value="80"/>    
<module name="camera" category="Periph">

    <reg name="CTRL" protect="rw">
		<bits access="rw" name="Enable" pos="0" rst="0">
            <options>
                <default/>
                <option name="ENABLE"  value="1"/>
                <option name="DISABLE" value="0"/>
            </options>            
			<comment> Enable camera controller,high active. 
			</comment>
    </bits>
		<bits access="rw" name="DctEnable" pos="1" rst="0">         
            <options>
                <default/>
                <option name="1_BUFENABLE_ENABLE"  value="1"/>
                <option name="1_BUFENABLE_DISABLE" value="0"/>
            </options>
			<comment> Enable camera controller,high active. 
			</comment>
    </bits>
    <bits access="rw" name="DataFormat" pos="5:4" rst="0">
            <options>
                <default/>
                <option name="RGB565"  value="0"/>
                <option name="YUV422"  value="1"/>
                <option name="JPEG"    value="2"/>
                <option name="RESERVE" value="3"/>
            </options>               
            <comment> "0" = RGB565.
                <br/> "1" = YUV422.
                <br/> "2" = Compressed Data.
                <br/> "3" = Reserved.
			</comment>
        </bits>
		<bits access="rw" name="RESET_Pol" pos="8" rst="1">
            <options>
                <default/>
                <option name="INVERT" value="1"/>
                <option name="NORMAL" value="0"/>
            </options>   
            <comment> '0' = keep output camera reset polarity.
                <br/> '1' = invert output camera reset polarity. 
			</comment>
        </bits>
		<bits access="rw" name="PWDN_Pol" pos="9" rst="0">
            <options>
                <default/>
                <option name="INVERT" value="1"/>
                <option name="NORMAL" value="0"/>
            </options>   
            <comment> '0' = keep output camera power down polarity.
                <br/> '1' = invert output camera power down polarity. 
			</comment>
        </bits>
		<bits access="rw" name="VSYNC_Pol" pos="10" rst="0">
            <options>
                <default/>
                <option name="INVERT" value="1"/>
                <option name="NORMAL" value="0"/>
            </options>   
            <comment> '0' = keep input VSYNC polarity.
                <br/> '1' = invert input VSYNC polarity. 
			</comment>
        </bits>
		<bits access="rw" name="HREF_Pol" pos="11" rst="0">
            <options>
                <default/>
                <option name="INVERT" value="1"/>
                <option name="NORMAL" value="0"/>
            </options>   
            <comment> '0' = keep input HREF polarity so data is sampled when HREF high.
                <br/> '1' = invert input HREF polarity so data is sampled when HREF low. 
			</comment>
        </bits>
		<bits access="rw" name="PIXCLK_Pol" pos="12" rst="0">
            <options>
                <default/>
                <option name="INVERT" value="1"/>
                <option name="NORMAL" value="0"/>
            </options>   
			<comment> '0' = keep pix clk polarity.
			    <br/> '1' = invert pix clk polarity.
			</comment>
        </bits>
		<bits access="rw" name="VSYNC_Drop" pos="14" rst="1">
            <options>
                <default/>
                <option name="DROP"   value="1"/>
                <option name="NORMAL" value="0"/>
            </options>   
			<comment> '0' = VSYNC irq always exists when Frame decimation is enabled.
			    <br/> '1' = VSYNC irq will drop when Frame data are dropped in decipation.
			</comment>
        </bits>
		<bits access="rw" name="DecimFrm" pos="17:16" rst="0">
            <options>
                <default/>
                <option name="ORIGINAL" value="0"/>
                <option name="DIV_2"    value="1"/>
                <option name="DIV_3"    value="2"/>
                <option name="DIV_4"    value="3"/>
            </options>   
			<comment> "0"= All frame data will be sent.
                <br/> "1"= only one frame out of two (1/2) will be sent.
                <br/> "2"= only one frame out of three (1/3) will be sent.
                <br/> "3"= only one frame out of four (1/4) will be sent.
			</comment>
        </bits>
        <bits access="rw" name="DecimCol" pos="19:18" rst="0">
            <options>
                <default/>
                <option name="ORIGINAL" value="0"/>
                <option name="DIV_2"    value="1"/>
                <option name="DIV_3"    value="2"/>
                <option name="DIV_4"    value="3"/>
            </options>   
			<comment> "0"= Pixel Decimation Disabled.
                <br/> "1"= Pixel Decimation 1/2.
                <br/> "2"= Pixel Decimation 1/3.
                <br/> "3"= Pixel Decimation 1/4.
			</comment>
        </bits> 
        <bits access="rw" name="DecimRow" pos="21:20" rst="0">
            <options>
                <default/>
                <option name="ORIGINAL" value="0"/>
                <option name="DIV_2"    value="1"/>
                <option name="DIV_3"    value="2"/>
                <option name="DIV_4"    value="3"/>
            </options>   
			<comment> "0"= line Decimation Disabled.
                <br/> "1"= line Decimation 1/2.
                <br/> "2"= line Decimation 1/3.
                <br/> "3"= line Decimation 1/4.
			</comment>
        </bits>  
        <bits name="Reorder"  pos="26:24" access="rw" rst="0">
            <comment>Controls the Re-ordering of the FIFO data.
                <br/> In following table, for input data, right comes before left. So YUYV means V comes first.
                <br/> for output data, right data is the LSB. So YUYV means V is stored in low 8-bit (byte0) of 32-bit word.
                <br/>
                <br/> If Bit 26 is '1', byte2 and byte0 is Y. 
                <br/> If Bit 25 is '1', both byte2/byte3 and byte1/byte0 interchange.
                <br/> If Bit 24 is '1', byte U and V should interchange. (UV bytes can be decided using bit 26).
                <br/>
                <br/> input YUYV, output YUYV: "000"
                <br/> input YVYU, output YUYV: "001"
                <br/> input UYVY, output YUYV: "110"
                <br/> input VYUY, output YUYV: "111"
                <br/>
                <br/> input YUYV, output UYVY: "010"
                <br/> input YVYU, output UYVY: "011"
                <br/> input UYVY, output UYVY: "100"
                <br/> input VYUY, output UYVY: "101"
                <br/>
                <br/> input YUYV, output YVYU: "001"
                <br/> input YVYU, output YVYU: "000"
                <br/> input UYVY, output YVYU: "111"
                <br/> input VYUY, output YVYU: "110"
                <br/>
                <br/> input YUYV, output VYUY: "011"
                <br/> input YVYU, output VYUY: "010"
                <br/> input UYVY, output VYUY: "101"
                <br/> input VYUY, output VYUY: "100"                
                <br/>
                <br/> Decimation will reorder data flow also. Input UYVY becomes YUVY after decimation.
                      This reorder is corrected using Bit 26 infomation.
            </comment>
        </bits>
        <bits access="rw" name="CropEn" pos="28" rst="0">
            <options>
                <default/>
                <option name="ENABLE"  value="1"/>
                <option name="DISABLE" value="0"/>
            </options>            
			<comment> "0"= Cropping Disabled.
				<br/> "1"= Cropping Enabled.
                <br/> Note: this bit should set to '0' when bit field "DataFormat" is "10" (compressed data)  
			</comment>
        </bits>          
		<bits access="rw" name="Bist Mode" pos="30" rst="0">
            <options>
                <default/>
                <option name="BIST"   value="1"/>
                <option name="NORMAL" value="0"/>
            </options>            
			<comment> 
				In Bist Mode, FIFO RAM are read and write by its address, FIFO mode is disabled. 
			</comment>
		</bits>       
		<bits access="rw" name="TEST" pos="31" rst="0">
            <options>
                <default/>
                <option name="TEST"  value="1"/>
                <option name="NORMAL" value="0"/>
            </options>            
			<comment> 
				Debug only. A RGB565 test card is sent to system bus instead of real data from sensor. 
			</comment>
		</bits>       
     </reg>
	<reg protect="r" name="STATUS">
		<bits access="r" name="OVFL" pos="0" rst="0">
            <comment> '1' = FIFO over-write IRQ status. 
                <br/> Write to corresponding bit in IRQ CLEAR register will clear this bit.  
			</comment>
		</bits>
		<bits access="r" name="VSYNC_R" pos="1" rst="0">
			<comment> '1' = VSYNC rising edge IRQ status 
                <br/> Write to corresponding bit in IRQ CLEAR register will clear this bit.  
			</comment>
        </bits>
		<bits access="r" name="VSYNC_F" pos="2" rst="0">
			<comment> '1' = VSYNC falling edge IRQ status 
                <br/> Write to corresponding bit in IRQ CLEAR register will clear this bit.  
			</comment>
        </bits>
		<bits access="r" name="DMA DONE" pos="3" rst="0">
			<comment> '1' = DMA Done IRQ status 
                <br/> Write to corresponding bit in IRQ CLEAR register will clear this bit.  
			</comment>
        </bits>
		<bits access="r" name="FIFO EMPTY" pos="4" rst="1">
			<comment> '1' = FIFO Empty status, not clear-able. 
			</comment>
        </bits>
	</reg>
     <reg name="DATA"  protect="r">
         <bits name="RX_DATA" pos="31:0" access="r" rst="0">
           <comment>Read in the receive FIFO
           </comment>
         </bits>
     </reg>

	<reg protect="rw" name="IRQ MASK">
		<bits access="rw" name="OVFL" pos="0" rst="0">
			<comment> '1' = FIFO over-write enable 
			</comment>
		</bits>
		<bits access="rw" name="VSYNC_R" pos="1" rst="0">
			<comment> '1' = VSYNC rising edge enable 
			</comment>
		</bits>
		<bits access="rw" name="VSYNC_F" pos="2" rst="0">
			<comment> '1' = VSYNC falling edge enable 
			</comment>
		</bits>
		<bits access="rw" name="DMA DONE" pos="3" rst="0">
			<comment> '1' = DMA Done enable 
			</comment>
		</bits>
        
	</reg>
     
	<reg protect="w" name="IRQ CLEAR">
		<bits access="w" name="OVFL" pos="0" rst="0">
			<comment> Write '1' to clear FIFO over-write interrupt
			</comment>
		</bits>
		<bits access="w" name="VSYNC_R" pos="1" rst="0">
			<comment> Write '1' to clear VSYNC rising edge interrupt
			</comment>
		</bits>
		<bits access="w" name="VSYNC_F" pos="2" rst="0">
			<comment> Write '1' to clear VSYNC falling edge interrupt
			</comment>
		</bits>
		<bits access="w" name="DMA DONE" pos="3" rst="0">
			<comment> Write '1' to clear DMA Done interrupt
			</comment>
		</bits>
	</reg>
	
	<reg protect="r" name="IRQ CAUSE">
		<bits access="r" name="OVFL" pos="0" rst="0">
			<comment> '1' = FIFO over-write cause 
			</comment>
		</bits>
		<bits access="r" name="VSYNC_R" pos="1" rst="0">
			<comment> '1' = VSYNC rising edge cause 
			</comment>
        </bits>
		<bits access="r" name="VSYNC_F" pos="2" rst="0">
			<comment> '1' = VSYNC falling edge cause 
			</comment>
        </bits>
		<bits access="r" name="DMA DONE" pos="3" rst="0">
			<comment> '1' = DMA Done cause 
			</comment>
        </bits>
	</reg>

	<reg protect="rw" name="CMD SET">
		<bits name="PWDN" pos="0" access="rs" rst="1">
			<comment> Power down pin of CMOS sensor . 
			</comment>
		</bits>
		<bits name="RESET" pos="4" access="rs" rst="1">
			<comment> Reset pin of CMOS sensor. 
                    <br/>Active Low.
			</comment>
        </bits>
       <bits name="FIFO RESET" pos="8" access="s" rst="0">
          <comment>For the software to clear FIFO. This bit is auto-reset to 0.
          </comment>
       </bits>
    </reg>

	<reg protect="rw" name="CMD CLR">
		<bits name="PWDN" pos="0" access="rc" rst="1">
			<comment> Power down pin of CMOS sensor . 
			</comment>
		</bits>
		<bits name="RESET" pos="4" access="rc" rst="1">
			<comment> Reset pin of CMOS sensor. 
			</comment>
        </bits>
    </reg>
   
	<reg protect="rw" name="DSTWINCOL">
		<bits name="DstWinColStart" pos="11:0" access="rw" rst="0">
			<comment> start pixel of cropped window. 
			</comment>
		</bits>
		<bits name="DstWinColEnd" pos="27:16" access="rw" rst="0">
			<comment> end pixel of cropped window. 
			</comment>
        </bits>
    </reg>

	<reg protect="rw" name="DSTWINROW">
		<bits name="DstWinRowStart" pos="11:0" access="rw" rst="0">
			<comment> start line of cropped window. 
			</comment>
		</bits>
    <bits name="DstWinRowEnd" pos="27:16" access="rw" rst="0">
			<comment> end line of cropped window. 
			</comment>
        </bits>
    </reg>

    <reg protect="rw" name="SCALE_COFIG">
        <bits name="SCALE_EN" pos="0" access="rw" rst="0">
            <comment> scale enable.
            </comment>
        </bits>
        <bits name="SCALE_COL" pos="9:8" access="rw" rst="0">
            <comment> scale column.
            </comment>
        </bits>
        <bits name="SCALE_ROW" pos="17:16" access="rw" rst="0">
            <comment> scale row.
            </comment>
        </bits>
    </reg>

    <reg protect="rw" name="CAM_SPI_REG_0">
        <bits name="line_num_per_frame" pos="31:22" access="rw" rst="0">
        </bits>
        <bits name="block_num_per_line" pos="21:12" access="rw" rst="0">
        </bits>
        <bits name="vsync_inv" pos="11" access="rw" rst="0">
        </bits>
        <bits name="href_inv" pos="10" access="rw" rst="0">
        </bits>
        <bits name="overflow_inv" pos="9" access="rw" rst="0">
        </bits>
        <bits name="big_end_dis" pos="8" access="rw" rst="0">
        </bits>
        <bits name="overflow_rst_en" pos="7" access="rw" rst="0">
        </bits>
        <bits name="overflow_observe_only_vsync_low" pos="6" access="rw" rst="0">
        </bits>
        <bits name="overflow_rstn_only_vsync_low" pos="5" access="rw" rst="0">
        </bits>
        <bits name="yuv_out_format" pos="4:2" access="rw" rst="0">
        </bits>
        <bits name="camera_spi_master_en" pos="1" access="rw" rst="0">
        </bits>
        <bits name="camera_spi_slave_en" pos="0" access="rw" rst="0">
        </bits>
    </reg>

    <reg protect="rw" name="CAM_SPI_REG_1">
        <bits name="clk_div_num" pos="15:0" access="rw" rst="0">
        </bits>
        <bits name="cts_spi_master_reg" pos="16" access="rw" rst="0">
        </bits>
        <bits name="ssn_cm_inv" pos="17" access="rw" rst="0">
        </bits>
        <bits name="sck_cm_inv" pos="18" access="rw" rst="0">
        </bits>
        <bits name="ssn_spi_oenb_dr" pos="19" access="rw" rst="0">
        </bits>
        <bits name="ssn_spi_oenb_reg" pos="20" access="rw" rst="0">
        </bits>
        <bits name="sck_spi_oenb_dr" pos="21" access="rw" rst="0">
        </bits>
        <bits name="sck_spi_oenb_reg" pos="22" access="rw" rst="0">
        </bits>
    </reg>

    <reg protect="rw" name="CAM_SPI_REG_2">
        <bits name="ssn_cs_inv" pos="29" access="rw" rst="0">
        </bits>
        <bits name="ready_cs_inv" pos="28" access="rw" rst="0">
        </bits>
        <bits name="data_rcv_choose_bit" pos="27:26" access="rw" rst="0">
        </bits>
        <bits name="ssn_cs_delay" pos="25:24" access="rw" rst="0">
        </bits>
        <bits name="word_num_per_block" pos="23:16" access="rw" rst="0">
        </bits>
        <bits name="init_wait_length" pos="15:8" access="rw" rst="0">
        </bits>
        <bits name="ssn_wait_length" pos="7:0" access="rw" rst="0">
        </bits>
    </reg>

    <reg protect="rw" name="CAM_SPI_REG_3">
        <bits name="ssn_high_length" pos="31:24" access="rw" rst="0">
        </bits>
        <bits name="block_wait_length" pos="23:16" access="rw" rst="0">
        </bits>
        <bits name="line_wait_length" pos="15:0" access="rw" rst="0">
        </bits>
    </reg>

    <reg protect="rw" name="CAM_SPI_REG_4">
        <bits name="block_num_per_packet" pos="15:6" access="rw" rst="0">
        </bits>
        <bits name="image_width_choose_bit" pos="5" access="rw" rst="0">
        </bits>
        <bits name="image_height_choose_bit" pos="4" access="rw" rst="0">
        </bits>
        <bits name="data_size_choose_bit" pos="3" access="rw" rst="0">
        </bits>
        <bits name="sdo_line_choose_bit" pos="2:1" access="rw" rst="0">
        </bits>
        <bits name="camera_spi_master_en_2" pos="0" access="rw" rst="0">
        </bits>
    </reg>

    <reg protect="rw" name="CAM_SPI_REG_5">
        <bits name="sync_code" pos="23:0" access="rw" rst="0">
        </bits>
    </reg>

    <reg protect="rw" name="CAM_SPI_REG_6">
        <bits name="packet_id_frame_start" pos="31:24" access="rw" rst="0">
        </bits>
        <bits name="packet_id_frame_end" pos="23:16" access="rw" rst="0">
        </bits>
        <bits name="packed_id_line_start" pos="15:8" access="rw" rst="0">
        </bits>
        <bits name="packed_id_data_start" pos="7:0" access="rw" rst="0">
        </bits>
    </reg>

    <reg protect="r" name="CAM_SPI_OBSERVE_REG_0">
        <bits name="obs_data_id_wrong" pos="28" access="r" rst="0">
        </bits>
        <bits name="obs_ln_num_wrong" pos="27" access="r" rst="0">
        </bits>
        <bits name="obs_img_width_wrong" pos="26" access="r" rst="0">
        </bits>
        <bits name="obs_img_height_wrong" pos="25" access="r" rst="0">
        </bits>
        <bits name="obs_data_size_wrong" pos="24" access="r" rst="0">
        </bits>
        <bits name="data_id" pos="23:16" access="r" rst="0">
        </bits>
        <bits name="line_id" pos="15:0" access="r" rst="0">
        </bits>
    </reg>

    <reg protect="r" name="CAM_SPI_OBSERVE_REG_1">
        <bits name="image_width" pos="31:16" access="r" rst="0">
        </bits>
        <bits name="image_height" pos="15:0" access="r" rst="0">
        </bits>
    </reg>

    <hole size="3456"/>
    <struct count="FIFORAM_SIZE" name="FIFORAM">
    <reg name="RAMData" protect="r">
        <bits name="Data" pos="31:0" access="r" rst="0">
            <comment> Direct FIFO Ram Access. They are enabled only in Bist Mode.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
    </reg>
    </struct>    
    
   
</module>
</archive>
<archive relative = "cau_dig.xml">

<module name="cau_dig" category="System">

  <reg name="gpadc_ctrl_0" protect="rw">
    <bits access="rw" name="pu_gpadc_sw" pos="0" rst="0x0">
      <comment> power up gpadc analog. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_1" protect="rw">
    <bits access="rw" name="pclk_wr_rd_bp" pos="10" rst="0x1">
      <comment> set 0, pclk will be auto-gated; otherwise, no auto-gating. </comment>
    </bits>
    <bits access="rw" name="clk_gpadc_acg_bp" pos="9" rst="0x1">
      <comment> set 0, clk_gpadc will be auto-gated; otherwise, no auto-gating. </comment>
    </bits>
    <bits access="rw" name="cfg_clk_gpadc" pos="8:0" rst="307">
      <comment> cfg clk_gpadc divider. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_2" protect="rw">
    <bits access="rw" name="gpadc_vref_bit" pos="3:2" rst="0x2">
      <comment> for analog config. </comment>
    </bits>
    <bits access="rw" name="gpadc_vref_ms_enable" pos="1" rst="0x0">
      <comment> for analog config. </comment>
    </bits>
    <bits access="rw" name="key_pullup2x" pos="0" rst="0x0">
      <comment> for analog config. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_3" protect="rw">
    <bits access="rw" name="gpadc_sar_mode" pos="2" rst="0x0">
      <comment> config gpadc sar mode: 0-fast mode; 1-slow mode. </comment>
    </bits>
    <bits access="rw" name="sar_adc_out_pol" pos="1" rst="0x0">
      <comment> config sar_adc_out from gpadc analog polarity. </comment>
    </bits>
    <bits access="rw" name="gpadc_auto_en" pos="0" rst="0x0">
      <comment> config auto gpadc enable. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_4" protect="rw">
    <bits access="rw" name="gpadc_channel_sel" pos="7:0" rst="0x0">
      <comment> config which gpadc channel enable. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_5" protect="rw">
    <bits access="rw" name="gpadc_start_interval" pos="15:0" rst="0xFFFF">
      <comment> config gpadc interval time. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_6" protect="rw">
    <bits access="rw" name="samp_wait_time" pos="7:0" rst="0x2">
      <comment> config gpadc sample wait time. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_7" protect="rw">
    <bits access="rw" name="samp_time" pos="7:0" rst="0x4">
      <comment> config gpadc sample time. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_8" protect="rw">
    <bits access="rw" name="conv_wait_time" pos="7:0" rst="0x4">
      <comment> config gpadc convert wait time. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_9" protect="rw">
    <bits access="rw" name="conv_time" pos="9:0" rst="0xB">
      <comment> config gpadc convert time. </comment>
    </bits>
  </reg>

  <reg name="gpadc_ctrl_10" protect="rw">
    <bits access="rw" name="gpadc_en" pos="0" rst="0x0">
      <comment> gpadc enable. </comment>
    </bits>
  </reg>

  <hole size="160" />

  <reg name="gpadc_value_0" protect="r">
    <bits access="r" name="gpadc0_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 0. </comment>
    </bits>
  </reg>

  <reg name="gpadc_value_1" protect="r">
    <bits access="r" name="gpadc1_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 1. </comment>
    </bits>
  </reg>

  <reg name="gpadc_value_2" protect="r">
    <bits access="r" name="gpadc2_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 2. </comment>
    </bits>
  </reg>

  <reg name="gpadc_value_3" protect="r">
    <bits access="r" name="gpadc3_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 3. </comment>
    </bits>
  </reg>

  <reg name="gpadc_value_4" protect="r">
    <bits access="r" name="gpadc4_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 4. </comment>
    </bits>
  </reg>

  <reg name="gpadc_value_5" protect="r">
    <bits access="r" name="gpadc5_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 5. </comment>
    </bits>
  </reg>

  <reg name="gpadc_value_6" protect="r">
    <bits access="r" name="gpadc6_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 6. </comment>
    </bits>
  </reg>

  <reg name="gpadc_value_7" protect="r">
    <bits access="r" name="gpadc7_value" pos="9:0" rst="0x0">
      <comment> gapdc digtal value of channel 7. </comment>
    </bits>
  </reg>

  <reg name="gpadc_channel_en" protect="r">
    <bits access="r" name="gpadc_channel_en" pos="7:0" rst="0x0">
      <comment> current which channel is working, read only. </comment>
    </bits>
  </reg>

  <reg name="gpadc_end" protect="rw">
    <bits access="rw" name="gpadc_end" pos="0" rst="0x0">
      <comment> when gpadc over, it will be set to 1. </comment>
    </bits>
  </reg>

  <reg name="gpadc_swrst" protect="rw">
    <bits access="rw" name="rst_gpadc_sw" pos="0" rst="0x0">
      <comment> sw rst. </comment>
    </bits>
  </reg>

  <hole size="128" />

  <reg name="gpadc_int_en" protect="rw">
    <bits access="rw" name="gpadc_int_en" pos="0" rst="0x0">
      <comment> enable gpadc interrupt. </comment>
    </bits>
  </reg>

  <hole size="1024" />

  <reg name="efuse_pgm_data0_15_0" protect="rw">
    <bits access="rw" name="efuse_pgm_data_0_15_0" pos="15:0" rst="0x0">
      <comment> bit 15 to 0 of efuse0 program. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_data0_31_16" protect="rw">
    <bits access="rw" name="efuse_pgm_data_0_31_16" pos="15:0" rst="0x0">
      <comment> bit 31 to 16 of efuse0 program. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_data0_47_32" protect="rw">
    <bits access="rw" name="efuse_pgm_data_0_47_32" pos="15:0" rst="0x0">
      <comment> bit 47 to 32 of efuse0 program. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_data0_63_48" protect="rw">
    <bits access="rw" name="efuse_pgm_data_0_63_48" pos="15:0" rst="0x0">
      <comment> bit 63 to 48 of efuse0 program. </comment>
    </bits>
  </reg>

  <hole size="128" />

  <reg name="efuse_prot_0" protect="rw">
    <bits access="rw" name="efuse_prot_0" pos="15:0" rst="0x0">
      <comment> protect register of efuse0, after it's set to 0x5a5a, you can use efuse0 controller; otherwise, it's forbbiden. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_0" protect="w">
    <bits access="rw" name="efuse_pgm_0" pos="0" rst="0x0">
      <comment> start program of efuse0. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_0" protect="w">
    <bits access="rw" name="efuse_read_0" pos="0" rst="0x0">
      <comment> start read of efuse0. </comment>
    </bits>
  </reg>

  <reg name="efuse_status_0" protect="r">
    <bits access="rw" name="efuse_done_0" pos="0" rst="0x0">
      <comment> the status of efuse0, when program or read, this bit is 1, indicating the operation is done. </comment>
    </bits>
  </reg>

  <reg name="efuse_avdd_time" protect="rw">
    <bits access="rw" name="efuse_avdd_time" pos="9:0" rst="0xA0">
      <comment> the avdd time parameter of efuse. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_time" protect="rw">
    <bits access="rw" name="efuse_pgm_time" pos="9:0" rst="0x20A">
      <comment> the pgm time parameter of efuse. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_time" protect="rw">
    <bits access="rw" name="efuse_read_time" pos="3:0" rst="0x5">
      <comment> the read time parameter of efuse. </comment>
    </bits>
  </reg>

  <hole size="288" />

  <reg name="efuse_read_data0_15_0" protect="rw">
    <bits access="rw" name="efuse_read_data_0_15_0" pos="15:0" rst="0x0">
      <comment> bit 15 to 0 value of read efuse0. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_data0_31_16" protect="rw">
    <bits access="rw" name="efuse_read_data_0_31_16" pos="15:0" rst="0x0">
      <comment> bit 31 to 16 value of read efuse0. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_data0_47_32" protect="rw">
    <bits access="rw" name="efuse_read_data_0_47_32" pos="15:0" rst="0x0">
      <comment> bit 47 to 32 value of read efuse0. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_data0_63_48" protect="rw">
    <bits access="rw" name="efuse_read_data_0_63_48" pos="15:0" rst="0x0">
      <comment> bit 63 to 48 value of read efuse0. </comment>
    </bits>
  </reg>

  <hole size="128" />

  <reg name="efuse_pgm_data1_15_0" protect="rw">
    <bits access="rw" name="efuse_pgm_data_1_15_0" pos="15:0" rst="0x0">
      <comment> bit 15 to 0 of efuse1 program. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_data1_31_16" protect="rw">
    <bits access="rw" name="efuse_pgm_data_1_31_16" pos="15:0" rst="0x0">
      <comment> bit 31 to 16 of efuse1 program. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_data1_47_32" protect="rw">
    <bits access="rw" name="efuse_pgm_data_1_47_32" pos="15:0" rst="0x0">
      <comment> bit 47 to 32 of efuse1 program. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_data1_63_48" protect="rw">
    <bits access="rw" name="efuse_pgm_data_1_63_48" pos="15:0" rst="0x0">
      <comment> bit 63 to 48 of efuse1 program. </comment>
    </bits>
  </reg>

  <hole size="128" />

  <reg name="efuse_prot_1" protect="rw">
    <bits access="rw" name="efuse_prot_1" pos="15:0" rst="0x0">
      <comment> protect register of efuse1, after it's set to 0x6b6b, you can use efuse1 controller; otherwise, it's forbbiden. </comment>
    </bits>
  </reg>

  <reg name="efuse_pgm_1" protect="w">
    <bits access="rw" name="efuse_pgm_1" pos="0" rst="0x0">
      <comment> start program of efuse1. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_1" protect="w">
    <bits access="rw" name="efuse_read_1" pos="0" rst="0x0">
      <comment> start read of efuse1. </comment>
    </bits>
  </reg>

  <reg name="efuse_status_1" protect="r">
    <bits access="rw" name="efuse_done_1" pos="0" rst="0x0">
      <comment> the status of efuse1, when program or read, this bit is 1, indicating the operation is done. </comment>
    </bits>
  </reg>

  <hole size="384" />

  <reg name="efuse_read_data1_15_0" protect="rw">
    <bits access="rw" name="efuse_read_data_1_15_0" pos="15:0" rst="0x0">
      <comment> bit 15 to  0 value of read efuse1. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_data1_31_16" protect="rw">
    <bits access="rw" name="efuse_read_data_1_31_16" pos="15:0" rst="0x0">
      <comment> bit 31 to 16 value of read efuse1. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_data1_47_32" protect="rw">
    <bits access="rw" name="efuse_read_data_1_47_32" pos="15:0" rst="0x0">
      <comment> bit 47 to 32 value of read efuse1. </comment>
    </bits>
  </reg>

  <reg name="efuse_read_data1_63_48" protect="rw">
    <bits access="rw" name="efuse_read_data_1_63_48" pos="15:0" rst="0x0">
      <comment> bit 63 to 48 value of read efuse1. </comment>
    </bits>
  </reg>

  <hole size="128" />

  <reg name="led_ctrl_0" protect="rw">
    <bits access="rw" name="cfg_clk_bl_dim_15_0" pos="15:0" rst="0xDD3">
      <comment> cfg clock divider of clk_bl_dim. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_1" protect="rw">
    <bits access="rw" name="cfg_clk_bl_dim_23_16" pos="7:0" rst="0x1">
      <comment> cfg clock divider of clk_bl_dim. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_2" protect="rw">
    <bits access="rw" name="cfg_clk_kp_dim_15_0" pos="15:0" rst="0xDD3">
      <comment> cfg clock divider of clk_kp_dim. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_3" protect="rw">
    <bits access="rw" name="cfg_clk_kp_dim_23_16" pos="7:0" rst="0x1">
      <comment> cfg clock divider of clk_kp_dim. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_4" protect="rw">
    <bits access="rw" name="bl_duty_cycle" pos="7:0" rst="0x10">
      <comment> config back light dim duty cycle. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_5" protect="rw">
    <bits access="rw" name="r_duty_cycle" pos="7:0" rst="0x10">
      <comment> config red dim duty cycle. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_6" protect="rw">
    <bits access="rw" name="g_duty_cycle" pos="7:0" rst="0x10">
      <comment> config green dim duty cycle. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_7" protect="rw">
    <bits access="rw" name="b_duty_cycle" pos="7:0" rst="0x10">
      <comment> config blue dim duty cycle. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_8" protect="rw">
    <bits access="rw" name="bit_bl_sel" pos="6" rst="0x0">
      <comment> 1- i_bit[3:0] of back light is from register; 0- i_bit[3:0] of back light from hardware. </comment>
    </bits>
    <bits access="rw" name="bit_bl_on" pos="5:2" rst="0x8">
      <comment> i_bit[3:0] register of back light. </comment>
    </bits>
    <bits access="rw" name="bl_dim_clk_dly" pos="1:0" rst="0x0">
      <comment> config the rate of back light dim. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_9" protect="rw">
    <bits access="rw" name="rgb_dim_mode"      pos="0" rst="0x0"> 
      <comment> 0- from pwm; 1- from cau_dig. </comment>
    </bits>
    <bits access="rw" name="bl_dim_en"         pos="1" rst="0x0"> </bits>
    <bits access="rw" name="r_dim_em"          pos="2" rst="0x0"> </bits>
    <bits access="rw" name="g_dim_em"          pos="3" rst="0x0"> </bits>
    <bits access="rw" name="b_dim_em"          pos="4" rst="0x0"> </bits>
    <bits access="rw" name="clk_bl_dim_acg_bp" pos="5" rst="0x1"> 
      <comment> set 0, clk_bl_dim will be auto-gated; otherwise, no auto-gating. </comment>
    </bits>
    <bits access="rw" name="clk_kp_dim_acg_bp" pos="6" rst="0x1"> 
      <comment> set 0, clk_kp_dim will be auto-gated; otherwise, no auto-gating. </comment>
    </bits>
    <bits access="rw" name="lp_bl          "   pos="7" rst="0x0"> </bits>
    <bits access="rw" name="lp_rgb         "   pos="8" rst="0x0"> </bits>
    <bits access="rw" name="lp2_rgb        "   pos="9" rst="0x0"> </bits>
    <bits access="rw" name="lowleak_bl     "   pos="10" rst="0x0"> </bits>
    <bits access="rw" name="lowleak_rgb    "   pos="11" rst="0x0"> </bits>
    <bits access="rw" name="hv_mode_bl     "   pos="12" rst="0x0"> </bits>
    <bits access="rw" name="ix2_bl         "   pos="13" rst="0x0"> </bits>
    <bits access="rw" name="former_mode_rgb"   pos="14" rst="0x0"> </bits>
  </reg>

  <reg name="led_ctrl_10" protect="rw">
    <bits access="rw" name="dim_b_buf"  pos="7" rst="0x0"> </bits>
    <bits access="rw" name="dim_g_buf"  pos="6" rst="0x0"> </bits>
    <bits access="rw" name="dim_r_buf"  pos="5" rst="0x0"> </bits>
    <bits access="rw" name="dim_bl_buf" pos="4" rst="0x0"> </bits>

    <bits access="rw" name="dim_b_sel"  pos="3" rst="0x0"> 
      <comment> blue dim: 0- from hardware; 1- dim signal from dim_b_buf. </comment>
    </bits>
    <bits access="rw" name="dim_g_sel"  pos="2" rst="0x0"> 
      <comment> green dim: 0- from hardware; 1- dim signal from dim_g_buf. </comment>
    </bits>
    <bits access="rw" name="dim_r_sel"  pos="1" rst="0x0"> 
      <comment> red dim: 0- from hardware; 1- dim signal from dim_r_buf. </comment>
    </bits>
    <bits access="rw" name="dim_bl_sel" pos="0" rst="0x0"> 
      <comment> back light dim: 0- from hardware; 1- dim signal from dim_bl_buf. </comment>
    </bits>
  </reg>

  <reg name="led_ctrl_11" protect="rw">
    <bits access="rw" name="rst_blkp_dim_sw" pos="0" rst="0x0"> </bits>
  </reg>

  <reg name="led_ctrl_12" protect="rw">
    <bits access="rw" name="kp_dim_clk_dly"  pos="1:0" rst="0x0">
      <comment> config the rate of rgb dim. </comment>
    </bits>
    <bits access="rw" name="bit_r_on      "  pos="4:2" rst="0x4"> 
      <comment> i_bit[2:0] register of red. </comment>
    </bits>
    <bits access="rw" name="bit_g_on      "  pos="7:5" rst="0x4"> 
      <comment> i_bit[2:0] register of green. </comment>
    </bits>
    <bits access="rw" name="bit_b_on      "  pos="10:8" rst="0x4"> 
      <comment> i_bit[2:0] register of blue. </comment>
    </bits>
    <bits access="rw" name="bit_r_sel     "  pos="11" rst="0x0"> 
      <comment> 1- i_bit[2:0] of red is from register; 0- i_bit[2:0] of red from hardware. </comment>
    </bits>
    <bits access="rw" name="bit_g_sel     "  pos="12" rst="0x0"> 
      <comment> 1- i_bit[2:0] of green is from register; 0- i_bit[2:0] of green from hardware. </comment>
    </bits>
    <bits access="rw" name="bit_b_sel     "  pos="13" rst="0x0"> 
      <comment> 1- i_bit[2:0] of blue is from register; 0- i_bit[2:0] of blue from hardware. </comment>
    </bits>
  </reg>

  <hole size="1632" />

  <reg name="prng_ctrl" protect="rw">
    <bits name="enable" pos="0" access="rw" rst="0">
    </bits>
  </reg>
  <reg name="prng_init" protect="rw">
    <bits name="init" pos="0" access="w" rst="0">
    </bits>
  </reg>
  <reg name="prng_seed" protect="r">
    <bits name="seed_data" pos="31:0" access="r" rst="0x0">
    </bits>
  </reg>
  <reg name="prng_lfsr" protect="r">
    <bits name="lfsr_data" pos="31:0" access="r" rst="0x0">
    </bits>
  </reg>

  <hole size="1920" />

  <reg name="rampdac_reg0" protect="rw">
    <bits name="pu_rampdac" pos="0" access="rw" rst="0">
    </bits>
  </reg>

  <reg name="rampdac_reg1" protect="rw">
    <bits name="gain" pos="4:0" access="rw" rst="0x4">
    </bits>
  </reg>

  <reg name="rampdac_reg2" protect="rw">
    <bits name="din" pos="9:0" access="rw" rst="0x200">
    </bits>
  </reg>

  <hole size="416" />

  <reg name="pmu1_reserved_vcore_in" protect="rw">
    <bits name="pmu1_reserved_vcore_in" pos="15:0" access="rw" rst="0">
    </bits>
  </reg>

  <reg name="pmu1_reserved_vcore_out" protect="r">
    <bits name="pmu1_reserved_vcore_out" pos="7:0" access="rw" rst="0">
    </bits>
  </reg>

  <reg name="pmu2_reserved_vcore_in" protect="rw">
    <bits name="pmu2_reserved_vcore_in" pos="15:0" access="rw" rst="0">
    </bits>
  </reg>

  <reg name="pmu2_reserved_vcore_out" protect="r">
    <bits name="pmu2_reserved_vcore_out" pos="7:0" access="rw" rst="0">
    </bits>
  </reg>

  <hole size="128" />

  <reg name="cfg_pfm_mode_clk_buck1" protect="r">
    <bits name="en_pfm_mode_clk_buck1" pos="2" access="rw" rst="0x0">
      <comment> set 1, enable pfm_mode_clk_buck1. </comment>
    </bits>
    <bits name="sel_pfm_mode_clk_buck1" pos="1:0" access="rw" rst="0x2">
      <options>
        <option name="pfm_mode_clk_buck1_32k_div2" value=" 0"/>
        <option name="pfm_mode_clk_buck1_32k_div4" value=" 1"/>
        <option name="pfm_mode_clk_buck1_32k_div8" value=" 2"/>
        <option name="pfm_mode_clk_buck1_32k_div16" value=" 3"/>
        <mask/>
        <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_pfm_mode_clk_buck2" protect="r">
    <bits name="en_pfm_mode_clk_buck2" pos="2" access="rw" rst="0x0">
      <comment> set 1, enable pfm_mode_clk_buck2. </comment>
    </bits>
    <bits name="sel_pfm_mode_clk_buck2" pos="1:0" access="rw" rst="0x2">
      <options>
        <option name="pfm_mode_clk_buck2_32k_div2" value=" 0"/>
        <option name="pfm_mode_clk_buck2_32k_div4" value=" 1"/>
        <option name="pfm_mode_clk_buck2_32k_div8" value=" 2"/>
        <option name="pfm_mode_clk_buck2_32k_div16" value=" 3"/>
        <mask/>
        <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_sync_clk_buck1" protect="r">
    <bits name="phase_ini_buck1" pos="4:0" access="rw" rst="0x00">
    </bits>
    <bits name="dither_disable" pos="5" access="rw" rst="0x00">
    </bits>
    <bits name="dither_sel_buck1" pos="7:6" access="rw" rst="0x00">
      <options>
        <option name="one_bit_positive_dither" value="0"/>
        <option name="one_bit_negative_dither" value="1"/>
        <option name="two_bit_positive_dither" value="2"/>
        <option name="two_bit_negative_dither" value="3"/>
        <mask/>
        <shift/>
      </options>
    </bits>
    <bits name="pol_clk_buck1" pos="8" access="rw" rst="0x00">
    </bits>
    <bits name="en_clk_buck1" pos="9" access="rw" rst="0x01">
    </bits>
  </reg>

  <reg name="cfg_sync_clk_buck2" protect="r">
    <bits name="phase_ini_buck2" pos="4:0" access="rw" rst="0x00">
    </bits>
    <bits name="dither_disable" pos="5" access="rw" rst="0x00">
    </bits>
    <bits name="dither_sel_buck2" pos="7:6" access="rw" rst="0x00">
      <options>
        <option name="one_bit_positive_dither" value="0"/>
        <option name="one_bit_negative_dither" value="1"/>
        <option name="two_bit_positive_dither" value="2"/>
        <option name="two_bit_negative_dither" value="3"/>
        <mask/>
        <shift/>
      </options>
    </bits>
    <bits name="pol_clk_buck2" pos="8" access="rw" rst="0x00">
    </bits>
    <bits name="en_clk_buck2" pos="9" access="rw" rst="0x01">
    </bits>
  </reg>

  <reg name="cfg_chr_chopper_clk" protect="r">
    <bits name="cfg_chr_chopper_clk" pos="5:0" access="rw" rst="0x1A">
    </bits>
    <bits name="en_chr_chopper_clk" pos="6" access="rw" rst="0x0">
    </bits>
  </reg>

  <hole size="992" />

  <reg name="usb11_pu_usb" protect="rw">
    <bits name="usb11_pu_usb" pos="0" access="rw" rst="1">
    </bits>
  </reg>

  <reg name="usb11_ctr_usb" protect="rw">
    <bits name="usb11_ctr_usb" pos="2:0" access="rw" rst="0x1">
    </bits>
  </reg>

  <reg name="usb11_vreg_bit" protect="rw">
    <bits name="usb11_vreg_bit" pos="2:0" access="rw" rst="0x4">
    </bits>
  </reg>

  <reg name="usb_id" protect="rw">
    <bits name="usb_id" pos="0" access="rw" rst="1">
    </bits>
  </reg>

  <reg name="spk_reg0" protect="rw">
    <bits name="pu_dvdd_spk " pos="9"   access="rw" rst="0"> </bits>
    <bits name="dvdd_spk_bit" pos="8:6" access="rw" rst="0x4"> </bits>
    <bits name="vh_spk_bit  " pos="5:3" access="rw" rst="0x4"> </bits>
    <bits name="vl_spk_bit  " pos="2:0" access="rw" rst="0x4"> </bits>
  </reg>

  <reg name="spk_reg1" protect="rw">
    <bits name="vcom_sel_clg    " pos="14:13" access="rw" rst="0"> </bits>
    <bits name="vcom_clg_bit    " pos="12:10" access="rw" rst="4"> </bits>
    <bits name="isel_clg_bit    " pos="9:8"   access="rw" rst="2"> </bits>
    <bits name="ipwm_bit        " pos="7:6"   access="rw" rst="0"> </bits>
    <bits name="setup_tmctrl_bit" pos="5:4"   access="rw" rst="0"> </bits>
    <bits name="gain_clg_bit    " pos="3:0"   access="rw" rst="0"> </bits>
  </reg>

  <reg name="spk_reg2" protect="rw">
    <bits name="dmode_en_clg     " pos="14:13" access="rw" rst="0x2"> </bits>
    <bits name="code_sel_bit     " pos="12"    access="rw" rst="0"> </bits>
    <bits name="interface_mode_en" pos="11"    access="rw" rst="1"> </bits>
    <bits name="pcc_en           " pos="10"    access="rw" rst="0"> </bits>
    <bits name="pcc_reset        " pos="9"     access="rw" rst="0"> </bits>
    <bits name="vcom_sel_int2    " pos="8"     access="rw" rst="0"> </bits>
    <bits name="dac_vpcc_bit     " pos="7:0"   access="rw" rst="3"> </bits>
  </reg>

  <reg name="spk_reg3" protect="rw">
    <bits name="no_det_clg" pos="5" access="rw" rst="0"> </bits>
    <bits name="ncn_enb   " pos="4" access="rw" rst="0"> </bits>
    <bits name="vncn_bit  " pos="3:2" access="rw" rst="1"> </bits>
    <bits name="vzcp_bit  " pos="1:0" access="rw" rst="1"> </bits>
  </reg>

  <reg name="spk_reg4" protect="rw">
    <bits name="reserved_in_bit" pos="15:0" access="rw" rst="0"> </bits>
  </reg>

  <reg name="spk_reg5" protect="r">
    <bits name="zcp_out_clg" pos="0" access="r" rst="1"> </bits>
    <bits name="ncn_out_clg" pos="1" access="r" rst="1"> </bits>
    <bits name="iov_out_clg" pos="2" access="r" rst="1"> </bits>
  </reg>

  <reg name="spk_reg6" protect="r">
    <bits name="reserved_out_bit" pos="7:0" access="r" rst="1">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg7" protect="rw">
    <bits name="pu_clg" pos="0" access="rw" rst="0">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg8" protect="rw">
    <bits name="reset_clg" pos="0" access="rw" rst="1">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg9" protect="rw">
    <bits name="pu_core_clg" pos="0" access="rw" rst="0">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg10" protect="rw">
    <bits name="reset_core_clg" pos="0" access="rw" rst="1">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg11" protect="rw">
    <bits name="pd_o_clg" pos="0" access="rw" rst="1">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg12" protect="rw">
    <bits name="prng_seed_15_0" pos="0" access="rw" rst="0">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg13" protect="rw">
    <bits name="prng_seed_31_16" pos="0" access="rw" rst="0">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg14" protect="rw">
    <bits name="enable_clk_32k" pos="0" access="rw" rst="1">
      <comment> . </comment>
    </bits>
    <bits name="enable_clk_spk" pos="1" access="rw" rst="1">
      <comment> . </comment>
    </bits>
  </reg>

  <reg name="spk_reg15" protect="rw">
    <bits name="cfg_clk_spk" pos="5:0" access="rw" rst="0x18">
      <comment> . </comment>
    </bits>
  </reg>


















</module>

</archive>

<archive relative = "cholk.xml">
    <module name="cholk" category="Baseband">
    <reg32 name="CHOLK_CTRL" protect="rw">
      <bits name="CHOLK_ON" pos="0" access="rw" rst="0">
	      <comment>write 1 will enable CHOLK module
	      </comment>
      </bits>
      <bits name="CHOLK_INT_MASK" pos="1" access="rw" rst="0">
	      <comment>1:level INT will be masked, 0:level INT will not be masked
	      </comment>
      </bits>   
      <bits name="CHOLK_MODE" pos="2" access="rw" rst="0">
	      <comment>1: Complex mode ; 0: Real mode
	      </comment>
      </bits>      
    </reg32>

    <reg32 name="GAIN" protect="rw">
      <bits name="RESI_GAIN" pos="1:0" access="rw" rst="0">
	      <comment>RESI GAIN
	      </comment>
      </bits> 
  
      <bits name="RESI2_GAIN" pos="3:2" access="rw" rst="0">
	      <comment>RESI2 GAIN
	      </comment>
      </bits> 


      <bits name="OGRS_GAIN" pos="5:4" access="rw" rst="0">
	      <comment>OGRS_GAIN
	      </comment>
      </bits> 


      <bits name="OLES1_GAIN" pos="7:6" access="rw" rst="0">
	      <comment>OLES1_GAIN
	      </comment>
      </bits> 

      <bits name="OLES2_GAIN" pos="9:8" access="rw" rst="0">
	      <comment>OLES2_GAIN
	      </comment>
      </bits> 

      <bits name="COEF_GAIN" pos="11:10" access="rw" rst="0">
	      <comment>COEF_GAIN
	      </comment>
      </bits> 

      <bits name="GRAD_GAIN" pos="13:12" access="rw" rst="0">
	      <comment>GRAD_GAIN
	      </comment>
      </bits> 
                                   
 
      <bits name="GOPS_GAIN" pos="15:14" access="rw" rst="0">
	      <comment>GOPS_GAIN
	      </comment>
      </bits> 

      <bits name="OLES3_GAIN" pos="17:16" access="rw" rst="0">
	      <comment>OLES3_GAIN
	      </comment>
      </bits> 
     </reg32>    

    <reg32 name="ITER_THRE" protect="rw">
      <bits name="ITER_THRE1" pos="15:0" access="rw" rst="0">
	      <comment>ITER_THRE1
	      </comment>
      </bits> 
     </reg32> 

    <reg32 name="MCOVA_BASE" protect="rw">
      <bits name="MCOVA_BASE" pos="12:0" access="rw" rst="0">
	      <comment>Matrix COVA base addr in BBSRAM
	      </comment>
      </bits> 
     </reg32> 

    <reg32 name="MCE_BASE" protect="rw">
      <bits name="MCE_BASE" pos="12:0" access="rw" rst="0">
	      <comment>CE base addr in BBSRAM
	      </comment>
      </bits> 
     </reg32>      

    <reg32 name="MCOEF_BASE" protect="rw">
      <bits name="MCOEF_BASE" pos="12:0" access="rw" rst="0">
	      <comment>COEF base addr in BBSRAM
	      </comment>
      </bits> 
     </reg32>   

    <reg32 name="NUMBER" protect="rw">
      <bits name="ROW_NUMBER" pos="4:0" access="rw" rst="0">
	      <comment>Matrix Row Number, maximal is 24 for Real, and 16 for Complex
	      </comment>
      </bits> 

      <bits name="MCOVA_NUMBER" pos="13:5" access="rw" rst="0">
	      <comment>Matrix COVA effective element number - 1 to read
	      </comment>
      </bits> 
      
      <bits name="ITER_NUMBER" pos="18:14" access="rw" rst="0">
	      <comment>MAXIMAL iteration number - 1 for CHOLK
	      </comment>
      </bits> 
  </reg32> 

   <reg32 name="CHOLK_STATUS" protect="rw">
      <bits name="CHOLK_STATUS" pos="0" access="rw" rst="1">
	      <comment>CHOLK Done status, ACC enable and SW write this bit will clear this Done status, hardware will set this bit when done.
	      </comment>
      </bits> 
  </reg32>  

   <reg32 name="CHOLK_INT" protect="rw">
      <bits name="CHOLK_INT_RAW" pos="0" access="rw" rst="1">
	      <comment>write 0 to this bit will clear CHOLK level RAW interrupt source bit, write 1 will not. read this bit will get raw cholk INT source bit
	      </comment>
      </bits>
      <bits name="CHOLK_INT_out" pos="1" access="r" rst="1">
	      <comment>read this bit will get cholk INT status after masking. INT_out = INT_RAW and ~MASK
	      </comment>
      </bits>                     
   </reg32>                

  </module>
</archive>     
<archive relative = "cipher.xml">
<module name="cipher" category="Baseband">
  <reg protect="rw" name="ctrl">
    <bits access="w" name="Enable" pos="0" rst="no">
        <comment>
            Writing a '1' in this register triggers an A5 process. Ignored if the module is
            already processing. Auto-reset bit
        </comment>
    </bits>
    <bits access="rw" name="Algorithm" pos="4" rst="1">
        <comment>Selects the appropriate algorithm
        </comment>
        <options>
            <option name="A5_1" value="0"/>
            <option name="A5_2" value="1"/>
        </options>
    </bits>
  </reg>

  <reg protect="r" name="status">
    <bits access="r" name="Running" pos="0" rst="0">
      <comment>1 when running, 0 in other case. </comment>
    </bits>
    <bits access="r" name="Data_Blk_Rdy" pos="4" rst="0">
        <comment>1 when data block ready (Ciphering processed), reseted when the data register is read.
        </comment>
    </bits>
  </reg>

  <reg protect="rw" name="Kc low">
    <bits access="rw" name="Kc_Lsb" pos="31:0" rst="0xFFFFFFFF" display="hex">
      <comment>Cipher key Kc, LSB bit [31:0].</comment>
    </bits>
  </reg>
  
  <reg protect="rw" name="Kc high">
    <bits access="rw" name="Kc_Msb" pos="31:0" rst="0xFFFFFFFF" display="hex">
      <comment>Cipher key Kc, MSB bit [31:0].</comment>
    </bits>
  </reg>
  
  <reg protect="rw" name="Count">
    <bits access="rw" name="Count" pos="21:0" rst="0x3FFFFF" display="hex">
      <comment>Count register, this field represent the TDMA frame number.</comment>
    </bits>
  </reg>

  <reg protect="r" name="Data0_block2">
    <bits access="r" name="Data_blk2" pos="31:0" rst="no">
      <comment>Data block2 bit[31:0]</comment>
    </bits>
  </reg>

  <reg protect="r" name="Data1_block2">
      <bits access="r" name="Data_blk2" pos="31:0" rst="no">
      <comment>Data block2 bit[63:32]</comment>
    </bits>
  </reg>

  <reg protect="r" name="Data2_block2">
    <bits access="r" name="Data_blk2" pos="31:0" rst="no">
      <comment>Data block2 bit[95:64]</comment>
    </bits>
  </reg>

  <reg protect="r" name="Data3_block2">
    <bits access="r" name="Data_blk2" pos="17:0" rst="no">
      <comment>Data block2 bit[113:96]</comment>
    </bits>
  </reg>

 <struct count="29" name="Data_block1">
    <reg protect="r" name="Data block1">
      <bits access="r" name="Bit0" pos="7" rst="no">
        <comment> </comment>
      </bits>
      <bits access="r" name="Bit1" pos="15" rst="no">
        <comment> </comment>
      </bits>
      <bits access="r" name="Bit2" pos="23" rst="no">
        <comment> </comment>
      </bits>
      <bits access="r" name="Bit3" pos="31" rst="no">
        <comment> </comment>
      </bits>
    </reg>
  </struct>

</module>
</archive>
<archive relative = "cipher_a53.xml">
<module name="cipher_a53" category="Baseband">
  <reg16 name="CIPH_STAT" protect="rw" >
      <bits access="r" name="RES" pos="15:5" rst="0">
      </bits>
      <bits access="rw" name="A53" pos="4" rst="0"> 
          <comment>
              Select Between A5/1-A5/2 and A5/3 Ciphering Block
          </comment>
      </bits>
      <bits access="rw" name="INIT" pos="3" rst="0"> 
          <comment>
              Initialize A5/3 Ciphering
          </comment>
      </bits>
      <bits access="rw" name="EDGE" pos="2" rst="0">
          <comment>
              Select Ciphering Blcok Size
          </comment>
      </bits>
      <bits access="rw" name="A52" pos="1" rst="0"> 
          <comment>
              Switch Between A5/1 and A5/2 Algorithm if A5/1-A5/2 Block is Selected
          </comment>
      </bits>
      <bits access="rw" name="CACT" pos="0" rst="0"> 
          <comment>
              Status and Activation of Ciphering Block
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register0" protect="rw" >
      <bits access="rw" name="KEY0" pos="15:0" rst="0">
          <comment>
              Cipher Key0
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register1" protect="rw" >
      <bits access="rw" name="KEY1" pos="15:0" rst="0">
          <comment>
              Cipher Key1
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register2" protect="rw" >
      <bits access="rw" name="KEY2" pos="15:0" rst="0">
          <comment>
              Cipher Key2
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register3" protect="rw" >
      <bits access="rw" name="KEY3" pos="15:0" rst="0">
          <comment>
              Cipher Key3
          </comment>
      </bits>
  </reg16>

  <reg16 name="TMOD26" protect="rw" >
      <bits access="rw" name="A52_RES_TMOD26" pos="15:5" rst="0">
          <comment>
          </comment>
      </bits>
      <bits access="rw" name="A52_T26N" pos="4:0" rst="0">
          <comment>
          </comment>
      </bits>
  </reg16>

  <reg16 name="TMOD51" protect="rw" >
      <bits access="rw" name="A52_RES_TMOD51" pos="15:6" rst="0">
          <comment>
          </comment>
      </bits>
      <bits access="rw" name="A52_T51N" pos="5:0" rst="0">
          <comment>
          </comment>
      </bits>
  </reg16>

  <reg16 name="SFNUM" protect="rw" >
      <bits access="rw" name="A52_RES_SFNUM" pos="15:11" rst="0">
          <comment>
          </comment>
      </bits>
      <bits access="rw" name="A52_SFN" pos="10:0" rst="0">
          <comment>
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register4" protect="rw" >
      <bits access="rw" name="KEY4" pos="15:0" rst="0">
          <comment>
              Cipher Key4
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register5" protect="rw" >
      <bits access="rw" name="KEY5" pos="15:0" rst="0">
          <comment>
              Cipher Key5
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register6" protect="rw" >
      <bits access="rw" name="KEY6" pos="15:0" rst="0">
          <comment>
              Cipher Key6
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Register7" protect="rw" >
      <bits access="rw" name="KEY7" pos="15:0" rst="0">
          <comment>
              Cipher Key7
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Data1" protect="rw" >
      <bits access="rw" name="CA" pos="15:8" rst="0">
          <comment>
              GSM mode:00001111
              EDGE mode:11110000
          </comment>
      </bits>
      <bits access="rw" name="CB" pos="7:3" rst="0">
          <comment>
              CB=0000
          </comment>
      </bits>
      <bits access="rw" name="CD" pos="2" rst="0">
          <comment>
              CD=0
          </comment>
      </bits>
      <bits access="r" name="RES_KEY_DAT1" pos="1:0" rst="0">
          <comment>
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Data2" protect="rw" >
      <bits access="rw" name="CE" pos="15:0" rst="0">
          <comment>
              CE=0000000000000000
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Data3" protect="rw" >
      <bits access="r" name="RES_15_14" pos="15:14" rst="0">
          <comment>
          </comment>
      </bits>
      <bits access="rw" name="SFN_10_5" pos="13:8" rst="0">
          <comment>
          </comment>
      </bits>
      <bits access="r" name="RES_7_0" pos="7:0" rst="0">
          <comment>
          </comment>
      </bits>
  </reg16>

  <reg16 name="Key Data4" protect="rw" >
      <bits access="rw" name="SFN_4_0" pos="15:11" rst="0">
          <comment>
          </comment>
      </bits>
      <bits access="rw" name="T51N" pos="10:5" rst="0">
          <comment>
          </comment>
      </bits>
      <bits access="rw" name="T26N" pos="4:0" rst="0">
          <comment>
          </comment>
      </bits>
  </reg16>

  <reg16 name="unused1" protect="rc" count="112" >
  </reg16>

  <reg16 name="block1" protect="rw" count="8" >
  </reg16>

  <reg16 name="unused2" protect="rc" count="24" >
  </reg16>

  <reg16 name="block2" protect="rw" count="8" >
  </reg16>

</module>

<module name="cipher_a53_spram" category="System">
    <memory name="spram_array" size="64*2">
        <comment>cipher_a53 internal Spram space
        </comment>
    </memory>
</module>

</archive>

<archive relative = "comregs.xml">
<module name="comregs" category="Modem">
    <reg name="Snapshot" protect="r">
        <bits name="Snapshot_gsm" pos="1:0" access="r" rst="0">
            <comment>Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg.
            </comment>
            <options><mask/><shift/></options>
        </bits>
        <bits name="Snapshot_nb" pos="3:2" access="r" rst="0">
            <comment>Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg.
            </comment>
            <options><mask/><shift/></options>
        </bits>
    </reg>
    <reg name="Snapshot_Cfg" protect="rw">
        <bits name="Snapshot_Cfg"  pos="0" access="rw" rst="0">
            <comment>Number of snapshot.
            </comment>
          </bits>
        <bits name="Snapshot_Cfg_rd"  pos="1" access="r" rst="1">
        </bits>          
    </reg>
    <reg name="Cause" protect="r">
        <bits name="Irq0_Cause" pos="7:0" access="r" rst="0">
            <comment>When read from the Xcpu, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask.
                <br/>When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask.
            </comment>
            <options><mask/><shift/></options>
        </bits>
        <bits name="Irq1_Cause" pos="15:8" access="r" rst="0">
            <comment>When read from the Xcpu, this return the cause of interruption, basically the set/clear register X_Irq1 part masked with X_Irq1_Mask.
                <br/>When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask.
            </comment>
            <options><mask/><shift/></options>
        </bits>
    </reg>
    <reg name="Mask_Set" protect="rw">
        <bits name="Irq0_Mask_Set" pos="7:0" access="rs" rst="0">
            <comment>When read: returns the value of the Irq0_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="Irq1_Mask_Set" pos="15:8" access="rs" rst="0">
            <comment>When read: returns the value of the Irq1_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 1.
            </comment>
           <options><mask/><shift/><default/></options>
        </bits>
    </reg>
    <reg name="Mask_Clr" protect="rw">
        <bits name="Irq0_Mask_Clr" pos="7:0" access="rc" rst="0">
            <comment>When read: returns the value of the Irq0_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0.
             </comment>
            <options><mask/><shift/><default/></options>
         </bits>
        <bits name="Irq1_Mask_Clr" pos="15:8" access="rc" rst="0">
            <comment>When read: returns the value of the Irq1_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 1.
             </comment>
             <options><mask/><shift/><default/></options>
        </bits>
    </reg>
    <reg name="ItReg_Set" protect="rw">
        <comment>If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously from both CPUs and affecting the same bits, the priority is given to set a bit.</comment>
        <bits name="Irq0_Set" pos="7:0" access="rs" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the XCPU/BCPU if enabled.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="Irq1_Set" pos="15:8" access="rs" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the XCPU/BCPU if enabled.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bitgroup name="Irq">
            <entry ref="Irq0_Set"/>
            <entry ref="Irq1_Set"/>
        </bitgroup>
    </reg>
    
    <reg name="ItReg_Clr" protect="rw">
        <comment>If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously from both CPUs and affecting the same bits, the priority is given to set a bit.</comment>
        <bits name="Irq0_Clr" pos="7:0" access="rc" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the XCPU/BCPU if enabled.
            </comment>
        </bits>
        <bits name="Irq1_Clr" pos="15:8" access="rc" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the XCPU/BCPU if enabled.
            </comment>
        </bits>
    </reg>

</module>
</archive>

<archive relative = "cordic.xml">

<module name="cordic" category="Baseband">

  <reg name="yin" protect="rw">
    <bits access="rw" name="y_addr" pos="31:0" rst="0x0">
      <comment>Control setting. y, i.e. numerator of atan computation. </comment>
    </bits>
  </reg>

  <reg name="xin" protect="rw">
    <bits access="rw" name="x_addr" pos="31:0" rst="0x0">
      <comment>Control setting. x, i.e. denominator of atan computation. </comment>
    </bits>
  </reg>

  <reg name="cmd" protect="rw">
    <bits access="rw" name="cmd" pos="0:0" rst="0x0">
      <comment>The start signal. Use the posedge of this signal. </comment>
      <options>
          <option name="RST" value="0"></option>
          <option name="START" value="1"></option>
      </options>
    </bits>
  </reg>

  <reg name="status" protect="r">
    <bits access="r" name="op" pos="31:0" rst="0x0">
      <comment>Status is set to 1 when an operation is finished. </comment>
      <options>
          <option name="Busy" value="0x00000000"></option>
          <option name="Free" value="0xFFFFFFFF"></option>
      </options>
    </bits>
  </reg>


  <reg name="dout" protect="r">
    <bits access="r" name="result_angle" pos="15:0" rst="0x0">
        <comment>. angle. The actual value is angle*pi/4</comment>
    </bits>
    <bits access="r" name="result_amplitude" pos="31:16" rst="0x0">
      <comment>amplitude.</comment>
    </bits>
  </reg>

  <reg name="amp" protect="r">
    <bits access="r" name="result_amp" pos="16:0" rst="0x0">
      <comment>amplitude only.</comment>
      <options>
          <mask/>
      </options>
    </bits>
  </reg>

</module>

</archive>

<archive relative = "debug_host.xml">


<module name="debug_host" category="Debug">
  <reg protect="--" name="cmd">
    <bits access="r" name="Addr" pos="28:0" rst="-">
      <comment>Address of data to be read or written. </comment>
    </bits>

    <bits access="r" name="Size" pos="30:29" rst="-">
      <comment>These two bits indicates element data size. <br />
            when "00" = "byte". <br />
            when "01" = "half word". <br />
            when "10" = "word". 
        </comment>
    </bits>

    <bits access="r" name="Write_H" pos="31" rst="-">
      <comment>This bit indicates command is read or write. <br />
        when "0" = "Read". <br />
        when "1" = "Write".  
      </comment>
    </bits>

  </reg>

  <reg protect="--" name="data">
    <bits access="rw" name="data" pos="31:0" rst="-">
      <comment>Those bits are data to be read or written by IFC. </comment>
    </bits>
    
  </reg>

  <reg protect="rw" name="event">
    <bits access="rw" name="event0_sema" pos="0" rst="0">
      <comment>When read, this bit is used for event semaphore. <br />
            '0' = no new event should be programed. <br />
            '1' = no pending event, new event is authorised. <br />
            If host is not enabled, this bit is always '1'. However in this case, 
            any event written will be ignored. <br />
            When Write, this bit is the least significant bit for a 32-bit event.
      </comment>
    </bits>

    <bits access="w" name="event31_1" pos="31:1" rst="-">
      <comment> These bits combined with bit0 consists a 32-bit event number. If a
            new event is written before the previous event has been sent, it will 
            be ignored. 
      </comment>
    </bits>
  </reg>

  <reg protect="rw" name="mode">
    <bits access="rw" name="force_on" pos="0" rst="1">
      <comment>When '1', force the debug host on, use clock UART if clock host is not
            detected. </comment>
    </bits>

    <bits access="r" name="Clk_Host_On" pos="1" rst="0">
      <comment>This bit indicates if clock host is detected to be on or not. <br />
            '0' = no clock host. <br />
            '1' = clock host detected. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="h2p_status">
    <bits access="r" name="h2p_status" pos="7:0" rst="0">
      <comment>Status which can be written through debug uart interface into a debug host
            internal register and read by APB. </comment>
      <options>
        <mask/>
        <shift/>
      </options>
    </bits>
    <bits access="w" name="h2p_status_rst" pos="16" rst="0">
      <comment>write in this bit will reset h2p status register. </comment>
    </bits>
  </reg>
  
  <reg protect="rw" name="p2h_status">
    <bits access="rw" name="p2h_status" pos="7:0" rst="0">
      <comment>Status which can be written by APB and read through debug uart interface 
            as a debug host internal register.
      </comment>
    </bits>
  </reg>
  
  <reg protect="r" name="irq">
    <bits access="r" name="xcpu_irq" pos="0" rst="0">
      <comment>when write '1', clear the xcpu irq level which is programmed in a debug host
          internal register, this bit is automatic cleared. <br /> when read, get the xcpu
          irq status. </comment>
    </bits>
    
    <bits access="r" name="bcpu_irq" pos="1" rst="0">
      <comment>when write '1', clear the bcpu irq level which is programmed in a debug host
            internal register, this bit is automatic cleared.<br /> when read, get the bcpu
            irq status.</comment>
    </bits>
    
  </reg>
</module>



</archive>

<archive relative = "debug_host_internals.xml">

<include file="globals.xml"/>

	<module name="debug_host_internal_registers" category="Debug">
		<ireg name="CTRL_SET" protect="rw">
			<comment>General control signals set.</comment>
			<bits name="Debug_Reset" pos="0" rst="0" access="rs">
				<comment>Debug host generated reset. Signal to system control. Active high.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
			<bits name="XCPU_Force_Reset" pos="1" rst="0" access="rs">
				<comment>Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal rst_host_reg.</comment>
			</bits>
			<bits name="Force_Wakeup" pos="2" rst="0" access="rs">
				<comment>Force wakeup. Active high.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal rst_host_reg.</comment>
			</bits>
			<bits name="Force_BP_XCPU" pos="3" rst="0" access="rs">
				<comment>Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
			<bits name="Force_BP_BCPU" pos="4" rst="0" access="rs">
				<comment>Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
			<bits name="IT_XCPU" pos="5" rst="0" access="rs">
				<comment>When write '1, generate a level IRQ to XCPU. Write '0 is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
			<bits name="IT_BCPU" pos="6" rst="0" access="rs">
				<comment>When write '1', generate a level IRQ to BCPU. Write '0' is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
			<bits name="Debug_Port_Lock" pos="7" rst="0" access="rs">
				<comment>Lock Debug port set.<br/>Write '1' to this bit will set it to '1'.<br/>Reseted by signal rst_host_reg.</comment>
			</bits>
		</ireg>
		
		<ireg name="CTRL_CLR" protect="rw">
			<comment>General control signals clear.</comment>		
			<bits name="XCPU_Force_Reset" pos="1" rst="0" access="rc">
				<comment>Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.<br/>Write '1' to this bit will clear it to '0'.<br/>Reseted by signal rst_host_reg.</comment>
			</bits>
			<bits name="Force_Wakeup" pos="2" rst="0" access="rc">
				<comment>Force wakeup. Active high.<br/>Write '1' to this bit will clear it to '0'.<br/>Reseted by signal rst_host_reg.</comment>
			</bits>
			<bits name="Force_BP_XCPU" pos="3" rst="0" access="rc">
				<comment>Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.<br/>Write '1' to this bit will clear it to '0'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>	
			<bits name="Force_BP_BCPU" pos="4" rst="0" access="rc">
				<comment>Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.<br/>Write '1' to this bit will clear it to '0'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
			<bits name="Debug_Port_Lock" pos="7" rst="0" access="rc">
				<comment>Lock Debug port clear.<br/>Write '1' to this bit will clear it to '0'.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>            
		</ireg>

		<ireg name="CLKDIV" protect="rw">
			<comment>Configure Debug UART Clock divider.</comment>
			<bits name="CFG_CLK" pos="5:0" rst="2" access="rw">
				<comment>Debug host clock divider. The serial clock is generated by dividing  14,7456MHz Host Clock by (CFG_CLK+2). So By default, the serial clock is 14,7456MHz / (2+2) = 3,6864 MHz which corresponds to the 921,6K Baud-rate.<br/>Reseted by signal rst_host_reg.</comment>
			</bits>
        </ireg>

		<ireg name="CFG" protect="rw">
			<comment>Configure Debug UART.</comment>
			<bits name="Disable_Uart_H" pos="0" rst="0" access="rw">
                <comment>When '1', Disable Normal Uart functional group.
                    <br/>This bit is set to '1' when break.
                    <br/>Reseted by signal rst_host_reg.
                </comment>
			</bits>
			<bits name="Disable_IFC_H" pos="1" rst="0" access="rw">
                <comment>When '1', Ignore IFC write and read access so only debug host internal is accessible.
                    <br/>This bit is set to '1' when break.
                    <br/>Reseted by signal rst_host_reg.
                </comment>
			</bits>
			<bits name="Debug_Host_Sel" pos="2" rst="0" access="rw">
                <comment>The usage of this bit is deternimed by the specific chip.
                    <br/>Can be used as Debug_Port_Lock register to protect some register change by the regular software while debug hosr is used to set thoses registers to specific values.
                    <br/>Reseted by signal rst_host_reg.
                </comment>
			</bits>
			<bits name="Force_Prio_H" pos="7" rst="1" access="rw">
				<comment>When '1', force the Debug Uart to have priority on TX.<br/>Reseted by signal rst_host_reg.</comment>
			</bits>	
        </ireg>
        

		<ireg name="CRC_REG" protect="rw">
			<comment>Status of CRC.</comment>
			<bits name="CRC" pos="0" rst="0" access="rc">
				<comment>This bit represents that an CRC error has occured in commands received by Debug Host. Once set to '1', it will keep the value until this register is clearred by write '1'.<br/>'0' = no CRC error.<br/>'1' = CRC error.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
			<bits name="FC_Fifo_Ovf" pos="1" rst="0" access="r">
				<comment>This bit represents if the 16-byte Flow Control FIFO has an overflow error. This status will be kept until a RX break is received.<br/>'0' = no Flow Control Overflow Error.<br/>'1' = Flow Control Overflow Error.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
		</ireg>
			
		<ireg name="H2P_STATUS" protect="rw">
			<comment>Host write, APB readable register.</comment>
			<bits name="STATUS" pos="7:0" rst="0" access="rw">
				<comment>These bits can be read by APB and write by host. Corresponds to APB register STATUS. They can also be reseted to zeros by APB command. (see details in debug host APB register mapping) <br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
		</ireg>

		<ireg name="P2H_STATUS" protect="rw">
			<comment>APB write, Host readable register.</comment>
			<bits name="STATUS" pos="7:0" rst="0" access="rw">
				<comment>These bits can be written by APB and read by host. Corresponds to APB register STATUS.<br/>Write to Bit 0 can reset the P2H status.<br/>Reseted by signal sys_rst_others (host).</comment>
			</bits>
		</ireg>

		<ireg name="AHB_SYS_HMBURSREQ" protect="r">
			<comment>Debug information of system side AHB bus status.</comment>
			<bits name="SYS_IFC_HMBURSREQ" pos="0" rst="-" access="r">
				<comment>The bit represent Sys Ifc HMBURSREQ.</comment>
			</bits>
			<bits name="SYS_DMA_HMBURSREQ" pos="1" rst="-" access="r">
				<comment>The bit represent Dma HMBURSREQ.</comment>
			</bits>
			<bits name="SYS_AHB2AHB_HMBURSREQ" pos="2" rst="-" access="r">
				<comment>The bit represent Sys Ahb2ahb HMBURSREQ.</comment>
			</bits>
			<bits name="XCPU_HMBURSREQ" pos="3" rst="-" access="r">
				<comment>The bit represent Xcpu HMBURSREQ.</comment>
            </bits>
			<bits name="USBC_HMBURSREQ" pos="4" rst="-" access="r">
				<comment>The bit represent USBC HMBURSREQ.</comment>
            </bits>
			<bits name="GOUDA_HMBURSREQ" pos="5" rst="-" access="r">
				<comment>The bit represent GOUDA HMBURSREQ.</comment>
            </bits>
		</ireg>
            
		<ireg name="AHB_SYS_HMGRANT" protect="r">
			<bits name="SYS_IFC_HMGRANT" pos="0" rst="-" access="r">
				<comment>The bit represent Sys Ifc HMGRANT.</comment>
			</bits>
			<bits name="SYS_DMA_HMGRANT" pos="1" rst="-" access="r">
				<comment>The bit represent Dma HMGRANT.</comment>
			</bits>
			<bits name="SYS_AHB2AHB_HMGRANT" pos="2" rst="-" access="r">
				<comment>The bit represent Sys Ahb2ahb HMGRANT.</comment>
			</bits>
			<bits name="XCPU_HMGRANT" pos="3" rst="-" access="r">
				<comment>The bit represent Xcpu HMGRANT.</comment>
			</bits>
			<bits name="USBC_HMGRANT" pos="4" rst="-" access="r">
				<comment>The bit represent USBC HMGRANT.</comment>
            </bits>
			<bits name="GOUDA_HMGRANT" pos="5" rst="-" access="r">
				<comment>The bit represent GOUDA HMGRANT.</comment>
            </bits>            
		</ireg>
	
		<ireg name="AHB_SYS_HSEL" protect="r">
			<comment>Debug information of AHB bus status HSEL.</comment>
			<bits name="SYS_MEM_EXT_HSEL" pos="0" rst="-" access="r">
				<comment>The bit represent Sys MEM_EXT HSEL.</comment>
			</bits>
			<bits name="SYS_MEM_INT_HSEL" pos="1" rst="-" access="r">
				<comment>The bit represent Sys MEM_INT HSEL.</comment>
			</bits>
			<bits name="SYS_IFC_HSEL" pos="2" rst="-" access="r">
				<comment>The bit represent Sys Ifc HSEL.</comment>
			</bits>
			<bits name="SYS_AHB2AHB_HSEL" pos="3" rst="-" access="r">
				<comment>The bit represent Sys Ahb2ahb HSEL.</comment>
			</bits>
			<bits name="SYS_USBC_HSEL" pos="4" rst="-" access="r">
				<comment>The bit represent USBC HSEL.</comment>
            </bits>
			<bits name="SYS_GOUDA_HSEL" pos="5" rst="-" access="r">
				<comment>The bit represent GOUDA HSEL.</comment>
            </bits>               
			<bits name="SYS_XCPU_RAM_HSEL" pos="6" rst="-" access="r">
				<comment>The bit represent XCPU RAM HSEL.</comment>
            </bits>               
		</ireg>

		<ireg name="AHB_SYS_HSREADY" protect="r">
			<bits name="SYS_IFC_HSREADY" pos="0" rst="-" access="r">
				<comment>The bit represent Sys Ifc HSREADY.</comment>
			</bits>
			<bits name="SYS_MEM_HSREADY" pos="1" rst="-" access="r">
				<comment>The bit represent Sys EBC HSREADY.</comment>
			</bits>
			<bits name="SYS_AHB2AHB_HSREADY" pos="2" rst="-" access="r">
				<comment>The bit represent Sys Ahb2ahb HSREADY.</comment>
            </bits>
			<bits name="SYS_USBC_HSREADY" pos="4" rst="-" access="r">
				<comment>The bit represent USBC HSREADY.</comment>
            </bits>
			<bits name="SYS_GOUDA_HSREADY" pos="5" rst="-" access="r">
				<comment>The bit represent GOUDA HSREADY.</comment>
            </bits>               
			<bits name="SYS_XCPU_RAM_HSREADY" pos="6" rst="-" access="r">
				<comment>The bit represent XCPU RAM HSREADY.</comment>
            </bits>              
			<bits name="SYS_HREADY" pos="7" rst="-" access="r">
				<comment>The bit represent Sys HSREADY which is sent to all sys AHB slaves.</comment>
			</bits>
		</ireg>

		<ireg name="AHB_BB_MASTER" protect="r">
			<comment>Debug information of baseband side AHB bus status.</comment>
			<bits name="BB_IFC_HMBURSREQ" pos="0" rst="-" access="r">
				<comment>The bit represent BB Ifc HMBURSREQ.</comment>
			</bits>
			<bits name="BB_VOC_HMBURSREQ" pos="1" rst="-" access="r">
				<comment>The bit represent Voc HMBURSREQ.</comment>
			</bits>
			<bits name="BB_AHB2AHB_HMBURSREQ" pos="2" rst="-" access="r">
				<comment>The bit represent BB Ahb2ahb HMBURSREQ.</comment>
			</bits>
			<bits name="BCPU_HMBRSREQ" pos="3" rst="-" access="r">
				<comment>The bit represent Bcpu HMBURSREQ.</comment>
			</bits>
			<bits name="BB_IFC_HMGRANT" pos="4" rst="-" access="r">
				<comment>The bit represent BB Ifc HMGRANT.</comment>
			</bits>
			<bits name="BB_VOC_HMGRANT" pos="5" rst="-" access="r">
				<comment>The bit represent Voc HMGRANT.</comment>
			</bits>
			<bits name="BB_AHB2AHB_HMGRANT" pos="6" rst="-" access="r">
				<comment>The bit represent BB Ahb2ahb HMGRANT.</comment>
			</bits>
			<bits name="BCPU_HMGRANT" pos="7" rst="-" access="r">
				<comment>The bit represent Bcpu HMGRANT.</comment>
			</bits>
		</ireg>

		<ireg name="AHB_BB_HSREADY" protect="r">
			<comment>Debug information of AHB bus status HSEL.</comment>
			<bits name="BB_MEM_HSREADY" pos="0" rst="-" access="r">
				<comment>The bit represent BB MEM HSREADY.</comment>
            </bits>
			<bits name="BB_VOC_HSREADY" pos="1" rst="-" access="r">
				<comment>The bit represent BB VoC HSREADY.</comment>
			</bits>
			<bits name="BB_SRAM_HSREADY" pos="2" rst="-" access="r">
				<comment>The bit represent BB Sram HSREADY.</comment>
			</bits>
			<bits name="BB_IFC_HSREADY" pos="3" rst="-" access="r">
				<comment>The bit represent BB Ifc HSREADY.</comment>
			</bits>
			<bits name="BB_AHB2AHB_HSREADY" pos="4" rst="-" access="r">
				<comment>The bit represent BB Ahb2ahb HSREADY.</comment>
			</bits>
			<bits name="BB_HREADY" pos="7" rst="-" access="r">
				<comment>The bit represent BB HREADY which is sent to all BB AHB slaves.</comment>
			</bits>
		</ireg>

		<ireg name="AHB_BB_HSEL" protect="r">
			<comment>Debug information of AHB bus status HSEL.</comment>
			<bits name="BB_MEM_EXT_HSEL" pos="0" rst="-" access="r">
				<comment>The bit represent BB MEM_EXT HSEL.</comment>
			</bits>
			<bits name="BB_MEM_INT_HSEL" pos="1" rst="-" access="r">
				<comment>The bit represent BB MEM_INT HSEL.</comment>
			</bits>
			<bits name="BB_VOC_HSEL" pos="2" rst="-" access="r">
				<comment>The bit represent BB VOC HSEL.</comment>
			</bits>
			<bits name="BB_SRAM_HSEL" pos="3" rst="-" access="r">
				<comment>The bit represent BB Sram HSEL.</comment>
			</bits>
			<bits name="BB_IFC_HSEL" pos="4" rst="-" access="r">
				<comment>The bit represent BB Ifc HSEL.</comment>
			</bits>
			<bits name="BB_AHB2AHB_HSEL" pos="5" rst="-" access="r">
				<comment>The bit represent BB Ahb2ahb HSEL.</comment>
			</bits>
		</ireg>

		<ireg name="AHB_SYS_MASK_SPLIT" protect="r">
            <comment>Represents the split status register of the SYS_AHBC.</comment>
            <bits name="Sys_Mask_Split" pos="SYS_NB_MASTERS-1:1" access="r" rst="-" cut="1" cutenum="Sys_Master_Id" cutprefix="Mask_Split" cutstart="1">
            </bits>
		</ireg>
		<ireg name="AHB_BB_MASK_SPLIT" protect="r">
            <comment>Represents the split status register of the BB_AHBC.</comment>
            <bits name="BB_Mask_Split" pos="BB_NB_MASTERS:1" access="r" rst="-" cut="1" cutenum="BB_Master_Id" cutprefix="Mask_Split" cutstart="1">
            </bits>
		</ireg>
        
	</module>

</archive>

<archive relative = "debug_host_test_chip.xml">

  <include file="debug_host.xml" />
  <include file="debug_host_internals.xml" />


</archive>


<archive relative = "debug_uart.xml">
<module name="debug_uart" category="System">
  <var  name="DEBUG_UART_RX_FIFO_SIZE"    value="16"  />
  <var  name="DEBUG_UART_TX_FIFO_SIZE"    value="16"  />
  <var  name="DEBUG_UART_NB_RX_FIFO_BITS" value="4"   />
  <var  name="DEBUG_UART_NB_TX_FIFO_BITS" value="4"   />
  <var  name="ESC_DAT"                    value="92"  />
  
  <reg protect="rw" name="ctrl">
    <bits access="rw" name="Enable" pos="0" rst="0">
      <options>
        <option name="DISABLE" value="0" />

        <option name="ENABLE" value="1" />

        <default />
      </options>

      <comment>Allows to turn off the UART:<br />0 = Disable<br />1 = Enable
      </comment>
    </bits>

    <bits access="rw" name="Data Bits" pos="1" rst="0">
      <options>
        <option name="7_BITS" value="0" />

        <option name="8_BITS" value="1" />

        <default />
      </options>

      <comment>Number of data bits per character (least significant bit
          first):<br />0 = 7 bits<br />1 = 8 bits <br /> This bit will be masked to
          '1' if debug host is enabled. </comment>
    </bits>

    <bits access="rw" name="Tx Stop Bits" pos="2" rst="0">
      <options>
        <option name="1_BIT" value="0" />

        <option name="2_BITS" value="1" />

        <default />
      </options>

      <comment>Stop bits controls the number of stop bits transmitted. Can
      receive with one stop bit (more inaccuracy can be compensated with two
      stop bits when divisor mode is set to 0).<br />0 = one stop bit is
      transmitted in the serial data.<br />1 = two stop bits are generated and
      transmitted in the serial data out. <br /> This bit will be masked to
      '0' if debug host is enabled. </comment>
    </bits>

    <bits access="rw" name="Parity Enable" pos="3" rst="0">
      <options>
        <option name="NO" value="0" />

        <option name="YES" value="1" />

        <default />
      </options>

      <comment> Parity is enabled when this bit is set. <br /> This bit will be masked to
      '0' if debug host is enabled. </comment>
    </bits>

    <bits access="rw" name="Parity Select" pos="5:4" rst="0">
      <options>
        <option name="ODD" value="0" />

        <option name="EVEN" value="1" />

        <option name="SPACE" value="2" />

        <option name="MARK" value="3" />

        <default />
      </options>

      <comment> Controls the parity format when parity is enabled:<br />00 =
      an odd number of received 1 bits is checked, or transmitted (the parity
      bit is included).<br />01 = an even number of received 1 bits is checked
      or transmitted (the parity bit is included).<br />10 = a space is
      generated and received as parity bit.<br />11 = a mark is generated and
      received as parity bit. <br /> These bit will be ignored if debug host is
      enabled. </comment>
    </bits>

    <bits access="rw" name="Tx Break Control" pos="6" rst="0">
      <comment> Sends a break signal by holding the Uart_Tx line low until
          this bit is cleared.<br /> This bit will be masked to '0' if debug host
          is enabled. </comment>
      <options>
        <option name="OFF" value="0" />
        <option name="ON"  value="1" />
        <default />
      </options>
    </bits>

   <bits access="rw" name="RX FIFO RESET" pos="7" rst="0">
      <comment>reset rx fifo. </comment>
   </bits>

   <bits access="rw" name="TX FIFO RESET" pos="8" rst="0">
      <comment>reset tx fifo. </comment>
   </bits>


    <bits access="rw" name="DMA Mode" pos="9" rst="0">
      <options>
        <option name="DISABLE" value="0" />

        <option name="ENABLE" value="1" />

        <default />
      </options>

      <comment>Enables the DMA signaling for the Uart_Dma_Tx_Req_H and
      Uart_Dma_Rx_Req_H to the IFC. </comment>
    </bits>

    <bits access="rw" name="SWRX flow ctrl" pos="13:12" rst="1">
        <comment> When this field is "00" and SWTX_flow_Ctrl is also "00", hardwre
            flow ctrl is used. Otherwise, software flow control is used: <br />
            00 = no transmit flow control. <br />
            01 = transmit XON1/XOFF1 as flow control bytes<br />
            10 = transmit XON2/XOFF2 as flow control bytes<br />
            11 = transmit XON1 and XON2/XOFF1 and XOFF2 as flow control bytes<br />
        </comment>
        <options><default/><mask/><shift/></options>
    </bits>

    <bits access="rw" name="SWTX flow ctrl" pos="15:14" rst="1">
        <comment> When this field is "00" and SWRX_flow_Ctrl is also "00", hardwre
            flow ctrl is used. Otherwise, software flow control is used: <br />
            00 = no receive flow control<br />
            01 = receive XON1/XOFF1 as flow control bytes<br />
            10 = receive XON2/XOFF2 as flow control bytes<br />
            11 = receive XON1 and XON2/XOFF1 and XOFF2 as flow control bytes<br />
            <br /> Note: If single XON/XOFF character is used for flow contol, the received 
            XON/XOFF character will not be put into Rx FIFO. This is also the case if XON is
            received when XOFF is expected. <br />
            If double XON/XOFF characters are expected, the XON1/XOFF1 must followed sequently 
            by XON2/XOFF2 to be considered as patterns, which will not be put into Rx FIFO. 
            Otherwise they will be considered as data. This is also the case if XOFF1 is followed
            by character other than XOFF2. <br />
        </comment>
        <options><default/><mask/><shift/></options>
    </bits>

    <bits access="rw" name="BackSlash En" pos="16" rst="1">
        <comment> When soft flow control characters or backslash are encountered in the data file, 
            they will be inverted and a backslash will be added before them. for example, if tx data
            is XON(0x11) with BackSlash_En = '1', then uart will send 5Ch(Backslash) + EEh (~XON).
        </comment>
    </bits>    
    
    <bits access="rw" name="Tx Finish n Wait" pos="19" rst="0">
      <comment>When this bit is set the Tx engine terminates to send the
      current byte and then it stops to send data.</comment>
    </bits>

    <bits access="rw" name="Divisor Mode" pos="20" rst="0">
      <comment>Selects the divisor value used to generate the baud rate
      frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA
      is enable, this bit is ignored and the divisor used will be 16.<br />0 =
      (BCLK = SCLK / 4)<br />1 = (BCLK = SCLK / 16) <br /> This bit will be
      masked to '0' if debug host is enabled.</comment>
    </bits>

    <bits access="rw" name="IrDA Enable" pos="21" rst="0">
      <comment>When set, the UART is in IrDA mode and the baud rate divisor
      used is 16 (see UART Operation for details). <br /> This bit will be
      masked to '0' if debug host is enabled. </comment>
    </bits>

    <bits access="rw" name="Rx RTS" pos="22" rst="0">
      <comment>Controls the Uart_RTS output (not directly in auto flow control
      mode).<br />0 = the Uart_RTS will be inactive high<br />1 = the Uart_RTS
      will be active low <br /> This bit will be masked to '1' if debug host is
      enabled. </comment>
      <options>
        <option name="INACTIVE" value="0" />
        <option name="ACTIVE"  value="1" />
        <default />
      </options>
    </bits>

    <bits access="rw" name="Auto Flow Control" pos="23" rst="0">
      <options>       
        <option name="ENABLE" value="1" />
        
        <option name="DISABLE" value="0" />
        
        <default />
      </options>
      <comment>Enables the auto flow control. <br/> 
          In case HW flow control (both swTx_Flow_ctrl=0 and swRx_Flow_Ctrl=0),
          If Auto_Flow_Control is enabled, Uart_RTS is controlled by the Rx RTS bit in 
          CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx
          Fifo Level and AFC_Level in Triggers register). 
          Tx data flow is stopped If Uart_CTS become inactive high.<br/>
          If Auto_Flow_Control is disabled, Uart_RTS is controlled only by the Rx RTS
          bit in CMD_Set register. Uart_CTS will not take effect. <br/><br/>

          In case SW flow control(either swTx_Flow_ctrl/=0 or swRx_Flow_Ctrl/=0),
          If Auto_Flow_Control is enabled, XON/XOFF will be controlled by the Rx RTS bit
          in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx
          Fifo Level and AFC_Level in Triggers register). <br/>
          If Auto_Flow_Control is disabled, XON/XOFF will be controlled only by Rx RTS bit
          in CMD_Set register. Tx data flow will be stoped when XOFF is received either
          this bit is enable or disabled.<br/>
          <br /> This bit will be masked to '1' if debug host is enabled.
      </comment>
    </bits>

    <bits access="rw" name="Loop Back Mode" pos="24" rst="0">
      <comment>When set, data on the Uart_Tx line is held high, while the
      serial output is looped back to the serial input line, internally. In
      this mode all the interrupts are fully functional. This feature is used
      for diagnostic purposes. Also, in loop back mode, the modem control
      input Uart_CTS is disconnected and the modem control output Uart_RTS are
      looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is
      inverted (see IrDA SIR Mode Support). </comment>
    </bits>

    <bits access="rw" name="Rx Lock Err" pos="25" rst="0">
      <comment>Allow to stop the data receiving when an error is detected
      (framing, parity or break). The data in the fifo are kept. <br /> This bit 
      will be masked to '0' if debug host is enabled. </comment>
      <options>
        <option name="DISABLE" value="0" />
        <option name="ENABLE" value="1" />
        <default />
      </options>
    </bits>

    <bits access="rw" name="HST TXD oen" pos="26" rst="0">
      <comment>HST TXD output enable. '0' enable.</comment>
      <options>
        <option name="DISABLE" value="1" />
        <option name="ENABLE" value="0" />
        <default />
      </options>
    </bits>

    <bits access="rw" name="Rx Break Length" pos="31:28" rst="0xF">
      <comment>Length of a break, in number of bits. <br /> This bit will be masked
      to "1011" if debug host is enabled. </comment>
    </bits>
  </reg>

  <reg protect="r" name="status">
    <bits access="r" name="Rx Fifo Level" pos="4:0" rst="0">
        <options>
            <mask/>
            <shift/>
        </options>
    <comment>Those bits indicate the number of data available in the Rx
      Fifo. Those data can be read. </comment>
    </bits>

    <bits access="r" name="Tx Fifo Level" pos="12:8" rst="0">
         <options>
            <mask/>
            <shift/>
        </options>
      <comment>Those bits indicate the number of data available in the Tx
      Fifo. Those data will be sent. </comment>
    </bits>

    <bits access="r" name="Tx Active" pos="13" rst="0">
      <comment>This bit indicates that the UART is sending data. If no data is
      in the fifo, the UART is currently sending the last one through the
      serial interface. </comment>
    </bits>

    <bits access="r" name="Rx Active" pos="14" rst="0">
      <comment>This bit indicates that the UART is receiving a byte.
      </comment>
    </bits>

    <bits access="r" name="Rx Overflow Err" pos="16" rst="0">
      <comment>This bit indicates that the receiver received a new character
      when the fifo was already full. The new character is discarded. This bit
      is cleared when the UART_STATUS register is written with any value.
      </comment>
    </bits>

    <bits access="r" name="Tx Overflow Err" pos="17" rst="0">
      <comment>This bit indicates that the user tried to write a character when fifo was
          already full. The written data will not be kept. This bit is cleared when 
          the UART_STATUS register is written with any value. </comment>
    </bits>

    <bits access="r" name="Rx Parity Err" pos="18" rst="0">
      <comment>This bit is set if the parity is enabled and a parity error
      occurred in the received data. This bit is cleared when the UART_STATUS
      register is written with any value. </comment>
    </bits>

    <bits access="r" name="Rx Framing Err" pos="19" rst="0">
      <comment>This bit is set whenever there is a framing error occured. A
      framing error occurs when the receiver does not detect a valid STOP bit
      in the received data. This bit is cleared when the UART_STATUS register
      is written with any value. </comment>
    </bits>

    <bits access="r" name="Rx Break Int" pos="20" rst="0">
      <comment>This bit is set whenever the serial input is held in a logic 0
      state for longer than the length of x bits, where x is the value
      programmed Rx Break Length. A null word will be written in the Rx Fifo.
      This bit is cleared when the UART_STATUS register is written with any
      value. </comment>
    </bits>

    <bits access="r" name="Tx DCTS" pos="24" rst="0">
      <comment>In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), 
            This bit is set when the Uart_CTS line changed since the last
            time this register has been written. <br/>
            In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), 
            This bit is set when received XON/XOFF status changed since the last time
            this register has been writtern. <br/>
            This bit is cleared when the UART_STATUS register is written with any value. 
       </comment>
    </bits>

    <bits access="r" name="Tx CTS" pos="25" rst="0">
        <comment>In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0),
            current value of the Uart_CTS line. 
            <br/> '1' = Tx not allowed. 
            <br/> '0' = Tx allowed. 
            <br/>In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0),
            current state of software flow control.
            <br/> '1' = when XOFF received. 
            <br/> '0' = when XON received. 
        </comment>
    </bits>

    <bits access="r" name="Tx Fifo Rsted L" pos="28" rst="0">
      <comment>This bit is set when Tx Fifo Reset command is received by CTRL
      register and is cleared when Tx fifo reset process has finished.      
      </comment>
    </bits>

    <bits access="r" name="Rx Fifo Rsted L" pos="29" rst="0">
      <comment>This bit is set when Rx Fifo Reset command is received by CTRL
      register and is cleared when Rx fifo reset process has finished.      
      </comment>
    </bits>
    
    <bits access="r" name="Enable n finished" pos="30" rst="0">
      <comment>This bit is set when bit enable is changed from '0' to '1' or 
      from '1' to '0', it is cleared when the enable process has finished.      
      </comment>
    </bits>
    
    <bits access="r" name="Clk Enabled" pos="31" rst="0">
      <comment>This bit is set when Uart Clk has been enabled and received by
      UART after Need Uart Clock becomes active. It serves to avoid enabling
      Rx RTS too early.</comment>
    </bits>
  </reg>

  <reg protect="--" name="rxtx_buffer">
    <bits access="r" name="Rx Data" pos="7:0" rst="no">
      <comment>The UART_RECEIVE_BUFFER register is a read-only register that
      contains the data byte received on the serial input port. This register
      accesses the head of the receive FIFO. If the receive FIFO is full and
      this register is not read before the next data character arrives, then
      the data already in the FIFO will be preserved but any incoming data
      will be lost. An overflow error will also occur. </comment>
    </bits>

    <bits access="w" name="Tx Data" pos="7:0" rst="no">
      <comment>The UART_TRANSMIT_HOLDING register is a write-only register
      that contains data to be transmitted on the serial output port. 16
      characters of data may be written to the UART_TRANSMIT_HOLDING register
      before the FIFO is full. Any attempt to write data when the FIFO is full
      results in the write data being lost. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="irq_mask">
    <bits access="rw" name="Tx Modem Status" pos="0" rst="0">
        <comment>Clear to send signal change or XON/XOFF detected. </comment>
    </bits>

    <bits access="rw" name="Rx Data Available" pos="1" rst="0">
      <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx
      Fifo trigger level). </comment>
    </bits>

    <bits access="rw" name="Tx Data Needed" pos="2" rst="0">
      <comment>Tx Fifo at or below threshold level (current level &lt;= Tx
      Fifo trigger level). </comment>
    </bits>

    <bits access="rw" name="Rx Timeout" pos="3" rst="0">
      <comment>No characters in or out of the Rx Fifo during the last 4
      character times and there is at least 1 character in it during this
      time. </comment>
    </bits>

    <bits access="rw" name="Rx Line Err" pos="4" rst="0">
      <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break
      Interrupt. </comment>
    </bits>

    <bits access="rw" name="Tx Dma Done" pos="5" rst="0">
      <comment>Pulse detected on Uart_Dma_Tx_Done_H signal. </comment>
    </bits>

    <bits access="rw" name="Rx Dma Done" pos="6" rst="0">
      <comment>Pulse detected on Uart_Dma_Rx_Done_H signal. </comment>
    </bits>

    <bits access="rw" name="Rx Dma Timeout" pos="7" rst="0">
      <comment>In DMA mode, there is at least 1 character that has been read 
            in or out the Rx Fifo. Then before received Rx DMA Done, No characters 
            in or out of the Rx Fifo during the last 4 character times.</comment>
        </bits>

    <bits access="rw" name="XOFF_detected" pos="8" rst="0">
    </bits>
    
  </reg>

  <reg protect="rw" name="irq_cause">
    <bits access="r" name="Tx Modem Status" pos="0" rst="0">
      <comment>Clear to send signal detected. Reset control: This bit is
      cleared when the UART_STATUS register is written with any value.
      </comment>
    </bits>

    <bits access="r" name="Rx Data Available" pos="1" rst="0">
      <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx
      Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER
      until the Fifo drops below the trigger level. </comment>
    </bits>

    <bits access="r" name="Tx Data Needed" pos="2" rst="0">
      <comment>Tx Fifo at or below threshold level (current level &lt;= Tx
      Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING
      register above threshold level. </comment>
    </bits>

    <bits access="r" name="Rx Timeout" pos="3" rst="0">
      <comment>No characters in or out of the Rx Fifo during the last 4
      character times and there is at least 1 character in it during this
      time. Reset control: Reading from the UART_RECEIVE_BUFFER register.
      </comment>
    </bits>

    <bits access="r" name="Rx Line Err" pos="4" rst="0">
      <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break
      Interrupt. Reset control: This bit is cleared when the UART_STATUS
      register is written with any value. </comment>
    </bits>

    <bits access="rw" name="Tx Dma Done" pos="5" rst="0">
      <comment>This interrupt is generated when a pulse is detected on the
      Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register.
      </comment>
    </bits>

    <bits access="rw" name="Rx Dma Done" pos="6" rst="0">
      <comment>This interrupt is generated when a pulse is detected on the
      Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register.
      </comment>
    </bits>

    <bits access="rw" name="Rx Dma Timeout" pos="7" rst="0">
        <comment>In DMA mode, there is at least 1 character that has been read 
            in or out the Rx Fifo. Then before received Rx DMA Done, No characters 
            in or out of the Rx Fifo during the last 4 character times.</comment>
    </bits>

    <bits access="r" name="Tx Modem Status U" pos="16" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Data Available U" pos="17" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Tx Data Needed U" pos="18" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Timeout U" pos="19" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Line Err U" pos="20" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Tx Dma Done U" pos="21" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Dma Done U" pos="22" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Dma Timeout U" pos="23" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="triggers">
    <bits access="rw" name="Rx Trigger" pos="3:0" rst="0">
      <comment>Defines the threshold level at which the Data Available
      Interrupt will be generated. <br />The Data Available interrupt is
      generated when quantity of data in Rx Fifo &gt; Rx Trigger.</comment>
    </bits>

    <bits access="rw" name="Tx Trigger" pos="7:4" rst="0">
      <comment>Defines the threshold level at which the Data Needed
      Interrupt will be generated.<br />The Data Needed Interrupt is generated
      when quantity of data in Tx Fifo &lt;= Tx Trigger.</comment>
    </bits>

    <bits access="rw" name="AFC Level" pos="11:8" rst="0">
      <comment>Controls the Rx Fifo level at which the Uart_RTS Auto Flow
      Control will be set inactive high (see UART Operation for more details
      on AFC).<br />The Uart_RTS Auto Flow Control will be set inactive high
      when quantity of data in Rx Fifo &gt; AFC Level.</comment>
    </bits>
  </reg>
  <reg protect="rw" name="XChar">
    <bits access="rw" name="XON1" pos="7:0" rst="17">
        <comment>XON1 character value. Reset Value is CTRL-Q 0x11.</comment>
    </bits>
    <bits access="rw" name="XOFF1" pos="15:8" rst="19">
        <comment>XOFF1 character value. Reset Value is CTRL-S 0x13</comment>
    </bits>
    <bits access="rw" name="XON2" pos="23:16" rst="0">
        <comment>XON2 character value. </comment>
    </bits>
    <bits access="rw" name="XOFF2" pos="31:24" rst="0">
        <comment>XOFF2 character value. </comment>
    </bits>
    <comment> These characters must respect following constraints: They must be different if used in software control, if BackSlash_En='1', they cannot be '\' and they cannot be complementary to each other, for example neither XON1 = ~XOFF1 nor XON1 = ~'\' is permitted. </comment>
  </reg>
  
</module>
</archive>

<archive relative = "dma.xml">
<module name="dma" category="System">
  <reg protect="w" name="get_channel">
    <bits access="r" name="Get Channel" pos="0" rst="1">
      <comment>Returns 1 and locks the DMA channel for a transaction if it is
      available. Else returns 0. <br />Clear the transfer done interrupt
      status. </comment>
    </bits>
  </reg>

  <reg protect="r" name="status">
    <bits access="r" name="Enable" pos="0" rst="0">
      <comment>Status of the DMA: 1 if enabled, 0 if disabled. </comment>
    </bits>

    <bits access="r" name="Int Done Cause" pos="1" rst="0">
      <comment>Cause of the interrupt. This bit is set when the transfer is
      done and the interrupt mask bit is set. <br />Write one in the Int Clear
      or write 0 in Enable control bits to clear Int Done Cause bit.
      </comment>
    </bits>

    <bits access="r" name="Int Done Status" pos="2" rst="0">
      <comment>Status of the interrupt. Status of the transfer: 1 if the
      transfer is finished, 0 if it is not finished. <br />Write one in the
      Int Clear or write 0 in Enable control bits to clear Int Done Status
      bit. </comment>
    </bits>

    <bits access="r" name="Channel Lock" pos="4" rst="0">
      <comment>Actual status of channel lock. Channel is unlocked at the end
      of transaction or when the DMA is disabled. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="control">
    <bits access="rw" name="Enable" pos="0" rst="0">
      <comment>Controls the DMA. Write 1 to enable the DMA, write 0 to disable
      it. When 0 is written in this register, the Int Done Status and Cause
      bits are reset. </comment>
    </bits>

    <bits access="rw" name="Int Done Mask" pos="1" rst="0">
      <comment>End of transfer interrupt generation. When 1, the DMA will send
      an interrupt at transaction completion. </comment>
      <options>
        <shift/>
      </options>  
    </bits>

    <bits access="rw" name="Int Done Clear" pos="2" rst="0">
      <comment>Clear the transfer done interruption (this will clear Int Done
      Status and Int Done Cause). <br />This bit is auto-clear. You will
      always read 0 here. </comment>
    </bits>

    <bits access="rw" name="Use Pattern" pos="4" rst="0">
      <comment>If this bit is set, the source address will be ignored and the
      memory will be fill with the value of the pattern register. </comment>
    </bits>

    <bits access="rw" name="max_burst_length" pos="6:5" rst="00">
      <comment>Set the MAX burst length. 
        <br/> The 2'b10 mean burst max 16, 2'b01 mean burst max 8, 00 mean burst max 4. 
      </comment>
    </bits>

    <bits access="w" name="Stop Transfer" pos="8" rst="0">
      <comment>The DMA stop the current transfer and flush his FIFO (write
      only bit). When the FIFO is empty and last write performed, the DMA is
      disabled and available for a next transfer. The number of bytes copied
      is readable on DMA_XFER_SIZE register.</comment>
    </bits>

    <bits access="rw" name="GEA Enable" pos="12" rst="0">
      <options>
        <option name="DMA" value="0" />

        <option name="GEA" value="1" />

        <default />
      </options>

      <comment>Enable Gea process when 1.</comment>
    </bits>

    <bits access="rw" name="GEA Algorithm" pos="13" rst="1">
      <options>
        <option name="GEA1" value="0" />

        <option name="GEA2" value="1" />

        <default />
      </options>

      <comment>This field sets the type of GEA algorithm to process.</comment>
    </bits>

    <bits access="rw" name="GEA Direction" pos="14" rst="1">
      <options>
        <shift/>
      </options>
      <comment>This field selects the Direction in the GEA algorithm.
      </comment>
    </bits>

    <bits access="rw" name="FCS Enable" pos="16" rst="0">
      <options>
        <option name="NORMAL_DMA" value="0" />

        <option name="FCS_PROCESS" value="1" />

        <default />
      </options>

      <comment>Enable FCS process when 1.</comment>
    </bits>

    <bits access="rw" name="Dst Addr Mgt" pos="21:20" rst="0">
      <options>
        <option name="NORMAL_DMA" value="0" />

        <option name="CONST_ADDR" value="1" />

        <option name="ALTERN_ADDR" value="2" />

        <option name="RESERVED" value="3" />

        <default />
      </options>

      <comment>Destination address management.<br />00 : Normal DMA operation,
      DMA_DST_ADDR register define the destination address.<br /> 01 : DMA
      write address is constant (no incremented) and defined by the
      DMA_DST_ADDR register. All data write are in 16-bit.<br /> 10 : DMA
      write address is alternatively defined by DMA_DST_ADDR and
      DMA_SD_DST_ADDR registers. All data write are in 16-bit. <br />In this
      configuration, DMA write operation is alternatively: <br />DMA_DST_ADDR
      &lt;= DMA_PATTERN register <br />DMA_SD_DST_ADDR &lt;=
      Data[DMA_SRC_ADDR] <br />11 : reserved </comment>
    </bits>
  </reg>

  <reg protect="rw" name="src_addr">
    <bits access="rw" name="Src Address" pos="27:0" rst="0xFFFFFFF">
      <comment>Source start read byte address. When a transfer is stalled by
      the Stop_Transfer bit, this register give the next current source
      address, which is directly the value to re-program to complete the
      transfer stopped.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="dst_addr">
    <bits access="rw" name="Dst Address" pos="27:0" rst="0xFFFFFFF">
      <comment>Destination start read byte address. When a transfer is stalled
      by the Stop_Transfer bit, this register give the next current
      destination address, which is directly the value to re-program to
      complete the transfer stopped.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="sd_dst_addr">
    <bits access="rw" name="Sd Dst Address" pos="27:0" rst="0xFFFFFFF">
      <comment>Second destination address. This register is only used when
      Dst_Address_Mgt=10.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="xfer_size">
    <bits access="rw" name="Transfer Size" pos="17:0" rst="0x3FFFF">
      <comment>Transfer size in bytes. Maximum: 262144 bytes. When a transfer
      is stopped by the Stop_Transfer bit, this register give the number of
      remainder bytes to transfer.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="pattern">
    <bits access="rw" name="Pattern" pos="31:0" rst="0xFFFFFFFF">
      <comment>Value taken to fill the memory when the configuration bit Use
      Pattern is set. When the pattern mode is used the destination address
      must be 32-bit aligned and the transfer size multiple of 4. when
      Dst_Address_Mgt=10 Pattern is the data written at the address given by
      the Dst_Address register.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gea_kc_low">
    <bits access="rw" name="KC_LSB" pos="31:0" rst="0xFFFFFFFF">
      <comment>GEA key Kc, LSB bit [31:0]. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gea_kc_high">
    <bits access="rw" name="KC_MSB" pos="31:0" rst="0xFFFFFFFF">
      <comment>GEA key Kc, MSB bit [31:0]. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gea_messkey">
    <bits access="rw" name="MessKey" pos="31:0" rst="0xFFFFFFFF">
      <comment>MessKey (Input) register. </comment>
    </bits>
  </reg>

  <reg protect="r" name="fcs">
    <bits access="r" name="FCS" pos="23:0" rst="0">
      <comment>Frame Check Sequence.</comment>
    </bits>

    <bits access="r" name="FCS Correct" pos="31" rst="0">
      <comment>The FCS is correct in reception when the final remainder is
      equal to C(x)= x^22 + x^21 + x^19 + x^18 + x^16 + x^15 + x^11 + x^8 +
      x^5 + x^4</comment>
    </bits>

    
  </reg>
</module>
</archive>

<archive relative = "ela.xml">

<var name="NUM_TRIG_STATES" value="4" />
<var name="ID_CAPTURE_SIZE" value="10" />
<var name="RAM_ADDR_SIZE" value="10" />

<module name="ela" category="Debug">

  <reg protect="rw" name="ctrl">
    <comment> logic analyzer control register</comment>
    <bits access="rw" name="run" pos="0" rst="0x0">
      <comment>
        run control.
        <br />0 ela-500 disabled. register programming permitted.
        <br />1 ela-500 enabled.
      </comment>
    </bits>
  </reg>
  <reg protect="rw" name="timectrl">
    <comment> timestamp control register</comment>
    <bits access="rw" name="tsen" pos="16" rst="0x0">
      <comment>
        timestamp enable.
      </comment>
    </bits>
    <bits access="rw" name="tsint" pos="15:12" rst="0x0">
      <comment>
        timestamp interval.
        <br />when timestamps are enabled, tsint specifies the bit number of the 16-bit trace counter that causes a timestamp
        packet to be requested. the trace counter runs from elaclk. when the specified bit changes, a timestamp
        packet is requested to be inserted into the trace sram when there is an elaclk cycle during which trace data is
        not being captured. the ela-500 does not insert back-to-back timestamps in the sram, even when tsint
        causes multiple requests to be made.
        <br />when tsint = 0, a timestamp is written when action.trace disables trace. looping trigger states enable
        and then disable trace, causing timestamp writes. a timestamp is always written when ctrl.run is cleared and
        the previous trace write contained a data payload.
      </comment>
    </bits>
    <bits access="rw" name="reserved" pos="11:8" rst="0x0">
      <comment>
        -
      </comment>
    </bits>
    <bits access="rw" name="tcsel1" pos="7:4" rst="0x0">
      <comment>
        trace counter 1 select.
        <br />selects the bit number of the 16-bit trace counter that is presented as trace counter[1] in the sram header byte.
      </comment>
    </bits>
    <bits access="rw" name="tcsel0" pos="3:0" rst="0xb">
      <comment>
        trace counter 0 select.
        <br />selects the bit number of the 16-bit trace counter that is presented as trace counter[0] in the sram header byte.
      </comment>
    </bits>
  </reg>
  <reg protect="rw" name="tssr">
    <comment> trigger state select register</comment>
    <bits access="rw" name="altts" pos="7:0" rst="0x0">
      <comment>
        each bit identifies the trigger state that enables independent trace. only trigger state 4 supports independent trace.
        <br />altts[4]=0 trigger state 4 independent trace disabled.
        <br />altts[4]=1 trigger state 4 independent trace enabled.
        <br />all other bits read zero.
      </comment>
    </bits>
  </reg>
  <hole size="32" />
  <reg protect="rw" name="ptaction">
    <comment> pre-trigger action register</comment>
    <bits access="rw" name="elaoutput" pos="7:4" rst="0x0">
      <comment>
        sets the value to drive on elaoutput[3:0].
      </comment>
    </bits>
    <bits access="rw" name="trace" pos="3" rst="0x0">
      <comment>
        enables trace.
      </comment>
    </bits>
    <bits access="rw" name="stopclock" pos="2" rst="0x0">
      <comment>
        sets the level to drive on stopclock.
      </comment>
    </bits>
    <bits access="rw" name="cttrigout" pos="1:0" rst="0x0">
      <comment>
        sets the value to drive on cttrigout[1:0].
      </comment>
    </bits>
  </reg>
  <hole size="96" />
  <reg protect="ro" name="ctsr">
    <comment> current trigger state register</comment>
    <bits access="ro" name="finalstate" pos="31" rst="0x0">
      <comment>
        0 ela-500 is still tracing.
        <br />1 indicates that the ela-500 has stopped advancing trigger states and stopped trace.
        <br />finalstate can be set by trigctrl.countbrk reaching the final loop count,
        or by programming nextstate or altnextstate to zero.
      </comment>
    </bits>
    <bits access="ro" name="reserved" pos="30:NUM_TRIG_STATES" rst="0x0">
      <comment>
        -
      </comment>
    </bits>
    <bits access="ro" name="ctsr" pos="NUM_TRIG_STATES-1:0" rst="0x1">
      <comment>
        reads current trigger state. this is a one-hot encoded field.
        <br />when ctrl.run:
        <br />0 raz
        <br />1 returns current trigger state.
        <br />if finalstate is 1, then the ctsr field gives the trigger state when finalstate
        became 1.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="ccvr">
    <comment> current counter value register</comment>
    <bits access="ro" name="ccvr" pos="31:0" rst="0x0">
      <comment>
        returns the counter value when the ctsr was last read. if the ctsr has never been read, then the value in the ccvr
        is undefined.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="cavr">
    <comment> current action value register</comment>
    <bits access="ro" name="elaoutput" pos="7:4" rst="0x00">
      <comment>
        value driven on elaoutput[3:0].
      </comment>
    </bits>
    <bits access="ro" name="trace" pos="3" rst="0x00">
      <comment>
        trace active.
        <br />0b0 trace is not active.
        <br />0b1 trace is active.
      </comment>
    </bits>
    <bits access="ro" name="stopclock" pos="2" rst="0x00">
      <comment>
        level driven on stopclock.
        <br />0b0 0 driven on stopclock.
        <br />0b1 1 driven on stopclock.
      </comment>
    </bits>
    <bits access="ro" name="cttrigout" pos="1:0" rst="0x00">
      <comment>
        value driven on cttrigout[1:0].
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="rdcaptid">
    <comment> read captured transaction id register</comment>
    <bits access="ro" name="rdcaptid" pos="ID_CAPTURE_SIZE-1:0" rst="-">
      <comment>
        returns the captured transaction id.
      </comment>
    </bits>
  </reg>
  <hole size="128" />
  <reg protect="rw" name="rrar">
    <comment> ram read address register</comment>
    <bits access="rw" name="rra" pos="RAM_ADDR_SIZE-1:0" rst="-">
      <comment>
        ram read address.
        <br />writes to the rra cause the trace sram data at that address to be transferred into the holding
        register.
        <br />after the sram read data is transferred to the holding register, rra increments by one. this
        prepares the rra address for sequential rrdr reads.
        <br />the rra automatically increments after apb reads from the rrdr have read the contents of the
        holding register. an rrdr read of the last data in the holding register initiates a read to sram at
        the address pointed to by the rra. the holding register is filled with the data at this address, then
        the rra increments.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="rrdr">
    <comment> ram read data register</comment>
    <bits access="ro" name="rrd" pos="31:0" rst="-">
      <comment>
        reads sram data from the holding register.
        <br />reads from the rrd return the sram data from the holding register. the first read of the rrd after an rrar update
        returns the trace data header byte value, zero-extended to 32 bits. subsequent reads of the rrd return 32-bit chunks of
        the trace data payload, starting with the least significant word, until all the payload data has been read, that is, two
        words if grp_width = 64, four words if grp_width = 128, and eight words if grp_width = 256.
        <br />when the final 32 bits of the payload have been read, the rra is incremented automatically, and the next word of
        sram data is copied into the holding register. this enables the sram data content to be read out efficiently.
        <br />the rra wraps to address zero if it is incremented beyond the maximum depth of the sram.
      </comment>
    </bits>
  </reg>
  <reg protect="rw" name="rwar">
    <comment> ram write address register</comment>
    <bits access="rw" name="wrap" pos="31" rst="-">
      <comment>
        the wrap bit is set when the ram write address is incremented beyond 2ram_addr_size while
        <br />the ela-500 is capturing trace data. the wrap bit is not set by writes to the rwdr that cause the
        <br />ram write address to roll over. software must clear the wrap bit when writing to the rwar.
      </comment>
    </bits>
    <bits access="rw" name="rwa" pos="RAM_ADDR_SIZE-1:0" rst="-">
      <comment>
        ram write address.
        <br />writes to the rwa set the sram address for data that is then written through the rwdr.
        <br />reads from the rwa return the address of the sram location that is to be written next, either by
        writes to the rwdr, or by the trace unit.
        <br />when trace is stopped, the rwa contains the address of the last sram location that was written
        plus one. if the ram write address was incremented beyond the depth of the ram while the
        ela-500 was capturing trace data, the wrap bit is set.
        <br />the rwar is automatically incremented by apb writes to the sram through the rwdr.
      </comment>
    </bits>
  </reg>
  <reg protect="wo" name="rwdr">
    <comment> ram write data register</comment>
    <bits access="wo" name="rwdr" pos="31:0" rst="-">
      <comment>
        writes data to the write holding register and initiates an sram write when the write holding register is full.
        writes to the rwd update the internal write holding register.
        <br />the first write to the rwd sets the header byte value from the least significant byte written. subsequent writes to the
        rwd set 32-bit chunks of the payload, starting with the least significant chunk. when the final 32 bits of the payload
        have been written, the content of the holding register is copied into the sram and the rwa is incremented
        automatically.
      </comment>
    </bits>
  </reg>
  <hole size="1408" />
  <struct count="NUM_TRIG_STATES" name="trig_state">
    <reg protect="rw" name="sigsel">
      <comment>signal select registers</comment>
      <bits access="rw" name="reserved" pos="31:12" rst="-">
        <comment>
          -
        </comment>
      </bits>
      <bits access="rw" name="sigsel" pos="11:0" rst="-">
        <comment>
          selects signal group.
          <br />0x1 selects signal group 0.
          <br />0x2 selects signal group 1.
          <br />0x4 selects signal group 2.
          <br />0x8 selects signal group 3.
          <br />0x10 selects signal group 4.
          <br />0x20 selects signal group 5.
          <br />0x40 selects signal group 6.
          <br />0x80 selects signal group 7.
          <br />0x100 selects signal group 8.
          <br />0x200 selects signal group 9.
          <br />0x400 selects signal group 10.
          <br />0x800 selects signal group 11.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="trigctrl">
      <comment>trigger control registers</comment>
      <bits access="rw" name="altcompsel" pos="15" rst="-">
        <comment>
          selects the alternative comparison mode:
          <br />0b0 trigger signal alternative comparisons selected.
          <br />0b1 trigger counter alternative comparisons selected.
        </comment>
      </bits>
      <bits access="rw" name="altcomp" pos="14:12" rst="-">
        <comment>
          trigger signal alternative comparison type select:
          <br />0b000 trigger signal alternative comparisons disabled.
          <br />0b001 alternative compare type is equal (==).
          <br />0b010 alternative compare type is greater than (&gt;).
          <br />0b011 alternative compare type is greater than or equal (&gt;=).
          <br />0b101 alternative compare type is not equal (!=).
          <br />0b110 alternative compare type is less than (&lt;).
          <br />0b111 alternative compare type is less than or equal (&lt;=).
        </comment>
      </bits>
      <bits access="rw" name="captid" pos="11:10" rst="-">
        <comment>
          <br />0b00 disable use of the captured id for signal comparisons.
          <br />0b01 capture id when trigger signal condition matches.
          the id is captured, from signalgrp[id_capture_size-1:0].
          <br />0b10 use the captured id instead of the target value in sigcomp[id_capture_size-1:0] for
          comparison of signalgrp[id_capture_size-1:0].
          <br />0b11 use the captured id instead of the signalgrp[id_capture_size-1:0] for a comparison
          against sigcomp[id_capture_size-1:0].
        </comment>
      </bits>
      <bits access="rw" name="countbrk" pos="9" rst="-">
        <comment>
          loop counter break.
          <br />the loop counter break uses the trigger state counter to break loops between trigger states after a trigger
          counter comparison. when the counter comparison matches, the trigger state goes to a final state, which
          stops trace writes and leaves the output actions at the previous trigger state action value.
          <br />0b0 normal operation.
          <br />0b1 break trigger state loop: a counter comparison match causes a transition to the
          final state, otherwise go to the nextstate trigger state as the counter
          increments.
        </comment>
      </bits>
      <bits access="rw" name="countclr" pos="8" rst="-">
        <comment>
          counter clear.
          <br />0b0 do not clear the counter value when moving to a different nextstate.
          <br />0b1 clear the counter value when moving to a different nextstate.
          <br />note: trigctrl.watchrst must be 0b0 when using this feature.
        </comment>
      </bits>
      <bits access="rw" name="trace" pos="7:6" rst="-">
        <comment>
          trace capture control.
          <br />0b00 trace is captured when trigger signal comparison succeeds.
          <br />0b01 trace is captured when trigger counter comparison succeeds.
          <br />0b10 trace is captured every elaclk cycle.
          <br />0b11 reserved.
        </comment>
      </bits>
      <bits access="rw" name="countsrc" pos="5" rst="-">
        <comment>
          counter source select.
          <br />0b0 counter is incremented every elaclk cycle.
          <br />0b1 counter is incremented when trigger signal comparison matches.
        </comment>
      </bits>
      <bits access="rw" name="watchrst" pos="4" rst="-">
        <comment>
          counter reset.
          <br />0b0 do not reset the counter after a trigger signal comparison match.
          <br />0b1 reset the counter after a trigger signal comparison match.
          <br />the counter acts like an activity watchdog timer, only allowing advancement to the
          next trigger state when the trigger counter comparison is reached. the counter is
          reset by a signal comparison.
        </comment>
      </bits>
      <bits access="rw" name="compsel" pos="3" rst="-">
        <comment>
          comparison mode. acts as both a counter enable and a select for the comparison mode.
          <br />0b0 disable counters and select trigger signal comparison mode.
          <br />0b1 enable counters and select trigger counter comparison mode.
        </comment>
      </bits>
      <bits access="rw" name="comp" pos="2:0" rst="-">
        <comment>
          trigger signal comparison type select.
          <br />0b000 trigger signal comparisons disabled. the enabled counters count clocks
          immediately after the trigger state has been entered and generate a programmable
          output action and transition to the next trigger state when the counter compare
          register count is reached, that is when a trigger counter comparison match
          occurs.
          <br />0b001 compare type is equal (==).
          <br />0b010 compare type is greater than (&gt;).
          <br />0b011 compare type is greater than or equal (&gt;=).
          <br />0b101 compare type is not equal (!=).
          <br />0b110 compare type is less than (&lt;).
          <br />0b111 compare type is less than or equal (&lt;=).
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="nextstate">
      <comment>next state registers</comment>
      <bits access="rw" name="nextstate" pos="NUM_TRIG_STATES-1:0" rst="-">
        <comment>
          selects the next state to move to after the trigger condition has been met in the current
          state.
          <br />0x0 do not change state. this is the final trigger state.
          <br />0x1 selects trigger state 0.
          <br />0x2 selects trigger state 1.
          <br />0x4 selects trigger state 2.
          <br />0x8 selects trigger state 3.
          <br />0x10 selects trigger state 4, when num_trig_states=5.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="action">
      <comment>action registers</comment>
      <bits access="rw" name="elaoutput" pos="7:4" rst="0x00">
        <comment>
          value to drive on elaoutput[3:0].
        </comment>
      </bits>
      <bits access="rw" name="trace" pos="3" rst="0x00">
        <comment>
          trace active.
          <br />0b0 trace is not active.
          <br />0b1 trace is active.
        </comment>
      </bits>
      <bits access="rw" name="stopclock" pos="2" rst="0x00">
        <comment>
          level to drive on stopclock.
          <br />0b0 drive 0 on stopclock.
          <br />0b1 drive 1 on stopclock.
        </comment>
      </bits>
      <bits access="rw" name="cttrigout" pos="1:0" rst="0x00">
        <comment>
          value to drive on cttrigout[1:0].
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="altnextstate">
      <comment>alt next state registers</comment>
      <bits access="rw" name="altnextstate" pos="NUM_TRIG_STATES-1:0" rst="-">
        <comment>
          selects the next state to move to after the conditional trigger condition has been
          met in the current state.
          <br />0x0 do not change state. this is the final trigger state.
          <br />0x1 selects trigger state 0.
          <br />0x2 selects trigger state 1.
          <br />0x4 selects trigger state 2.
          <br />0x8 selects trigger state 3.
          <br />0x10 selects trigger state 4, when num_trig_states=5.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="altaction">
      <comment>alt action registers</comment>
      <bits access="rw" name="elaoutput" pos="7:4" rst="0x00">
        <comment>
          value to drive on elaoutput[3:0].
        </comment>
      </bits>
      <bits access="rw" name="trace" pos="3" rst="0x00">
        <comment>
          trace active.
          <br />0b0 trace is not active.
          <br />0b1 trace is active.
        </comment>
      </bits>
      <bits access="rw" name="stopclock" pos="2" rst="0x00">
        <comment>
          level to drive on stopclock.
          <br />0b0 drive 0 on stopclock.
          <br />0b1 drive 1 on stopclock.
        </comment>
      </bits>
      <bits access="rw" name="cttrigout" pos="1:0" rst="0x00">
        <comment>
          value to drive on cttrigout[1:0].
        </comment>
      </bits>
    </reg>
    <hole size="64" />
    <reg protect="rw" name="countcomp">
      <comment>counter compare registers</comment>
      <bits access="rw" name="countcomp" pos="31:0" rst="-">
        <comment>
          value that, when reached in the associated up-counter for this trigger state, causes a trigger counter
          comparison match to occur.
        </comment>
      </bits>
    </reg>
    <hole size="96" />
    <reg protect="rw" name="extmask">
      <comment>external mask registers</comment>
      <bits access="rw" name="exttrig" pos="7:2" rst="-">
        <comment>
          mask exttrig[5:0] signals. each signal is masked by clearing the appropriate bit.
          <br />0b0 external trigger input signal is masked and is not used in comparisons.
          <br />0b1 external trigger input signal is not masked.
        </comment>
      </bits>
      <bits access="rw" name="cttrigin" pos="1:0" rst="-">
        <comment>
          mask cttrigin[1:0] signals. each signal is masked by clearing the appropriate bit.
          <br />0b0 external trigger input signal is masked and is not used in comparisons.
          <br />0b1 external trigger input signal is not masked.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="extcomp">
      <comment>external compare registers</comment>
      <bits access="rw" name="exttrig" pos="7:2" rst="-">
        <comment>
          compare value for exttrig[5:0] signals.
        </comment>
      </bits>
      <bits access="rw" name="cttrigin" pos="1:0" rst="-">
        <comment>
          compare value for cttrigin[1:0] signals.
        </comment>
      </bits>
    </reg>
    <hole size="64" />
    <reg count="4" protect="rw" name="sigmask">
      <comment>signal mask registers</comment>
      <bits access="rw" name="sigmask" pos="31:0" rst="-">
        <comment>
          mask bits from sigcomp[31:0].
          <br />mask bits from sigcomp[63:32].
          <br />mask bits from sigcomp[95:64]. these bits are only used if grp_width = 128 or 256.
          <br />mask bits from sigcomp[127:96]. these bits are only used if grp_width = 128 or 256.
        </comment>
      </bits>
    </reg>
    <hole size="384" />
    <reg count="4" protect="rw" name="sigcomp">
      <comment>signal compare registers</comment>
      <bits access="rw" name="sigcomp" pos="31:0" rst="-">
        <comment>
          compare value for signal group signals[31:0].
          <br />compare value for signal group signals[63:32].
          <br />compare value for signal group signals[95:64]. these bits are only used if grp_width = 128 or 256.
          <br />compare value for signal group signals[127:96]. these bits are only used if grp_width = 128 or 256.
        </comment>
      </bits>
    </reg>
    <hole size="896" />
  </struct>
  <hole size="20288" />
  <reg protect="wo" name="ittrigout">
    <comment>integration mode action trigger output register</comment>
    <bits access="wo" name="elaoutput" pos="7:4" rst="0x00">
      <comment>
        value to drive on elaoutput[3:0] when itctlr.ime = 1.
      </comment>
    </bits>
    <bits access="wo" name="reserved" pos="3" rst="0x00">
      <comment>
        -
      </comment>
    </bits>
    <bits access="wo" name="stopclock" pos="2" rst="0x00">
      <comment>
        level to drive on stopclock when itctlr.ime = 1.
        <br />0b0 drive 0 on stopclock.
        <br />0b1 drive 1 on stopclock.
      </comment>
    </bits>
    <bits access="wo" name="cttrigout" pos="1:0" rst="0x00">
      <comment>
        value to drive on cttrigout[1:0] when itctlr.ime = 1.
      </comment>
    </bits>
  </reg>
  <hole size="96" />
  <reg protect="ro" name="ittrigin">
    <comment>integration mode external trigger input register</comment>
    <bits access="ro" name="exttrig" pos="7:2" rst="-">
      <comment>
        captures the value on exttrig[5:0] when itctlr.ime = 1.
      </comment>
    </bits>
    <bits access="ro" name="cttrigin" pos="1:0" rst="-">
      <comment>
        captures the value on cttrigin[1:0] when itctlr.ime = 1.
      </comment>
    </bits>
  </reg>
  <hole size="32" />
  <reg protect="rw" name="itctrl">
    <comment>integration mode control register</comment>
    <bits access="rw" name="ime" pos="0" rst="0x0">
      <comment>
        integration mode enable.
        <br />0b0 integration mode disabled. the ela-500 operates normally.
        <br />0b1 integration mode enabled when ctrl.run = 0.
      </comment>
    </bits>
  </reg>
  <hole size="1376" />
  <reg protect="wo" name="lar">
    <comment>lock access register</comment>
    <bits access="wo" name="lar" pos="31:0" rst="-">
      <comment>
        permits writes to the other ela-500 registers when the access code 0xc5acce55 is written. writing any other value
        prevents access to the other ela-500 registers.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="lsr">
    <comment>lock status register</comment>
    <bits access="ro" name="lsr" pos="2:0" rst="0x00">
      <comment>
        returns the status of the lock access control.
        <br />0b001 write access permitted.
        <br />0b011 write access not permitted.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="authstatus">
    <comment>authentication status register</comment>
    <bits access="ro" name="snid" pos="7:6" rst="-">
      <comment>
        secure, non-invasive debug.
        <br />0b10 debug disabled.
        <br />0b11 debug enabled.
      </comment>
    </bits>
    <bits access="ro" name="sid" pos="5:4" rst="-">
      <comment>
        secure, invasive debug.
        <br />0b10 debug disabled.
        <br />0b11 debug enabled.
      </comment>
    </bits>
    <bits access="ro" name="nsnid" pos="3:2" rst="-">
      <comment>
        non-secure, non-invasive debug.
        <br />0b10 debug disabled.
        <br />0b11 debug enabled.
      </comment>
    </bits>
    <bits access="ro" name="nsid" pos="1:0" rst="-">
      <comment>
        non-secure, invasive debug.
        <br />0b10 debug disabled.
        <br />0b11 debug enabled.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="devarch">
    <comment>device architecture register</comment>
    <bits access="ro" name="architect" pos="31:21" rst="0x23b">
      <comment>
        the architect of the device.
        <br />0x23b arm.
      </comment>
    </bits>
    <bits access="ro" name="present" pos="20" rst="0x1">
      <comment>
        indicates that the register is present.
        <br />1 register present.
      </comment>
    </bits>
    <bits access="ro" name="revision" pos="19:16" rst="0x0">
      <comment>
        architecture revision.
        <br />0 first revision.
      </comment>
    </bits>
    <bits access="ro" name="archid" pos="15:0" rst="0x0a75">
      <comment>
        the architecture of the device.
        <br />0x0a75 coresight ela.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="devid2">
    <comment>device configuration register 2</comment>
    <bits access="ro" name="reserved" pos="31:20" rst="-d">
      <comment>
        -
      </comment>
    </bits>
    <bits access="ro" name="trigin_edge" pos="19:16" rst="-d">
      <comment>
        0: level detect of cttrigin and exttrig.
        <br />1: single edge detect of cttrigin and exttrig.
      </comment>
    </bits>
    <bits access="ro" name="comp_width" pos="15:8" rst="-d">
      <comment>
        indicates the comparator width.
        0: comparator width = grp_width.
        <br />>0: comparator width = (comp_width + 1) x 8.
        <br />for example, if comp_width = 15, then comparator width = 256.
      </comment>
    </bits>
    <bits access="ro" name="altts" pos="7:0" rst="-d">
      <comment>
        0x00 num_trig_states=4. trigger state 4 is not implemented.
        <br />0x10 num_trig_states=5. trigger state 4 is implemented and can be used for independent trace.
        <br />all other encodings are reserved and read as 0x00.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="devid1">
    <comment>device configuration register 1</comment>
    <bits access="ro" name="countwidth" pos="31:24" rst="-d">
      <comment>
        counter width in bits. fixed at 32.
      </comment>
    </bits>
    <bits access="ro" name="numtrigstates" pos="23:16" rst="-d">
      <comment>
        number of trigger states. four or five.
      </comment>
    </bits>
    <bits access="ro" name="siggrpwidth" pos="15:8" rst="-d">
      <comment>
        signal group width. the field value is (signal group width/8) - 1.
        <br />for example, 7 if grp_width = 64, 15 if grp_width = 128, and 31 if grp_width = 256.
      </comment>
    </bits>
    <bits access="ro" name="numsiggrps" pos="7:0" rst="-d">
      <comment>
        number of signal groups. fixed at 12.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="devid">
    <comment>device configuration register</comment>
    <bits access="ro" name="reserved" pos="31:29" rst="-d">
      <comment>
      </comment>
    </bits>
    <bits access="ro" name="scrambler" pos="28:25" rst="-d">
      <comment>
        0: trace read data scrambler not present.
        <br />1: trace read data scrambler present.
      </comment>
    </bits>
    <bits access="ro" name="id_capture_size" pos="24:20" rst="-d">
      <comment>
        2-30 bits when cond_trig = 1, or 0 otherwise.
      </comment>
    </bits>
    <bits access="ro" name="cond_trig" pos="19:16" rst="-d">
      <comment>
        shows the value of the cond_trig parameter.
        <br />1, when cond_trig = 1, or 0 otherwise.
      </comment>
    </bits>
    <bits access="ro" name="sram_addr_size" pos="15:8" rst="-d">
      <comment>
        sram address width in bits.
      </comment>
    </bits>
    <bits access="ro" name="traceformat" pos="7:4" rst="-d">
      <comment>
        trace implementation:
        <br />1 fixed at 1. indicates trace header format revision 1.
      </comment>
    </bits>
    <bits access="ro" name="tracetype" pos="3:0" rst="-d">
      <comment>
        atb trace:
        <br />0 atb trace not implemented.
        <br />1 atb trace is implemented.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="devtype">
    <comment>device type identifier register</comment>
    <bits access="ro" name="devtype" pos="7:0" rst="0x75">
      <comment>
        0x75.
        <br />sub type = 0x7.
        <br />major type = 0x5.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr4">
    <comment>peripheral id4 register</comment>
    <bits access="ro" name="size" pos="7:4" rst="0x0">
      <comment>
        0x0. one 4kb count.
      </comment>
    </bits>
    <bits access="ro" name="des_2" pos="3:0" rst="0x4">
      <comment>
        0x4. jep continuation code for arm.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr5">
    <comment>peripheral id5 register</comment>
    <bits access="ro" name="pidr5" pos="7:0" rst="0x00">
      <comment>
        0x00. reserved.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr6">
    <comment>peripheral id6 register</comment>
    <bits access="ro" name="pidr6" pos="7:0" rst="0x00">
      <comment>
        0x00. reserved.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr7">
    <comment>peripheral id7 register</comment>
    <bits access="ro" name="pidr7" pos="7:0" rst="0x00">
      <comment>
        0x00. reserved.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr0">
    <comment>peripheral id0 register</comment>
    <bits access="ro" name="part_0" pos="7:0" rst="0xb8">
      <comment>
        0xb8. bits[7:0] of part number 0x9b8.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr1">
    <comment>peripheral id1 register</comment>
    <bits access="ro" name="des_0" pos="7:4" rst="0xb">
      <comment>
        0xb. bits[3:0] of jep106 identification code for arm 0x3b.
      </comment>
    </bits>
    <bits access="ro" name="part_1" pos="3:0" rst="0x9">
      <comment>
        0x9. bits[11:8] of part number 0x9b8.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr2">
    <comment>peripheral id2 register</comment>
    <bits access="ro" name="revision" pos="7:4" rst="0x2">
      <comment>
        0x2. revision number. indicates revision r2p0.
      </comment>
    </bits>
    <bits access="ro" name="jedec" pos="3" rst="0x1">
      <comment>
        0b1. fixed at 0b1.
      </comment>
    </bits>
    <bits access="ro" name="des_1" pos="2:0" rst="0x3">
      <comment>
        0b011. bits[6:4] of jep106 identification code for arm 0x3b.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="pidr3">
    <comment>peripheral id3 register</comment>
    <bits access="ro" name="revand" pos="7:4" rst="0x00">
      <comment>
        0x0. revand.
      </comment>
    </bits>
    <bits access="ro" name="cmod" pos="3:0" rst="0x00">
      <comment>
        0x0. indicates whether the customer has modified the behavior of the component. in most cases, this field is
        0b0000. you can change this value when you make authorized modifications to this component.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="cidr0">
    <comment>component id0 register</comment>
    <bits access="ro" name="prmbl_0" pos="7:0" rst="0x0d">
      <comment>
        0x0d. preamble.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="cidr1">
    <comment>component id1 register</comment>
    <bits access="ro" name="class" pos="7:4" rst="0x9">
      <comment>
        0x9. indicates a coresight component.
      </comment>
    </bits>
    <bits access="ro" name="prmbl_1" pos="3:0" rst="0x0">
      <comment>
        0x0. preamble.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="cidr2">
    <comment>component id2 register</comment>
    <bits access="ro" name="prmbl_2" pos="7:0" rst="0x05">
      <comment>
        0x05. preamble.
      </comment>
    </bits>
  </reg>
  <reg protect="ro" name="cidr3">
    <comment>component id3 register</comment>
    <bits access="ro" name="prmbl_3" pos="7:0" rst="0xb1">
      <comment>
        0xb1. preamble.
      </comment>
    </bits>
  </reg>

</module>

</archive>


<archive relative = "excor.xml">

<include file="globals.xml"/>

<module name="excor" category="Baseband">

 <var name="EXCOR_IDLE" value="0" />
 <var name="EXCOR_BMMLZF" value="1" />
 <var name="EXCOR_COMPMATRIMUL" value="2" />
 <var name="EXCOR_COMPCONV" value="3" />
 <var name="EXCOR_COMPPOW" value="4" />
 <var name="EXCOR_DEROTATE" value="5" />
 <var name="EXCOR_DCCOMP" value="6" />
 <var name="EXCOR_SRECPSK8" value="7" />
 <var name="EXCOR_FCCH" value="8" />
 <var name="EXCOR_IR_COMB" value="9" />
 <var name="EXCOR_IQ_SHIFT" value="10" />
 <var name="EXCOR_STATUS_MASK" value="1" />
 <var name="EXCOR_FASTMATRIMUL" value="11" />
 <var name="EXCOR_FASTCONV" value="12" />
 <var name="EXCOR_2XTO1X" value="19" />
 <var name="EXCOR_M1" value="20" />
 <var name="EXCOR_M2" value="21" />
 <var name="EXCOR_Z" value="22" />
 <var name="EXCOR_Y" value="23" />
 <var name="EXCOR_DET" value="24" />
 
  
 
  <reg name="ctrl" protect="rw">
    <bits access="rw" name="cmd" pos="7:0" rst="0x0">
      <comment>Control setting. comand type. </comment>
    </bits>

    <bits access="rw" name="nb_iloop" pos="15:8" rst="0x0">
      <comment>Control setting. Number of internal loop iteration.
      </comment>
    </bits>

    <bits access="rw" name="nb_oloop" pos="25:16" rst="0x0">
      <comment>Control setting. Number of nb_symbol.
      </comment>
    </bits>

    <bits access="rw" name="shift_bit" pos="30:26" rst="0x0">
      <comment>Control setting. Number of shift bits.
      </comment>
    </bits>
  </reg>

 <reg name="addr0" protect="rw">
    <bits access="rw" name="addr0" pos="14:0" rst="0x0">
        <comment>address register 0. </comment>
    </bits>

  </reg>
  
  <reg name="addr1" protect="rw">
    <bits access="rw" name="addr1" pos="14:0" rst="0x0">
        <comment>address register 1. </comment>
    </bits>
  </reg>
  
  <reg name="addr2" protect="rw">
    <bits access="rw" name="addr2" pos="14:0" rst="0x0">
        <comment>address register 2. </comment>
    </bits>
  </reg>
  
<reg name="addr3" protect="rw">
    <bits access="rw" name="addr3" pos="31:0" rst="0x0">
        <comment>address register 3. </comment>
    </bits>
  </reg>
  
<reg name="addr4" protect="rw">
    <bits access="rw" name="addr4" pos="31:0" rst="0x0">
        <comment>address register 4. </comment>
    </bits>
  </reg>  
  
<reg name="addr5" protect="rw">
    <bits access="rw" name="addr5" pos="31:0" rst="0x0">
        <comment>address register 5. </comment>
    </bits>
  </reg>  
  
 <reg name="data0" protect="rw">
    <bits access="rw" name="data0" pos="31:0" rst="0x0">
        <comment>data register 0. </comment>
    </bits>
  </reg>  
  
 <reg name="data1" protect="rw">
    <bits access="rw" name="data1" pos="31:0" rst="0x0">
        <comment>data register 1. </comment>
    </bits>
  </reg>
  
 <reg name="data2" protect="rw">
    <bits access="rw" name="data2" pos="31:0" rst="0x0">
        <comment>data register 2. </comment>
    </bits>
  </reg>  
    
 <reg name="data3" protect="rw">
    <bits access="rw" name="data3" pos="31:0" rst="0x0">
        <comment>data register 3. </comment>
    </bits>
  </reg>  
  
 <reg name="data4" protect="rw">
    <bits access="rw" name="ircom_psidx0" pos="1:0" rst="0x0">
      <comment>for ircombine idx0 </comment>
    </bits>
    <bits access="rw" name="ircom_psidx2" pos="5:4" rst="0x0">
      <comment>for ircombine idx1 </comment>
    </bits>
    <bits access="rw" name="ircom_psidx1" pos="18:8" rst="0x0">
      <comment>for ircombine idx2 </comment>
    </bits>
  </reg>    
  
 <reg name="data5" protect="rw">
    <bits access="rw" name="data5" pos="31:0" rst="0x0">
        <comment>data register 5. </comment>
    </bits>
  </reg>    
  
  
  <reg name="status" protect="rw">
    <bits access="rw" name="status" pos="7:0" rst="0x0">
        <comment>Status is set to 1 when an operation is finished. </comment>
    </bits>
  </reg>
  <reg name="ctrl_fast" protect="rw">
    <bits access="rw" name="loop_num_a" pos="2:0" rst="0x0">
      <comment>Control setting. Number of A row. </comment>
    </bits>

    <bits access="rw" name="loop_num_b" pos="6:4" rst="0x0">
      <comment>Control setting. Number of B column.
      </comment>
    </bits>

    <bits access="rw" name="loop_num_ab" pos="15:8" rst="0x0">
      <comment>Control setting. Number of  A column and B row.
      </comment>
    </bits>
    <bits access="rw" name="shift_bit_reg1" pos="20:16" rst="0x0">
      <comment>Control setting. Number of  shift bit after multiply.
      </comment>
    </bits>
  </reg>  
</module>

</archive>
<archive relative = "f8.xml">
<module name="cipher_f8" category="Baseband">
  
  <reg protect="rw" name="F8_CONF">
    <bits access="rw" name="F8_START" pos="0" rst="0">
      <comment>f8 start bit, 0: not start or finished ,  1: start</comment>
    </bits>
    
    <bits access="rw" name="F8_IRQ_EN" pos="1" rst="0">
      <comment> when all groups done , 0: no gen int 1: gen int </comment>
    </bits>
    
    <bits access="rw" name="F8_AR_SEL" pos="3:2" rst="0x0">
        <comment>function sel 00: only move data , no encrypt 
                              01:      move data , AES encrypt
                              10:      move data , snow3G encrypt
                              11:      move data , zuc encrypt
        </comment>
    </bits>
  </reg>

  <reg protect="rw" name="F8_GROUP_ADDR">
    <bits access="rw" name="GROUP_ADDR" pos="31:0" rst="0x0">
      <comment>group start address</comment>
    </bits>
  </reg>

  <reg protect="rw" name="F8_GROUP_CNT">
    <bits access="rw" name="GROUP_ADDR" pos="31:0" rst="0x0">
      <comment>total group cnt</comment>
    </bits>
  </reg>

  <reg protect="rw" name="F8_STATUS">
    <bits access="rw" name="F8_STAT" pos="0" rst="0">
      <comment>0: not started or no finished  1: finished</comment>
    </bits>

    <bits access="rw" name="F9_STAT" pos="1" rst="0">
      <comment>0: not started or no finished  1: finished</comment>
    </bits>
  </reg>

  <reg protect="rw" name="F9_CONF">
    <bits access="rw" name="F9_START" pos="0" rst="0">
      <comment>f9 start bit, 0: not start or finished ,  1: start</comment>
    </bits>
    
    <bits access="rw" name="F9_IRQ_EN" pos="1" rst="0">
      <comment> when all groups done , 0: no gen int 1: gen int </comment>
    </bits>
    
    <bits access="rw" name="F9_AR_SEL" pos="3:2" rst="0x0">
        <comment>function sel 00:  AES encrypt 
                              01:  AES encrypt
                              10:  snow3G encrypt
                              11:  zuc encrypt
        </comment>
    </bits>
  </reg>

  <reg protect="rw" name="F9_GROUP_ADDR">
    <bits access="rw" name="F9_ADDR" pos="31:0" rst="0x0">
      <comment>group start address</comment>
    </bits>
  </reg>

  <reg protect="r" name="F9_RESULT">
    <bits access="rw" name="F9_MAC" pos="31:0" rst="0x0">
      <comment>f9 result</comment>
    </bits>
  </reg>

</module>
</archive>

<archive relative = "gouda.xml">

<include file='globals.xml'/>

<module name="gouda" category="System">
  <var name="GD_MAX_OUT_WIDTH" value="640" />
      <comment>Maximum output width in pixels</comment>
  <var name="GD_NB_BITS_LCDPOS" value="11" />
      <comment>Number of bits coding position in virtual screen</comment>
  <var name="GD_FP_FRAC_SIZE" value="8" />
      <comment>Number of bits of fractional part of internal fixed point values</comment>
  <var name="GD_FIXEDPOINT_SIZE" value="3+GD_FP_FRAC_SIZE" />
      <comment>Number of bits of internal fixed point values</comment>
  <var name="GD_NB_BITS_STRIDE" value="13" />
      <comment>Number of bits for stride storage</comment>

  <var name="GD_MAX_SLCD_READ_LEN" value="4" />
  <var name="GD_MAX_SLCD_CLK_DIVIDER" value="255" />

  
  <reg protect="rw" name="gd_command">
    <bits access="rw" name="start" pos="0" rst="0x0">
      <comment>Starts the image transfer. Autoreset</comment>
    </bits>
  </reg>

  <reg protect="r" name="gd_status">
    <bits access="r" name="ia_busy" pos="0" rst="0x0">
      <comment>High while image accelerator is busy</comment>
    </bits>
    <bits access="r" name="lcd_busy" pos="4" rst="0x0">
      <comment>High while LCD controller is busy</comment>
    </bits>
  </reg>

  <reg protect="rc" name="gd_eof_irq">
    <bits access="rc" name="eof_cause" pos="0" rst="0x0">
        <comment>High when End Of Frame IRQ has been generated.
            <br />To clear it, write 1 in this bit or in eof_status.
        </comment>
    </bits>
    <bits access="rc" name="eof_status" pos="16" rst="0x0">
      <comment>Unmasked version of eof_cause.
            <br />To clear it, write 1 in this bit or in eof_status.
        </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_eof_irq_mask">
    <bits access="rw" name="eof_mask" pos="0" rst="0x0">
        <comment>EOF interrupt generation mask:
            <br />0: EOF IRQ disabled
            <br />1: EOF IRQ enabled
        </comment>
    </bits>
  </reg>

  
  <reg protect="rw" name="gd_roi_tl_ppos">
    <bits access="rw" name="x0" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
        <comment>LCD Region Of Interest Top-Left pixel x-axis </comment>
    </bits>
    <bits access="rw" name="y0" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
        <comment>LCD Region Of Interest Top-Left pixel y-axis </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_roi_br_ppos">
    <bits access="rw" name="x1" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
        <comment>LCD Region Of Interest Bottom-Right pixel x-axis </comment>
    </bits>
    <bits access="rw" name="y1" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
        <comment>LCD Region Of Interest Bottom-Right pixel y-axis </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_roi_bg_color">
    <bits access="rw" name="b" pos="4:0" rst="0x0">
        <comment>Blue component of the ROI background color</comment>
    </bits>
    <bits access="rw" name="g" pos="10:5" rst="0x0">
        <comment>Green component of the ROI background color</comment>
    </bits>
    <bits access="rw" name="r" pos="15:11" rst="0x0">
        <comment>Red component of the ROI background color</comment>
    </bits>
  </reg>

  
  <reg protect="rw" name="gd_vl_input_fmt">
    <bits access="rw" name="format" pos="1:0" rst="0x0">
        <comment>Input image format
            <br />00b: RGB565 pixel packed
            <br />01b: YUV4:2:2 pixel packed (UYVY)
            <br />10b: YUV4:2:2 pixel packed (YUYV)
            <br />11b: YUV4:2:0 planar (IYUV)
        </comment>
    </bits>
    <bits access="rw" name="stride" pos="GD_NB_BITS_STRIDE+1:2" rst="0x0">
        <comment>Image stride in bytes (of Y component for planar formats).
            <br />This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size).
        </comment>
    </bits>
    <bits access="rw" name="active" pos="31" rst="0x0">
        <comment>Defines Layer's activity:
            <br />0: Layer disabled
            <br />1: Layer active
        </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_tl_ppos">
    <bits access="rw" name="x0" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
        <comment>Video Layer (layer 0) Top-Left pixel x-axis position</comment>
    </bits>
    <bits access="rw" name="y0" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
        <comment>Video Layer (layer 0) Top-Left pixel y-axis position</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_br_ppos">
    <bits access="rw" name="x1" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
        <comment>Video Layer (layer 0) Bottom-Right pixel x-axis position</comment>
    </bits>
    <bits access="rw" name="y1" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
        <comment>Video Layer (layer 0) Bottom-Right pixel y-axis position</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_extents">
    <bits access="rw" name="max_line" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
        <comment>Number of lines of source image (idem gd_vl_br_ppos.y1 when
                 vertical scaling factor is one).
        </comment>
    </bits>
    <bits access="rw" name="max_col" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
        <comment>Number of columns of source image (idem gd_vl_br_ppos.x1 when
                 vertical scaling factor is one).
        </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_blend_opt">
    <bits access="rw" name="chroma key b" pos="4:0" rst="0x0">
        <comment>Blue component of the Chroma Key</comment>
        <options><mask/></options>
    </bits>
    <bits access="rw" name="chroma key g" pos="10:5" rst="0x0">
        <comment>Green component of the Chroma Key</comment>
        <options><mask/></options>
    </bits>
    <bits access="rw" name="chroma key r" pos="15:11" rst="0x0">
        <comment>Red component of the Chroma Key</comment>
        <options><mask/></options>
    </bits>
    <bitgroup name="chroma key color">
        <entry ref="chroma key b"/>
        <entry ref="chroma key g"/>
        <entry ref="chroma key r"/>
    </bitgroup>
    <bits access="rw" name="chroma key enable" pos="16" rst="0x0">
        <comment>Enables the Chroma Keying</comment>
        <options><mask/></options>
    </bits>
    <bits access="rw" name="chroma key mask" pos="19:17" rst="0x0">
        <comment>Allows a range of color for the Chroma Keying:
            <br />000b: exact color match
            <br />001b: disregard 1 LSBit of each color component for matching
            <br />011b: disregard 2 LSBit of each color component for matching
            <br />111b: disregard 3 LSBit of each color component for matching
        </comment>
        <options><mask/></options>
    </bits>
    <bits access="rw" name="alpha" pos="27:20" rst="0x0">
        <comment>Layer Alpha blending coefficient</comment>
        <options><mask/></options>
    </bits>
    <bits access="rw" name="rotation" pos="29:28" rst="0x0">
        <comment>Layer rotation selection
            <br />00b: No rotation
            <br />01b: 90  degrees rotation (clockwise)
            <br />10b: reserved
            <br />11b: reserved
        </comment>
        <options><mask/></options>
    </bits>
    <bits access="rw" name="depth" pos="31:30" rst="0x0">
        <comment>Layer depth
            <br />00b: Video layer behind all Overlay layers
            <br />01b: Video layer between Overlay layers 1 and 0
            <br />10b: Video layer between Overlay layers 2 and 1
            <br />11b: Video layer on top of all Overlay layers
        </comment>
        <options><mask/></options>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_y_src">
    <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
        <comment>Dword-aligned address of the Y component (or RGB) of the source image</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_u_src">
    <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
        <comment>Dword-aligned address of the U component of the source image</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_v_src">
    <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
        <comment>Dword-aligned address of the V component of the source image</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_vl_resc_ratio">
    <bits access="rw" name="xPitch" pos="GD_FIXEDPOINT_SIZE-1:0" rst="0x0">
        <comment>Video layer rescaling ratio upon x-axis. This is a 2.8 fixed point number representing the input/output width ratio.</comment>
    </bits>
    <bits access="rw" name="yPitch" pos="GD_FIXEDPOINT_SIZE+15:16" rst="0x0">
        <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
    </bits>
    <bits access="w" name="pre_fetch_en" pos="29" rst="0x0">
        <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
    </bits>
    <bits access="rw" name="iy_dctenable" pos="30" rst="0x0">
        <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
    </bits>
    <bits access="rw" name="ypitch_scale_enable" pos="31" rst="0x0">
        <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
    </bits>
  </reg>

  
  <struct count="3" name="Overlay_Layer">
    <comment>
        The Overlay layers have a fixed depth relative to their index. Overlay layer 0 is the first to be drawn (thus the deepest), overlay layer 2 is the last to be drawn.
    </comment>
  <reg protect="rw" name="gd_ol_input_fmt">
    <bits access="rw" name="format" pos="1:0" rst="0x0">
        <comment>Input image format
            <br />0: RGB565 pixel packed
            <br />1: ARGB8888 pixel packed
            <br />others: reserved
        </comment>
    </bits>
    <bits access="rw" name="stride" pos="GD_NB_BITS_STRIDE+1:2" rst="0x0">
        <comment>Image stride in 16-bits word.
            <br />This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size).
        </comment>
    </bits>
    <bits access="rw" name="prefetch" pos="18" rst="0x1">
        <comment>Image stride in 16-bits word.
            <br />This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size).
        </comment>
    </bits>
      
    <bits access="rw" name="active" pos="31" rst="0x0">
        <comment>Defines Layer's activity:
            <br />0: Layer disabled
            <br />1: Layer active
        </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_ol_tl_ppos">
    <bits access="rw" name="x0" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
        <comment>Overlay Layer (layer X+1) Top-Left pixel x-axis position</comment>
    </bits>
    <bits access="rw" name="y0" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
        <comment>Overlay Layer (layer X+1) Top-Left pixel y-axis position</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_ol_br_ppos">
    <bits access="rw" name="x1" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
        <comment>Overlay Layer (layer X+1) Bottom-Right pixel x-axis position</comment>
    </bits>
    <bits access="rw" name="y1" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
        <comment>Overlay Layer (layer X+1) Bottom-Right pixel y-axis position</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_ol_blend_opt">
    <bits access="rw" name="chroma key b" pos="4:0" rst="0x0">
        <comment>Blue component of the Chroma Key</comment>
    </bits>
    <bits access="rw" name="chroma key g" pos="10:5" rst="0x0">
        <comment>Green component of the Chroma Key</comment>
    </bits>
    <bits access="rw" name="chroma key r" pos="15:11" rst="0x0">
        <comment>Red component of the Chroma Key</comment>
    </bits>
    <bitgroup name="chroma key color">
        <entry ref="chroma key b"/>
        <entry ref="chroma key g"/>
        <entry ref="chroma key r"/>
    </bitgroup>
    <bits access="rw" name="chroma key enable" pos="16" rst="0x0">
        <comment>Enables the Chroma Keying</comment>
    </bits>
    <bits access="rw" name="chroma key mask" pos="19:17" rst="0x0">
        <comment>Allows a range of color for the Chroma Keying:
            <br />000b: exact color match
            <br />001b: disregard 1 LSBit of each color component for matching
            <br />011b: disregard 2 LSBit of each color component for matching
            <br />111b: disregard 3 LSBit of each color component for matching
        </comment>
    </bits>
    <bits access="rw" name="alpha" pos="27:20" rst="0x0">
        <comment>Layer Alpha blending coefficient</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_ol_rgb_src">
    <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
        <comment>Dword-aligned address of the source image</comment>
    </bits>
  </reg>
  </struct>

  
  <reg protect="rw" name="gd_lcd_ctrl">
    <bits access="rw" name="Destination" pos="1:0" rst="0x0">
        <comment>Destination Selection
        </comment>
        <options>
            <option name="LCD CS 0" value ="0"></option>
            <option name="LCD CS 1" value ="1"></option>
            <option name="Memory LCD type" value ="2"></option>
            <option name="Memory RAM" value ="3"></option>
        </options>
    </bits>
    <bits access="rw" name="Output Format" pos="6:4" rst="0x0">
       <comment>Output format
            <br />000b:  8-bit - RGB3:3:2 - 1cycle/1pixel - RRRGGGBB
            <br />001b:  8-bit - RGB4:4:4 - 3cycle/2pixel - RRRRGGGG/BBBBRRRR/GGGGBBBB
            <br />010b:  8-bit - RGB5:6:5 - 2cycle/1pixel - RRRRRGGG/GGGBBBBB
            <br />011b:  reserved
            <br />100b: 16-bit - RGB3:3:2 - 1cycle/2pixel - RRRGGGBBRRRGGGBB
            <br />101b: 16-bit - RGB4:4:4 - 1cycle/1pixel - XXXXRRRRGGGGBBBB
            <br />110b: 16-bit - RGB5:6:5 - 1cycle/1pixel - RRRRRGGGGGGBBBBB
            <br />111b:  reserved
            <br />
            <br /> The MSB select also the AHB access size (8-bit or 16-bit) when Memory destination is selected.
            <br /> Must set to RGB565 when RAM type destination selected
        </comment>
        <options>
            <option name="8-bit;RGB332" value ="0"></option>
            <option name="8-bit;RGB444" value ="1"></option>
            <option name="8-bit;RGB565" value ="2"></option>
            <option name="16-bit;RGB332" value ="4"></option>
            <option name="16-bit;RGB444" value ="5"></option>
            <option name="16-bit;RGB565" value ="6"></option>
        </options>
      </bits>
    <bits access="rw" name="high byte" pos="7" rst="0x0">
    </bits>
    <bits access="rw" name="CS0 Polarity" pos="8" rst="0x0">
       <comment>Change Polarity of CS0 signal
            <br /> 0: no change
            <br /> 1: Inverted
        </comment>
    </bits>
    <bits access="rw" name="CS1 Polarity" pos="9" rst="0x0">
       <comment>Change Polarity of CS1 signal
            <br /> 0: no change
            <br /> 1: Inverted
        </comment>
    </bits>
    <bits access="rw" name="RS Polarity" pos="10" rst="0x0">
       <comment>Change Polarity of RS signal
            <br /> 0: no change
            <br /> 1: Inverted
        </comment>
    </bits>
    <bits access="rw" name="WR Polarity" pos="11" rst="0x0">
       <comment>Change Polarity of WR signal
            <br /> 0: no change
            <br /> 1: Inverted
        </comment>
    </bits>
    <bits access="rw" name="RD Polarity" pos="12" rst="0x0">
       <comment>Change Polarity of RD signal
            <br /> 0: no change
            <br /> 1: Inverted
        </comment>
    </bits>

    <bits access="rw" name="Nb Command" pos="21:16" rst="0x0">
       <comment>Number of command to be send to the LCD command (up to 31)
        </comment>
    </bits>
    <bits access="w" name="Start command" pos="24" rst="0x0">
       <comment>Start command transfer only. Autoreset
       </comment>
    </bits>
    <bits access="rw" name="LCD Resetb" pos="25" rst="0x1">
       <comment>LCD reset signal. Low active
        </comment>
    </bits>
  </reg>
  <reg protect="rw" name="gd_lcd_timing">
        <comment>All value are in cycle number of system clock
        </comment>
    <bits access="rw" name="TAS" pos="2:0" rst="0x0">
        <comment>Address setup time (RS to WR, RS to RD)
        </comment>
    </bits>
    <bits access="rw" name="TAH" pos="6:4" rst="0x0">
        <comment>Adress hold time
        </comment>
    </bits>
    <bits access="rw" name="PWL" pos="13:8" rst="0x0">
        <comment>Pulse Width Low level, between 2 and 63.
        </comment>
    </bits>
    <bits access="rw" name="PWH" pos="21:16" rst="0x0">
        <comment>Pulse Width High level, between 2 and 63 (must be > (TAH+TAS) ).
        </comment>
    </bits>
  </reg>
  <reg protect="rw" name="gd_lcd_mem_address">
    <bits access="rw" name="addr_dst" pos="NB_BITS_ADDR-1:2" rst="all0">
        <comment>Address destination pointer when memory destination is selected.
                 <br />The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data.
        </comment>
    </bits>
  </reg>
  <reg protect="rw" name="gd_lcd_stride_offset">
    <bits access="rw" name="stride_offset" pos="9:0" rst="all0">
        <comment>Address offset (in Bytes) skipped at the end of each line when memory destination is selected.
                 <br />This 2D feature allows for in-memory image compositing. 
        </comment>
    </bits>
  </reg>
  <reg protect="rw" name="gd_lcd_single_access">
    <bits access="rw" name="lcd_data" pos="15:0" rst="all0">
        <comment>data to write or data readen (the readen data is ready when the lcd is not busy)
        </comment>
    </bits>
    <bits access="rw" name="type" pos="16" rst="0x0">
        <comment>Acesss type selection
            <br />0: Command
            <br />1: Data
        </comment>
    </bits>
    <bits access="w" name="start_write" pos="17" rst="0x0">
        <comment>Start a single write access. Autoreset
       </comment>
    </bits>
    <bits access="w" name="start_read" pos="18" rst="0x0">
        <comment>Start a single read access (only when LCD output selected). Autoreset.
       </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gd_spilcd_config">
    <bits access="rw" name="spi_lcd_select" pos="0" rst="0"> </bits>
    <bits access="rw" name="spi_device_id" pos="6:1" rst="all0">
        <options><mask/><shift/></options>
    </bits>
    <bits access="rw" name="spi_clk_divider" pos="14:7" rst="0xa"> 
        <options><mask/><shift/></options>
    </bits>
    <bits access="rw" name="spi_dummy_cycle" pos="17:15" rst="all0"> 
        <options><mask/><shift/></options>
    </bits>
    <bits access="rw" name="spi_line" pos="19:18" rst="all0"> 
          <comment>0:4 line mode 
                   1:3 line mode
                   2:command mode
                   3:3 line 2 lane mode tx
          </comment>
          <options>
              <mask/>
              <option name="4" value ="0"></option>
              <option name="3" value ="1"></option>
              <option name="4_Start_Byte" value ="2"></option>
              <option name="3_Two_Lane" value ="3"></option>
          </options>
    </bits>
    <bits access="rw" name="spi_rx_byte" pos="22:20" rst="all0">
          <options><mask/><shift/></options>
    </bits>
    <bits access="rw" name="spi_rw" pos="23" rst="0"> 
         <options>
              <option name="Write" value ="0"></option>
              <option name="Read" value ="1"></option>
          </options>
    </bits>
  </reg>
  <reg protect="r" name="gd_spilcd_rd">
    <bits access="r" name="spi_lcd_rd" pos="31:0" rst="all0">
        <comment>
        </comment>
    </bits>
  </reg>
  <reg name="gd_vl_fix_ratio" protect="rw">
      <bits name="reg_vl_only_sel" pos="19" access="rw" rst="0x0">
          <comment>
          </comment>
      </bits>
        <bits name="mirror" pos="18" access="rw" rst="0x0">
            <comment>Mirror enable.
            </comment>
        </bits>
        <bits name="l_yfixen" pos="17" access="rw" rst="0x0">
            <comment>.
            </comment>
        </bits>
        <bits name="l_xfixen" pos="16" access="rw" rst="0x0">
            <comment>.
            </comment>
        </bits>
        <bits name="l_yratio" pos="15:8" access="rw" rst="0x0">
            <comment>.
            </comment>
        </bits>
        <bits name="l_xratio" pos="7:0" access="rw" rst="0x0">
            <comment>.
            </comment>
        </bits>
    </reg>

    <hole size="(80-38-1)*32"/> 
   
   
    <reg name="TECON" protect="rw">
        <bits name="te_count2" pos="27:16" access="rw" rst="0x0">
            <comment>Count value to detect vsync pulse
            </comment>
        </bits>
        <bits name="te_mode" pos="2" access="rw" rst="0x0">
            <comment>0:vsync te only 1:vsync and hsync te
            </comment>
        </bits>
        <bits name="te_edge_sel" pos="1" access="rw" rst="0x0">
            <comment>Pol select
            </comment>
        </bits>
        <bits name="te_en" pos="0" access="rw" rst="0x0">
            <comment>Te enable.
            </comment>
        </bits>
    </reg>
    <reg name="TECON2" protect="rw">
        <bits name="te_count1" pos="28:0" access="rw" rst="0x0">
            <comment>Te counter value
            </comment>
        </bits>
    </reg>

<hole size="(256-81-1)*32"/>

</module>




<module name="gouda_sram" category="System">
  <var name="GD_NB_WORKBUF_WORDS"  value="5856" />
  <var name="GD_NB_LCD_CMD_WORDS"  value="64" />
  <var name="GD_SRAM_SIZE"  value="(GD_NB_WORKBUF_WORDS+GD_NB_LCD_CMD_WORDS)*2" />
  <var name="GD_SRAM_ADDR_WIDTH"  value="13" />

    <memory name="sram_array" size="GD_SRAM_SIZE">
        <comment>Gouda internal Sram space
        </comment>
    </memory>
</module>

</archive>

<archive relative = "gpio.xml">

  
  

  
  <var name="IDX_GPIO_DCON" value="0" />
  <var name="IDX_GPO_CHG"   value="0" />
  <var name="NB_GPIO"       value="64" />
  <var name="NB_GPIO_INT"   value="64" />
  <var name="NB_GPO"        value="10" />

<module name="gpio" category="Periph">

  
  
  <reg protect="rw" name="gpio_oen_val_l">
    <bits access="rw" name="oen_val_l" pos="31:0" rst="0xffffffff" display="hex">
      <options>
        <option name="INPUT" value="1" />

        <option name="OUTPUT" value="0" />

        <default />
      </options>

      <comment>Set the direction of the GPIO n.<br />0 = output<br />1 =
      input</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_oen_set_out_l">
    <bits access="rc" name="oen_set_out_l" pos="31:0" rst="0xffffffff">
      <comment>'Write '1' sets the corresponding GPIO pin as output.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_oen_set_in_l">
    <bits access="rs" name="oen_set_in_l" pos="31:0" rst="0xffffffff" display="hex">
      <comment>'Write '1' sets the corresponding GPIO pin as input.</comment>
    </bits>
  </reg>

  

  <reg protect="rw" name="gpio_val_l">
    <bits access="rw" name="gpio_val_l" pos="31:0" rst="0xffffffff" display="hex">
      <comment>When write, update the output value. When read, get the input
      value. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_set_l">
    <bits access="rs" name="gpio_set_l" pos="31:0" rst="0xffffffff">
      <comment>Write '1' will set GPIO output value. When read, get the GPIO
      output value.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_clr_l">
    <bits access="rc" name="gpio_clr_l" pos="31:0" rst="0xffffffff">
      <comment>'Write '1' clears corresponding GPIO output value. When read, get the GPIO
      output value. </comment>
    </bits>
  </reg>


   <reg protect="rw" name="gpint_r_set_l">
     <bits access="rs" name="gpint_r_set_l" pos="31:0" rst="0">
       <comment>Write '1' will set GPIO interrupt mask for rising edge and
       level high. When read, get the GPIO interrupt mask for rising edge and
       level high. </comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_r_set_h">
     <bits access="rs" name="gpint_r_set_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>Write '1' will set GPIO interrupt mask for rising edge and
       level high. When read, get the GPIO interrupt mask for rising edge and
       level high. </comment>
     </bits>
   </reg>

  <reg protect="w" name="int_clr_l">
    <bits access="c" name="gpint_clr_l" pos="31:0" rst="0">
      <comment>'Write '1' will clear GPIO interrupt.</comment>
    </bits>
  </reg>

  <reg protect="r" name="int_status_l">
    <bits access="r" name="gpint_status_l" pos="31:0" rst="0">
      <comment>Each bit represents if there is a GPIO interrupt
      pending.</comment>
      <options>
        <default/>
        <mask/>
        <shift/>
      </options>
    </bits>
  </reg>

  <reg protect="rw" name="chg_ctrl">
    <bits access="rw" name="out_time" pos="3:0" rst="0xf" display="hex">
        <comment>time for which GPIO0 is set to output mode, after a start read
            DCON command is issued.<br />The output time = (OUT_TIME+1)*30.5us.
        </comment>
    </bits>

    <bits access="rw" name="wait_time" pos="9:4" rst="0x3f" display="hex">
        <comment>time for which GPIO0 should wait before reading DC_ON, after
            a start read DCON command is issued.<br />The wait time = (WAIT_TIME+1)*30.5us.
            <br/>NOTE: wait_time must be strictly greater than out_time;
        </comment>
    </bits>

    <bits access="rw" name="int_mode" pos="17:16" rst="0x3" display="hex">
        <comment>interruption mode of GPIO0 in mode DC_ON detection.<br />
        </comment>
            <options>
                <option name="L2H" value="0">
                    <comment>
                        "00" = send IRQ if last read DCON is '0' and now is '1'. 
                    </comment>
                </option>
                <option name="H2L" value="1">
                    <comment>
                        "01" = send IRQ if last read DCON is '1' and now is '0'.
                    </comment>
                </option>
                <option name="RR" value="3">
                    <comment>
                        "11" = send IRQ every time read is ready.
                    </comment>
                </option>
            </options>
    </bits>
  </reg>

  <reg protect="w" name="chg_cmd">
    <bits access="s" name="dcon_mode_set" pos="0" rst="0">
      <comment>Write '1' to set GPIO0 to charger DCON detect mode.</comment>
    </bits>
      
    <bits access="s" name="chg_mode_set" pos="4" rst="0">
      <comment>Write '1' to set GPO0 to charger watchdog mode.</comment>
    </bits>

    <bits access="c" name="dcon_mode_clr" pos="8" rst="0">
      <comment>Write '1' to clear charger DCON detect mode of GPIO0.</comment>
    </bits>

    <bits access="c" name="chg_mode_clr" pos="12" rst="0">
      <comment>Write '1' to clear the charger watchdog mode of GPO0.</comment>
    </bits>

    <bits access="s" name="chg_down" pos="24" rst="0">
      <comment>Write '1' to generate a pulse of '0' on GPO0 for 16 CLK_OSC cycles.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpo_set">
    <bits access="rs" name="gpo_set" pos="NB_GPO-1:0" rst="0x2aa" display="hex">
      <comment>'Write '1' will set GPO output value. When read, get the GPO
      output value.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpo_clr">
    <bits access="rc" name="gpo_clr" pos="NB_GPO-1:0" rst="0x2aa" display="hex">
      <comment>'Write '1' will clear GPO output value. When read, get the GPO
      output value.</comment>
    </bits>
  </reg>

  
  <reg protect="rw" name="gpio_oen_val_h">
    <bits access="rw" name="oen_val_h" pos="NB_GPIO-33:0" rst="0xffffffff" display="hex">
      <options>
        <option name="INPUT" value="1" />

        <option name="OUTPUT" value="0" />

        <default />
      </options>

      <comment>Set the direction of the GPIO n.<br />0 = output<br />1 =
      input</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_oen_set_out_h">
    <bits access="rc" name="oen_set_out_h" pos="NB_GPIO-33:0" rst="0xffffffff">
      <comment>'Write '1' sets the corresponding GPIO pin as output.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_oen_set_in_h">
    <bits access="rs" name="oen_set_in_h" pos="NB_GPIO-33:0" rst="0xffffffff" display="hex">
      <comment>'Write '1' sets the corresponding GPIO pin as input.</comment>
    </bits>
  </reg>

  

  <reg protect="rw" name="gpio_val_h">
    <bits access="rw" name="gpio_val_h" pos="NB_GPIO-33:0" rst="0xffffffff" display="hex">
      <comment>When write, update the output value. When read, get the input
      value. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_set_h">
    <bits access="rs" name="gpio_set_h" pos="NB_GPIO-33:0" rst="0xffffffff">
      <comment>Write '1' will set GPIO output value. When read, get the GPIO
      output value.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="gpio_clr_h">
    <bits access="rc" name="gpio_clr_h" pos="NB_GPIO-33:0" rst="0xffffffff">
      <comment>'Write '1' clears corresponding GPIO output value. When read, get the GPIO
      output value. </comment>
    </bits>
  </reg>

  
  
   <reg protect="rw" name="gpint_r_clr_l">
     <bits access="rs" name="gpint_r_clr_l" pos="31:0" rst="0">
       <comment>'Write '1' will clear GPIO interrupt mask for rising edge and
       level high.</comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_r_clr_h">
     <bits access="rs" name="gpint_r_clr_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>'Write '1' will clear GPIO interrupt mask for rising edge and
       level high.</comment>
     </bits>
   </reg>

   <reg protect="rw" name="gpint_f_set_l">
     <bits access="rs" name="gpint_f_set_l" pos="31:0" rst="0">
       <comment>Write '1' will set GPIO interrupt mask for rising edge and
       level high. When read, get the GPIO interrupt mask for rising edge and
       level high. </comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_f_set_h">
     <bits access="rs" name="gpint_f_set_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>Write '1' will set GPIO interrupt mask for falling edge and
       level low. When read, get the GPIO interrupt mask for falling edge and
       level low.</comment>
     </bits>
   </reg>

   <reg protect="rw" name="gpint_f_clr_l">
     <bits access="rs" name="gpint_f_clr_l" pos="31:0" rst="0">
       <comment>Write '1' will clear GPIO interrupt mask for falling edge and
       level low.</comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_f_clr_h">
     <bits access="rs" name="gpint_f_clr_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>Write '1' will clear GPIO interrupt mask for falling edge and
       level low.</comment>
     </bits>
   </reg>

   <reg protect="rw" name="gpint_dbn_en_set_l">
     <bits access="rs" name="dbn_en_set_l" pos="31:0" rst="0">
       <comment>Write '1' will enable debounce mechanism.</comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_dbn_en_set_h">
     <bits access="rs" name="dbn_en_set_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>Write '1' will enable debounce mechanism.</comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_dbn_en_clr_l">
     <bits access="rs" name="dbn_en_clr_l" pos="31:0" rst="0">
       <comment>Write '1' will disable debounce mechanism.</comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_dbn_en_clr_h">
     <bits access="rs" name="dbn_en_clr_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>Write '1' will disable debounce mechanism.</comment>
     </bits>
   </reg>

   <reg protect="rw" name="gpint_mode_set_l">
     <bits access="rs" name="gpint_mode_set_l" pos="31:0" rst="0">
       <comment>Write '1' will set interruption mode to level.</comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_mode_set_h">
     <bits access="rs" name="gpint_mode_set_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>Write '1' will set interruption mode to level.</comment>
     </bits>
   </reg>

   <reg protect="rw" name="gpint_mode_clr_l">
     <bits access="rs" name="gpint_mode_clr_l" pos="31:0" rst="0">
       <comment>Write '1' will set interruption mode to edge
       triggered.</comment>
     </bits>
   </reg>
   <reg protect="rw" name="gpint_mode_clr_h">
     <bits access="rs" name="gpint_mode_clr_h" pos="NB_GPIO_INT-33:0" rst="0">
       <comment>Write '1' will set interruption mode to edge
       triggered.</comment>
     </bits>
   </reg>

  <reg protect="r" name="int_status_h">
    <bits access="r" name="gpint_status_h" pos="NB_GPIO_INT-33:0" rst="0">
      <comment>Each bit represents if there is a GPIO interrupt
      pending.</comment>
      <options>
        <default/>
        <mask/>
        <shift/>
      </options>
    </bits>
  </reg>

  <reg protect="w" name="int_clr_h">
    <bits access="c" name="gpint_clr_h" pos="NB_GPIO_INT-33:0" rst="0">
      <comment>'Write '1' will clear GPIO interrupt.</comment>
    </bits>
  </reg>


</module>


</archive>

<archive relative = "i2c_master.xml">

<module name="i2c_master" category="Periph">
    
    <reg protect="rw" name="CTRL">
        
 		<bits access="rw" name="EN" pos="0" rst="0">
			<comment> I2C master enable, high active. 
			</comment>
		</bits>
        
		<bits access="rw" name="IRQ_MASK" pos="8" rst="0">
			<comment> I2C master interrupt enable, high active. 
			</comment>
		</bits>
        
		<bits access="rw" name="Clock_Prescale" pos="31:16" rst="0xFFFF">
            <comment> This register is used to prescale the SCL clock line. Due to the structure of I2C interface, this module uses a 5*SCL clock frequency. Clock_Prescale must be programmed to this 5*SCL clock frequency (minus 1). Change the value of Clock_Prescale only when bit EN is cleared. <br /> <br /> Example:<br /> PCLK_MOD is 52 MHz, desired SCL is 100 KHz. <br /> Prescale = 52MHz / (5 * 100KHz) -1 = 103.
			</comment>
            <options><mask/></options>
		</bits>
	</reg>

    <reg protect="r" name="STATUS">
        
        <bits access="r" name="IRQ_Cause" pos="0" rst="0">
			<comment> IRQ Cause bit. This bit is set when one byte transfer has been completed or arbitration is lost, this bit is generated by bit IRQ_Status AND bit IRQ_MASK.
			</comment>
        </bits>
        
		<bits access="r" name="IRQ_Status" pos="4" rst="0">
			<comment> IRQ status bit. 
			</comment>
        </bits>
        
		<bits access="r" name="TIP" pos="8" rst="0">
			<comment> TIP, Transfer in progress.
				'1' when transferring data. '0' when transfer complete.
			</comment>
		</bits>
        
		<bits access="r" name="AL" pos="12" rst="0">
			<comment> AL,Arbitration lost.
				This bit is set when the I2C master lost arbitration.
			</comment>
		</bits>
        
		<bits access="r" name="Busy" pos="16" rst="0">
			<comment> Busy,I2C bus busy.
				'1' after START signal detected.
				'0' after STOP signal detected.
			</comment>
		</bits>
        
		<bits access="r" name="RxACK" pos="20" rst="0">
			<comment> RxACK, Received acknowledge from slave.
				'1'= "No ACK" received.
				'0'= ACK received.
			</comment>
		</bits>
    </reg>
    
	<reg protect="rw" name="TXRX_BUFFER">
        
		<bits access="w" name="TX_DATA" pos="7:0" rst="-">
			<comment> Byte to transmit via I2C. <br /> for Bit 0, In case of a data transfer this bit represents the data's LSB. In case of a slave address transfer this bit represents the RW bit. <br /> '1' = reading from slave. <br /> '0' = writing to slave.   
			</comment>
		</bits>

 		<bits access="r" name="RX_DATA" pos="7:0" rst="-">
			<comment> Last byte received via I2C. 
			</comment>
		</bits>
        
	</reg>

	<reg protect="w" name="CMD">

		<bits access="w" name="ACK" pos="0" rst="0">
			<comment> ACK,when master works as a receiver,sent ACK(ACK='0') or NACK(ACK='1').
			</comment>
		</bits>

		<bits access="w" name="RD" pos="4" rst="0">
			<comment> RD,read from slave, this bit is auto cleared.
			</comment>
		</bits>

		<bits access="w" name="STO" pos="8" rst="0">
			<comment> STO,generate stop condition, this bit is auto cleared.
			</comment>
		</bits>
        
		<bits access="w" name="WR" pos="12" rst="0">
			<comment> WR,write to slave, this bit is auto cleared.
			</comment>
		</bits>

		<bits access="w" name="STA" pos="16" rst="0">
			<comment> STA,generate (repeated) start condition, this bit is auto cleared.
			</comment>
		</bits>
    </reg>

  	<reg protect="rw" name="IRQ_CLR">  
        
		<bits access="c" name="IRQ_Clr" pos="0" rst="0">
			<comment> When write '1', clears a pending I2C interrupt.
			</comment>
        </bits>
    </reg>
    

</module>
</archive>
<archive relative = "iomux.xml">
<module name="iomux" category="System">
  
 

  <reg name="pad_M_DQ_0_cfg" protect="rw">
     <bits name="pad_M_DQ_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_0 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_0 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_0 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_0 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_0 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_0 select</comment>
     <options>
            <option name="fun_M_DQ_0_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQ_1_cfg" protect="rw">
     <bits name="pad_M_DQ_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_1 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_1 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_1 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_1 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_1 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_1 select</comment>
     <options>
            <option name="fun_M_DQ_1_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQ_2_cfg" protect="rw">
     <bits name="pad_M_DQ_2_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_2 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_2_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_2 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_2_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_2 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_2_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_2 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_2_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_2 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_2_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_2 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_2_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_2 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_2_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_2 select</comment>
     <options>
            <option name="fun_M_DQ_2_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQ_3_cfg" protect="rw">
     <bits name="pad_M_DQ_3_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_3 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_3_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_3 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_3_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_3 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_3_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_3 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_3_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_3 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_3_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_3 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_3_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_3 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_3_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_3 select</comment>
     <options>
            <option name="fun_M_DQ_3_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQ_4_cfg" protect="rw">
     <bits name="pad_M_DQ_4_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_4 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_4_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_4 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_4_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_4 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_4_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_4 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_4_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_4 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_4_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_4 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_4_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_4 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_4_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_4 select</comment>
     <options>
            <option name="fun_M_DQ_4_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQ_5_cfg" protect="rw">
     <bits name="pad_M_DQ_5_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_5 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_5_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_5 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_5_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_5 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_5_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_5 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_5_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_5 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_5_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_5 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_5_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_5 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_5_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_5 select</comment>
     <options>
            <option name="fun_M_DQ_5_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQ_6_cfg" protect="rw">
     <bits name="pad_M_DQ_6_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_6 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_6_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_6 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_6_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_6 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_6_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_6 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_6_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_6 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_6_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_6 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_6_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_6 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_6_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_6 select</comment>
     <options>
            <option name="fun_M_DQ_6_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQ_7_cfg" protect="rw">
     <bits name="pad_M_DQ_7_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQ_7 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQ_7_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQ_7 PUll up</comment>
     </bits>
     <bits name="pad_M_DQ_7_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQ_7 PUll down</comment>
     </bits>
     <bits name="pad_M_DQ_7_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQ_7 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQ_7_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQ_7 force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQ_7_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQ_7 force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQ_7_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQ_7 pin output value. </comment>
     </bits>
     <bits name="pad_M_DQ_7_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQ_7 select</comment>
     <options>
            <option name="fun_M_DQ_7_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_CS_cfg" protect="rw">
     <bits name="pad_M_CS_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_CS force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_CS_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_CS PUll up</comment>
     </bits>
     <bits name="pad_M_CS_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_CS PUll down</comment>
     </bits>
     <bits name="pad_M_CS_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_CS force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_CS_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_CS force outoen value. </comment>
     </bits>
     <bits name="pad_M_CS_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_CS force output value for output. </comment>
     </bits>
     <bits name="pad_M_CS_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_CS pin output value. </comment>
     </bits>
     <bits name="pad_M_CS_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_CS select</comment>
     <options>
            <option name="fun_M_CS_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DM_cfg" protect="rw">
     <bits name="pad_M_DM_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DM force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DM_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DM PUll up</comment>
     </bits>
     <bits name="pad_M_DM_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DM PUll down</comment>
     </bits>
     <bits name="pad_M_DM_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DM force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DM_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DM force outoen value. </comment>
     </bits>
     <bits name="pad_M_DM_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DM force output value for output. </comment>
     </bits>
     <bits name="pad_M_DM_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DM pin output value. </comment>
     </bits>
     <bits name="pad_M_DM_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DM select</comment>
     <options>
            <option name="fun_M_DM_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_CLK_cfg" protect="rw">
     <bits name="pad_M_CLK_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_CLK force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_CLK_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_CLK PUll up</comment>
     </bits>
     <bits name="pad_M_CLK_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_CLK PUll down</comment>
     </bits>
     <bits name="pad_M_CLK_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_CLK force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_CLK_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_CLK force outoen value. </comment>
     </bits>
     <bits name="pad_M_CLK_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_CLK force output value for output. </comment>
     </bits>
     <bits name="pad_M_CLK_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_CLK pin output value. </comment>
     </bits>
     <bits name="pad_M_CLK_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_CLK select</comment>
     <options>
            <option name="fun_M_CLK_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_CLKB_cfg" protect="rw">
     <bits name="pad_M_CLKB_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_CLKB force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_CLKB_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_CLKB PUll up</comment>
     </bits>
     <bits name="pad_M_CLKB_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_CLKB PUll down</comment>
     </bits>
     <bits name="pad_M_CLKB_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_CLKB force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_CLKB_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_CLKB force outoen value. </comment>
     </bits>
     <bits name="pad_M_CLKB_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_CLKB force output value for output. </comment>
     </bits>
     <bits name="pad_M_CLKB_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_CLKB pin output value. </comment>
     </bits>
     <bits name="pad_M_CLKB_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_CLKB select</comment>
     <options>
            <option name="fun_M_CLKB_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_DQS_cfg" protect="rw">
     <bits name="pad_M_DQS_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_DQS force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_DQS_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_DQS PUll up</comment>
     </bits>
     <bits name="pad_M_DQS_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_DQS PUll down</comment>
     </bits>
     <bits name="pad_M_DQS_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_DQS force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_DQS_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_DQS force outoen value. </comment>
     </bits>
     <bits name="pad_M_DQS_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_DQS force output value for output. </comment>
     </bits>
     <bits name="pad_M_DQS_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_DQS pin output value. </comment>
     </bits>
     <bits name="pad_M_DQS_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_DQS select</comment>
     <options>
            <option name="fun_M_DQS_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_SPI_CLK_cfg" protect="rw">
     <bits name="pad_M_SPI_CLK_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_SPI_CLK force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_SPI_CLK_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_SPI_CLK PUll up</comment>
     </bits>
     <bits name="pad_M_SPI_CLK_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_SPI_CLK PUll down</comment>
     </bits>
     <bits name="pad_M_SPI_CLK_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_SPI_CLK force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_SPI_CLK_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_SPI_CLK force outoen value. </comment>
     </bits>
     <bits name="pad_M_SPI_CLK_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_SPI_CLK force output value for output. </comment>
     </bits>
     <bits name="pad_M_SPI_CLK_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_SPI_CLK pin output value. </comment>
     </bits>
     <bits name="pad_M_SPI_CLK_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_SPI_CLK select</comment>
     <options>
            <option name="fun_M_SPI_CLK_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_SPI_CS_cfg" protect="rw">
     <bits name="pad_M_SPI_CS_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_SPI_CS force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_SPI_CS_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_SPI_CS PUll up</comment>
     </bits>
     <bits name="pad_M_SPI_CS_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_SPI_CS PUll down</comment>
     </bits>
     <bits name="pad_M_SPI_CS_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_SPI_CS force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_SPI_CS_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_SPI_CS force outoen value. </comment>
     </bits>
     <bits name="pad_M_SPI_CS_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_SPI_CS force output value for output. </comment>
     </bits>
     <bits name="pad_M_SPI_CS_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_SPI_CS pin output value. </comment>
     </bits>
     <bits name="pad_M_SPI_CS_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_SPI_CS select</comment>
     <options>
            <option name="fun_M_SPI_CS_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_SPI_D_0_cfg" protect="rw">
     <bits name="pad_M_SPI_D_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_SPI_D_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_SPI_D_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_SPI_D_0 PUll up</comment>
     </bits>
     <bits name="pad_M_SPI_D_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_SPI_D_0 PUll down</comment>
     </bits>
     <bits name="pad_M_SPI_D_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_SPI_D_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_SPI_D_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_SPI_D_0 force outoen value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_SPI_D_0 force output value for output. </comment>
     </bits>
     <bits name="pad_M_SPI_D_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_SPI_D_0 pin output value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_SPI_D_0 select</comment>
     <options>
            <option name="fun_M_SPI_D_0_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_SPI_D_1_cfg" protect="rw">
     <bits name="pad_M_SPI_D_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_SPI_D_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_SPI_D_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_SPI_D_1 PUll up</comment>
     </bits>
     <bits name="pad_M_SPI_D_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_SPI_D_1 PUll down</comment>
     </bits>
     <bits name="pad_M_SPI_D_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_SPI_D_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_SPI_D_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_SPI_D_1 force outoen value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_SPI_D_1 force output value for output. </comment>
     </bits>
     <bits name="pad_M_SPI_D_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_SPI_D_1 pin output value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_SPI_D_1 select</comment>
     <options>
            <option name="fun_M_SPI_D_1_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_SPI_D_2_cfg" protect="rw">
     <bits name="pad_M_SPI_D_2_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_SPI_D_2 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_SPI_D_2_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_SPI_D_2 PUll up</comment>
     </bits>
     <bits name="pad_M_SPI_D_2_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_SPI_D_2 PUll down</comment>
     </bits>
     <bits name="pad_M_SPI_D_2_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_SPI_D_2 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_SPI_D_2_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_SPI_D_2 force outoen value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_2_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_SPI_D_2 force output value for output. </comment>
     </bits>
     <bits name="pad_M_SPI_D_2_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_SPI_D_2 pin output value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_2_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_SPI_D_2 select</comment>
     <options>
            <option name="fun_M_SPI_D_2_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_M_SPI_D_3_cfg" protect="rw">
     <bits name="pad_M_SPI_D_3_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>M_SPI_D_3 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_M_SPI_D_3_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>M_SPI_D_3 PUll up</comment>
     </bits>
     <bits name="pad_M_SPI_D_3_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>M_SPI_D_3 PUll down</comment>
     </bits>
     <bits name="pad_M_SPI_D_3_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>M_SPI_D_3 force enable for outoen. </comment>
     </bits>
     <bits name="pad_M_SPI_D_3_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>M_SPI_D_3 force outoen value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_3_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>M_SPI_D_3 force output value for output. </comment>
     </bits>
     <bits name="pad_M_SPI_D_3_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>M_SPI_D_3 pin output value. </comment>
     </bits>
     <bits name="pad_M_SPI_D_3_sel" pos="3:0" access="rw" rst="0"> 
         <comment>M_SPI_D_3 select</comment>
     <options>
            <option name="fun_M_SPI_D_3_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SDMMC_CLK_cfg" protect="rw">
     <bits name="pad_SDMMC_CLK_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SDMMC_CLK force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SDMMC_CLK_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SDMMC_CLK PUll up</comment>
     </bits>
     <bits name="pad_SDMMC_CLK_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SDMMC_CLK PUll down</comment>
     </bits>
     <bits name="pad_SDMMC_CLK_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SDMMC_CLK force enable for outoen. </comment>
     </bits>
     <bits name="pad_SDMMC_CLK_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SDMMC_CLK force outoen value. </comment>
     </bits>
     <bits name="pad_SDMMC_CLK_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SDMMC_CLK force output value for output. </comment>
     </bits>
     <bits name="pad_SDMMC_CLK_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SDMMC_CLK pin output value. </comment>
     </bits>
     <bits name="pad_SDMMC_CLK_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SDMMC_CLK select</comment>
     <options>
            <option name="fun_SDMMC_CLK_sel" value ="0"></option>
            <option name="fun_GPIO_16_sel" value ="1"></option>
            <option name="fun_SPI1_CLK_sel" value ="2"></option>
            <option name="fun_wcn_m_symbol_rx_0_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_rx_0_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SDMMC_CMD_cfg" protect="rw">
     <bits name="pad_SDMMC_CMD_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SDMMC_CMD force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SDMMC_CMD_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SDMMC_CMD PUll up</comment>
     </bits>
     <bits name="pad_SDMMC_CMD_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SDMMC_CMD PUll down</comment>
     </bits>
     <bits name="pad_SDMMC_CMD_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SDMMC_CMD force enable for outoen. </comment>
     </bits>
     <bits name="pad_SDMMC_CMD_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SDMMC_CMD force outoen value. </comment>
     </bits>
     <bits name="pad_SDMMC_CMD_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SDMMC_CMD force output value for output. </comment>
     </bits>
     <bits name="pad_SDMMC_CMD_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SDMMC_CMD pin output value. </comment>
     </bits>
     <bits name="pad_SDMMC_CMD_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SDMMC_CMD select</comment>
     <options>
            <option name="fun_SDMMC_CMD_sel" value ="0"></option>
            <option name="fun_GPIO_17_sel" value ="1"></option>
            <option name="fun_SPI1_CS_0_sel" value ="2"></option>
            <option name="fun_wcn_m_symbol_rx_1_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_rx_1_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SDMMC_DAT_0_cfg" protect="rw">
     <bits name="pad_SDMMC_DAT_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_0 PUll up</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_0 PUll down</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_0 force outoen value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_0 force output value for output. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_0 pin output value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SDMMC_DAT_0 select</comment>
     <options>
            <option name="fun_SDMMC_DAT_0_sel" value ="0"></option>
            <option name="fun_GPIO_18_sel" value ="1"></option>
            <option name="fun_SPI1_CS_1_sel" value ="2"></option>
            <option name="fun_wcn_m_symbol_rx_2_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_rx_2_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SDMMC_DAT_1_cfg" protect="rw">
     <bits name="pad_SDMMC_DAT_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_1 PUll up</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_1 PUll down</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_1 force outoen value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_1 force output value for output. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_1 pin output value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SDMMC_DAT_1 select</comment>
     <options>
            <option name="fun_SDMMC_DAT_1_sel" value ="0"></option>
            <option name="fun_GPIO_19_sel" value ="1"></option>
            <option name="fun_SPI1_DI_0_sel" value ="2"></option>
            <option name="fun_wcn_m_symbol_flag_rx_0_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_flag_rx_0_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SDMMC_DAT_2_cfg" protect="rw">
     <bits name="pad_SDMMC_DAT_2_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_2 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_2_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_2 PUll up</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_2_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_2 PUll down</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_2_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_2 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_2_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_2 force outoen value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_2_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_2 force output value for output. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_2_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_2 pin output value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_2_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SDMMC_DAT_2 select</comment>
     <options>
            <option name="fun_SDMMC_DAT_2_sel" value ="0"></option>
            <option name="fun_GPIO_20_sel" value ="1"></option>
            <option name="fun_SPI1_DI_1_sel" value ="2"></option>
            <option name="fun_wcn_m_symbol_flag_rx_1_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_flag_rx_1_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SDMMC_DAT_3_cfg" protect="rw">
     <bits name="pad_SDMMC_DAT_3_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_3 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_3_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_3 PUll up</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_3_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_3 PUll down</comment>
     </bits>
     <bits name="pad_SDMMC_DAT_3_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_3 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_3_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_3 force outoen value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_3_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_3 force output value for output. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_3_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SDMMC_DAT_3 pin output value. </comment>
     </bits>
     <bits name="pad_SDMMC_DAT_3_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SDMMC_DAT_3 select</comment>
     <options>
            <option name="fun_SDMMC_DAT_3_sel" value ="0"></option>
            <option name="fun_GPIO_21_sel" value ="1"></option>
            <option name="fun_wcn_m_symbol_flag_rx_2_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_flag_rx_2_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_LCD_RSTB_cfg" protect="rw">
     <bits name="pad_LCD_RSTB_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>LCD_RSTB force enable for pu/pd </comment>
     </bits>
     <bits name="pad_LCD_RSTB_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>LCD_RSTB PUll up</comment>
     </bits>
     <bits name="pad_LCD_RSTB_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>LCD_RSTB PUll down</comment>
     </bits>
     <bits name="pad_LCD_RSTB_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>LCD_RSTB force enable for outoen. </comment>
     </bits>
     <bits name="pad_LCD_RSTB_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>LCD_RSTB force outoen value. </comment>
     </bits>
     <bits name="pad_LCD_RSTB_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>LCD_RSTB force output value for output. </comment>
     </bits>
     <bits name="pad_LCD_RSTB_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>LCD_RSTB pin output value. </comment>
     </bits>
     <bits name="pad_LCD_RSTB_sel" pos="3:0" access="rw" rst="0"> 
         <comment>LCD_RSTB select</comment>
     <options>
            <option name="fun_LCD_RSTB_sel" value ="0"></option>
            <option name="fun_GPIO_22_sel" value ="1"></option>
            <option name="fun_DAI_RST_sel" value ="2"></option>
            <option name="fun_I2S_BCK_sel" value ="3"></option>
            <option name="fun_SEGOUT_0_sel" value ="5"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_LCD_SPI_CS_cfg" protect="rw">
     <bits name="pad_LCD_SPI_CS_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>LCD_SPI_CS force enable for pu/pd </comment>
     </bits>
     <bits name="pad_LCD_SPI_CS_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>LCD_SPI_CS PUll up</comment>
     </bits>
     <bits name="pad_LCD_SPI_CS_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>LCD_SPI_CS PUll down</comment>
     </bits>
     <bits name="pad_LCD_SPI_CS_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>LCD_SPI_CS force enable for outoen. </comment>
     </bits>
     <bits name="pad_LCD_SPI_CS_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>LCD_SPI_CS force outoen value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_CS_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>LCD_SPI_CS force output value for output. </comment>
     </bits>
     <bits name="pad_LCD_SPI_CS_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>LCD_SPI_CS pin output value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_CS_sel" pos="3:0" access="rw" rst="0"> 
         <comment>LCD_SPI_CS select</comment>
     <options>
            <option name="fun_LCD_SPI_CS_sel" value ="0"></option>
            <option name="fun_GPIO_23_sel" value ="1"></option>
            <option name="fun_DAI_CLK_sel" value ="2"></option>
            <option name="fun_I2S_LRCK_sel" value ="3"></option>
            <option name="fun_SEGOUT_1_sel" value ="5"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_LCD_SPI_SCK_cfg" protect="rw">
     <bits name="pad_LCD_SPI_SCK_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SCK force enable for pu/pd </comment>
     </bits>
     <bits name="pad_LCD_SPI_SCK_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SCK PUll up</comment>
     </bits>
     <bits name="pad_LCD_SPI_SCK_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SCK PUll down</comment>
     </bits>
     <bits name="pad_LCD_SPI_SCK_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SCK force enable for outoen. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SCK_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SCK force outoen value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SCK_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SCK force output value for output. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SCK_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SCK pin output value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SCK_sel" pos="3:0" access="rw" rst="0"> 
         <comment>LCD_SPI_SCK select</comment>
     <options>
            <option name="fun_LCD_SPI_SCK_sel" value ="0"></option>
            <option name="fun_GPIO_24_sel" value ="1"></option>
            <option name="fun_DAI_DI_sel" value ="2"></option>
            <option name="fun_I2S_DI_sel" value ="3"></option>
            <option name="fun_SEGOUT_2_sel" value ="5"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_LCD_SPI_DIO_cfg" protect="rw">
     <bits name="pad_LCD_SPI_DIO_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>LCD_SPI_DIO force enable for pu/pd </comment>
     </bits>
     <bits name="pad_LCD_SPI_DIO_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>LCD_SPI_DIO PUll up</comment>
     </bits>
     <bits name="pad_LCD_SPI_DIO_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>LCD_SPI_DIO PUll down</comment>
     </bits>
     <bits name="pad_LCD_SPI_DIO_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>LCD_SPI_DIO force enable for outoen. </comment>
     </bits>
     <bits name="pad_LCD_SPI_DIO_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>LCD_SPI_DIO force outoen value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_DIO_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>LCD_SPI_DIO force output value for output. </comment>
     </bits>
     <bits name="pad_LCD_SPI_DIO_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>LCD_SPI_DIO pin output value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_DIO_sel" pos="3:0" access="rw" rst="0"> 
         <comment>LCD_SPI_DIO select</comment>
     <options>
            <option name="fun_LCD_SPI_DIO_sel" value ="0"></option>
            <option name="fun_GPIO_25_sel" value ="1"></option>
            <option name="fun_DAI_DO_sel" value ="2"></option>
            <option name="fun_I2S_DO_sel" value ="3"></option>
            <option name="fun_SEGOUT_3_sel" value ="5"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_LCD_SPI_SDC_cfg" protect="rw">
     <bits name="pad_LCD_SPI_SDC_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SDC force enable for pu/pd </comment>
     </bits>
     <bits name="pad_LCD_SPI_SDC_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SDC PUll up</comment>
     </bits>
     <bits name="pad_LCD_SPI_SDC_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SDC PUll down</comment>
     </bits>
     <bits name="pad_LCD_SPI_SDC_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SDC force enable for outoen. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SDC_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SDC force outoen value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SDC_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SDC force output value for output. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SDC_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>LCD_SPI_SDC pin output value. </comment>
     </bits>
     <bits name="pad_LCD_SPI_SDC_sel" pos="3:0" access="rw" rst="0"> 
         <comment>LCD_SPI_SDC select</comment>
     <options>
            <option name="fun_LCD_SPI_SDC_sel" value ="0"></option>
            <option name="fun_GPIO_26_sel" value ="1"></option>
            <option name="fun_TCO_1_sel" value ="3"></option>
            <option name="fun_SEGOUT_4_sel" value ="5"></option>
            <option name="fun_wcn_m_sync_clk_sel" value ="9"></option>
            <option name="fun_wcn_s_sync_clk_sel" value ="10"></option>
            <option name="fun_wcn_rf_rxon_out_sel" value ="11"></option>
            <option name="fun_wcn_rf_rxon_in_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_LCD_TE_cfg" protect="rw">
     <bits name="pad_LCD_TE_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>LCD_TE force enable for pu/pd </comment>
     </bits>
     <bits name="pad_LCD_TE_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>LCD_TE PUll up</comment>
     </bits>
     <bits name="pad_LCD_TE_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>LCD_TE PUll down</comment>
     </bits>
     <bits name="pad_LCD_TE_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>LCD_TE force enable for outoen. </comment>
     </bits>
     <bits name="pad_LCD_TE_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>LCD_TE force outoen value. </comment>
     </bits>
     <bits name="pad_LCD_TE_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>LCD_TE force output value for output. </comment>
     </bits>
     <bits name="pad_LCD_TE_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>LCD_TE pin output value. </comment>
     </bits>
     <bits name="pad_LCD_TE_sel" pos="3:0" access="rw" rst="0"> 
         <comment>LCD_TE select</comment>
     <options>
            <option name="fun_LCD_TE_sel" value ="0"></option>
            <option name="fun_GPIO_27_sel" value ="1"></option>
            <option name="fun_CLK_32K_sel" value ="2"></option>
            <option name="fun_PWT_1_sel" value ="3"></option>
            <option name="fun_SEGOUT_5_sel" value ="5"></option>
            <option name="fun_wcn_m_sync_dat_sel" value ="9"></option>
            <option name="fun_wcn_s_sync_dat_sel" value ="10"></option>
            <option name="fun_wcn_rf_txon_out_sel" value ="11"></option>
            <option name="fun_wcn_rf_txon_in_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_CAM_PWDN_cfg" protect="rw">
     <bits name="pad_CAM_PWDN_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>CAM_PWDN force enable for pu/pd </comment>
     </bits>
     <bits name="pad_CAM_PWDN_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>CAM_PWDN PUll up</comment>
     </bits>
     <bits name="pad_CAM_PWDN_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>CAM_PWDN PUll down</comment>
     </bits>
     <bits name="pad_CAM_PWDN_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>CAM_PWDN force enable for outoen. </comment>
     </bits>
     <bits name="pad_CAM_PWDN_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>CAM_PWDN force outoen value. </comment>
     </bits>
     <bits name="pad_CAM_PWDN_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>CAM_PWDN force output value for output. </comment>
     </bits>
     <bits name="pad_CAM_PWDN_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>CAM_PWDN pin output value. </comment>
     </bits>
     <bits name="pad_CAM_PWDN_sel" pos="3:0" access="rw" rst="0"> 
         <comment>CAM_PWDN select</comment>
     <options>
            <option name="fun_CAM_PWDN_sel" value ="0"></option>
            <option name="fun_GPIO_28_sel" value ="1"></option>
            <option name="fun_SPI2_CLK_sel" value ="2"></option>
            <option name="fun_M2_SPI_CLK_sel" value ="3"></option>
            <option name="fun_SDMMC2_CLK_sel" value ="4"></option>
            <option name="fun_SEGOUT_6_sel" value ="5"></option>
            <option name="fun_wcn_m_senb_sel" value ="9"></option>
            <option name="fun_wcn_s_senb_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_CAM_RSTB_cfg" protect="rw">
     <bits name="pad_CAM_RSTB_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>CAM_RSTB force enable for pu/pd </comment>
     </bits>
     <bits name="pad_CAM_RSTB_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>CAM_RSTB PUll up</comment>
     </bits>
     <bits name="pad_CAM_RSTB_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>CAM_RSTB PUll down</comment>
     </bits>
     <bits name="pad_CAM_RSTB_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>CAM_RSTB force enable for outoen. </comment>
     </bits>
     <bits name="pad_CAM_RSTB_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>CAM_RSTB force outoen value. </comment>
     </bits>
     <bits name="pad_CAM_RSTB_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>CAM_RSTB force output value for output. </comment>
     </bits>
     <bits name="pad_CAM_RSTB_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>CAM_RSTB pin output value. </comment>
     </bits>
     <bits name="pad_CAM_RSTB_sel" pos="3:0" access="rw" rst="0"> 
         <comment>CAM_RSTB select</comment>
     <options>
            <option name="fun_CAM_RSTB_sel" value ="0"></option>
            <option name="fun_GPIO_29_sel" value ="1"></option>
            <option name="fun_SPI2_CS_0_sel" value ="2"></option>
            <option name="fun_M2_SPI_CS_sel" value ="3"></option>
            <option name="fun_SDMMC2_CMD_sel" value ="4"></option>
            <option name="fun_SEGOUT_7_sel" value ="5"></option>
            <option name="fun_wcn_m_sclk_sel" value ="9"></option>
            <option name="fun_wcn_s_sclk_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_CAM_CLK_cfg" protect="rw">
     <bits name="pad_CAM_CLK_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>CAM_CLK force enable for pu/pd </comment>
     </bits>
     <bits name="pad_CAM_CLK_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>CAM_CLK PUll up</comment>
     </bits>
     <bits name="pad_CAM_CLK_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>CAM_CLK PUll down</comment>
     </bits>
     <bits name="pad_CAM_CLK_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>CAM_CLK force enable for outoen. </comment>
     </bits>
     <bits name="pad_CAM_CLK_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>CAM_CLK force outoen value. </comment>
     </bits>
     <bits name="pad_CAM_CLK_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>CAM_CLK force output value for output. </comment>
     </bits>
     <bits name="pad_CAM_CLK_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>CAM_CLK pin output value. </comment>
     </bits>
     <bits name="pad_CAM_CLK_sel" pos="3:0" access="rw" rst="0"> 
         <comment>CAM_CLK select</comment>
     <options>
            <option name="fun_CAM_CLK_sel" value ="0"></option>
            <option name="fun_GPIO_30_sel" value ="1"></option>
            <option name="fun_SPI2_CS_1_sel" value ="2"></option>
            <option name="fun_M2_SPI_D_0_sel" value ="3"></option>
            <option name="fun_SDMMC2_DAT_0_sel" value ="4"></option>
            <option name="fun_SEGOUT_8_sel" value ="5"></option>
            <option name="fun_wcn_m_sdo_sel" value ="9"></option>
            <option name="fun_wcn_s_sdo_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_CAM_SPI_SCK_cfg" protect="rw">
     <bits name="pad_CAM_SPI_SCK_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>CAM_SPI_SCK force enable for pu/pd </comment>
     </bits>
     <bits name="pad_CAM_SPI_SCK_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>CAM_SPI_SCK PUll up</comment>
     </bits>
     <bits name="pad_CAM_SPI_SCK_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>CAM_SPI_SCK PUll down</comment>
     </bits>
     <bits name="pad_CAM_SPI_SCK_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>CAM_SPI_SCK force enable for outoen. </comment>
     </bits>
     <bits name="pad_CAM_SPI_SCK_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>CAM_SPI_SCK force outoen value. </comment>
     </bits>
     <bits name="pad_CAM_SPI_SCK_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>CAM_SPI_SCK force output value for output. </comment>
     </bits>
     <bits name="pad_CAM_SPI_SCK_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>CAM_SPI_SCK pin output value. </comment>
     </bits>
     <bits name="pad_CAM_SPI_SCK_sel" pos="3:0" access="rw" rst="0"> 
         <comment>CAM_SPI_SCK select</comment>
     <options>
            <option name="fun_CAM_SPI_SCK_sel" value ="0"></option>
            <option name="fun_GPIO_31_sel" value ="1"></option>
            <option name="fun_SPI2_DI_0_sel" value ="2"></option>
            <option name="fun_M2_SPI_D_1_sel" value ="3"></option>
            <option name="fun_SDMMC2_DAT_1_sel" value ="4"></option>
            <option name="fun_SEGOUT_9_sel" value ="5"></option>
            <option name="fun_wcn_m_sdi_sel" value ="9"></option>
            <option name="fun_wcn_s_sdi_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_CAM_SPI_DI_0_cfg" protect="rw">
     <bits name="pad_CAM_SPI_DI_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_0 PUll up</comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_0 PUll down</comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_0 force outoen value. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_0 force output value for output. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_0 pin output value. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>CAM_SPI_DI_0 select</comment>
     <options>
            <option name="fun_CAM_SPI_DI_0_sel" value ="0"></option>
            <option name="fun_GPIO_32_sel" value ="1"></option>
            <option name="fun_SPI2_DI_1_sel" value ="2"></option>
            <option name="fun_M2_SPI_D_2_sel" value ="3"></option>
            <option name="fun_SDMMC2_DAT_2_sel" value ="4"></option>
            <option name="fun_SEGOUT_10_sel" value ="5"></option>
            <option name="fun_wcn_m_newpkt_flag_sel" value ="9"></option>
            <option name="fun_wcn_s_newpkt_flag_sel" value ="10"></option>
            <option name="fun_wcn_bt_ch_type_in_sel" value ="11"></option>
            <option name="fun_wcn_bt_ch_type_out_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_CAM_SPI_DI_1_cfg" protect="rw">
     <bits name="pad_CAM_SPI_DI_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_1 PUll up</comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_1 PUll down</comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_1 force outoen value. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_1 force output value for output. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>CAM_SPI_DI_1 pin output value. </comment>
     </bits>
     <bits name="pad_CAM_SPI_DI_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>CAM_SPI_DI_1 select</comment>
     <options>
            <option name="fun_CAM_SPI_DI_1_sel" value ="0"></option>
            <option name="fun_GPIO_33_sel" value ="1"></option>
            <option name="fun_CLK_32K_sel" value ="2"></option>
            <option name="fun_M2_SPI_D_3_sel" value ="3"></option>
            <option name="fun_SDMMC2_DAT_3_sel" value ="4"></option>
            <option name="fun_SEGOUT_11_sel" value ="5"></option>
            <option name="fun_wcn_m_le_mode_sel" value ="9"></option>
            <option name="fun_wcn_s_le_mode_sel" value ="10"></option>
            <option name="fun_wcn_rf_m_bt_tx_52m_sel" value ="11"></option>
            <option name="fun_wcn_rf_s_bt_tx_52m_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_0_cfg" protect="rw">
     <bits name="pad_GPIO_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_0 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_0 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_0 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_0 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_0 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_0 select</comment>
     <options>
            <option name="fun_GPIO_0_sel" value ="0"></option>
            <option name="fun_UART1_RXD_sel" value ="1"></option>
            <option name="fun_DBG_DO_0_sel" value ="6"></option>
            <option name="fun_rf_spi_clk_m_sel" value ="7"></option>
            <option name="fun_rf_spi_clk_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_rxd_sel" value ="9"></option>
            <option name="fun_wcn_pcmfsync_sel" value ="10"></option>
            <option name="fun_wcn_tck_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_1_cfg" protect="rw">
     <bits name="pad_GPIO_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_1 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_1 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_1 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_1 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_1 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_1 select</comment>
     <options>
            <option name="fun_GPIO_1_sel" value ="0"></option>
            <option name="fun_UART1_TXD_sel" value ="1"></option>
            <option name="fun_SPI1_CS_1_sel" value ="2"></option>
            <option name="fun_DBG_DO_1_sel" value ="6"></option>
            <option name="fun_rf_spi_cs_m_sel" value ="7"></option>
            <option name="fun_rf_spi_cs_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_txd_sel" value ="9"></option>
            <option name="fun_wcn_pcmclk_sel" value ="10"></option>
            <option name="fun_wcn_tms_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_2_cfg" protect="rw">
     <bits name="pad_GPIO_2_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_2 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_2_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_2 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_2_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_2 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_2_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_2 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_2_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_2 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_2_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_2 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_2_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_2 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_2_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_2 select</comment>
     <options>
            <option name="fun_GPIO_2_sel" value ="0"></option>
            <option name="fun_UART1_CTS_sel" value ="1"></option>
            <option name="fun_SPI1_DI_0_sel" value ="2"></option>
            <option name="fun_TCO_1_sel" value ="3"></option>
            <option name="fun_SDMMC2_DAT_0_sel" value ="4"></option>
            <option name="fun_DBG_DO_2_sel" value ="6"></option>
            <option name="fun_rf_spi_do_m_sel" value ="7"></option>
            <option name="fun_rf_spi_di_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_cts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdin_sel" value ="10"></option>
            <option name="fun_wcn_tdi_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_3_cfg" protect="rw">
     <bits name="pad_GPIO_3_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_3 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_3_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_3 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_3_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_3 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_3_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_3 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_3_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_3 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_3_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_3 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_3_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_3 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_3_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_3 select</comment>
     <options>
            <option name="fun_GPIO_3_sel" value ="0"></option>
            <option name="fun_UART1_RTS_sel" value ="1"></option>
            <option name="fun_SPI1_DI_1_sel" value ="2"></option>
            <option name="fun_PWT_1_sel" value ="3"></option>
            <option name="fun_SDMMC2_DAT_1_sel" value ="4"></option>
            <option name="fun_DBG_DO_3_sel" value ="6"></option>
            <option name="fun_rf_spi_di_m_sel" value ="7"></option>
            <option name="fun_rf_spi_do_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_rts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdout_sel" value ="10"></option>
            <option name="fun_wcn_tdo_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_4_cfg" protect="rw">
     <bits name="pad_GPIO_4_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_4 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_4_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_4 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_4_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_4 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_4_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_4 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_4_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_4 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_4_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_4 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_4_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_4 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_4_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_4 select</comment>
     <options>
            <option name="fun_GPIO_4_sel" value ="0"></option>
            <option name="fun_UART2_RXD_sel" value ="1"></option>
            <option name="fun_SPI1_DI_0_sel" value ="2"></option>
            <option name="fun_SDMMC2_DAT_2_sel" value ="4"></option>
            <option name="fun_DBG_DO_4_sel" value ="6"></option>
            <option name="fun_dfe_rx_en_m_sel" value ="7"></option>
            <option name="fun_dfe_rx_en_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_rxd_sel" value ="9"></option>
            <option name="fun_wcn_pcmfsync_sel" value ="10"></option>
            <option name="fun_wcn_trstn_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_5_cfg" protect="rw">
     <bits name="pad_GPIO_5_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_5 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_5_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_5 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_5_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_5 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_5_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_5 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_5_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_5 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_5_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_5 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_5_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_5 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_5_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_5 select</comment>
     <options>
            <option name="fun_GPIO_5_sel" value ="0"></option>
            <option name="fun_UART2_TXD_sel" value ="1"></option>
            <option name="fun_SPI1_DI_1_sel" value ="2"></option>
            <option name="fun_SDMMC2_DAT_3_sel" value ="4"></option>
            <option name="fun_DBG_DO_5_sel" value ="6"></option>
            <option name="fun_wcn_uart_txd_sel" value ="9"></option>
            <option name="fun_wcn_pcmclk_sel" value ="10"></option>
            <option name="fun_DBG_TRIG_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_6_cfg" protect="rw">
     <bits name="pad_GPIO_6_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_6 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_6_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_6 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_6_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_6 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_6_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_6 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_6_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_6 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_6_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_6 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_6_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_6 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_6_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_6 select</comment>
     <options>
            <option name="fun_GPIO_6_sel" value ="0"></option>
            <option name="fun_UART2_CTS_sel" value ="1"></option>
            <option name="fun_I2C1_SCL_sel" value ="2"></option>
            <option name="fun_DBG_DO_6_sel" value ="6"></option>
            <option name="fun_wcn_uart_cts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdin_sel" value ="10"></option>
            <option name="fun_DBG_CLK_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_7_cfg" protect="rw">
     <bits name="pad_GPIO_7_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_7 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_7_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_7 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_7_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_7 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_7_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_7 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_7_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_7 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_7_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_7 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_7_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_7 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_7_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_7 select</comment>
     <options>
            <option name="fun_GPIO_7_sel" value ="0"></option>
            <option name="fun_UART2_RTS_sel" value ="1"></option>
            <option name="fun_I2C1_SDA_sel" value ="2"></option>
            <option name="fun_DBG_DO_7_sel" value ="6"></option>
            <option name="fun_wcn_uart_rts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdout_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_8_cfg" protect="rw">
     <bits name="pad_GPIO_8_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_8 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_8_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_8 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_8_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_8 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_8_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_8 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_8_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_8 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_8_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_8 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_8_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_8 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_8_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_8 select</comment>
     <options>
            <option name="fun_GPIO_8_sel" value ="0"></option>
            <option name="fun_UART3_RXD_sel" value ="1"></option>
            <option name="fun_TCO_0_sel" value ="3"></option>
            <option name="fun_SDMMC2_CLK_sel" value ="4"></option>
            <option name="fun_DBG_DO_8_sel" value ="6"></option>
            <option name="fun_digrf_rx_en_m_sel" value ="7"></option>
            <option name="fun_digrf_rx_en_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_rxd_sel" value ="9"></option>
            <option name="fun_wcn_pcmfsync_sel" value ="10"></option>
            <option name="fun_wcn_tck_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_9_cfg" protect="rw">
     <bits name="pad_GPIO_9_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_9 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_9_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_9 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_9_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_9 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_9_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_9 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_9_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_9 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_9_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_9 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_9_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_9 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_9_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_9 select</comment>
     <options>
            <option name="fun_GPIO_9_sel" value ="0"></option>
            <option name="fun_UART3_TXD_sel" value ="1"></option>
            <option name="fun_PWT_0_sel" value ="3"></option>
            <option name="fun_SDMMC2_CMD_sel" value ="4"></option>
            <option name="fun_DBG_DO_9_sel" value ="6"></option>
            <option name="fun_digrf_rx_data_m_sel" value ="7"></option>
            <option name="fun_digrf_rx_data_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_txd_sel" value ="9"></option>
            <option name="fun_wcn_pcmclk_sel" value ="10"></option>
            <option name="fun_wcn_tms_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_10_cfg" protect="rw">
     <bits name="pad_GPIO_10_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_10 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_10_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_10 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_10_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_10 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_10_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_10 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_10_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_10 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_10_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_10 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_10_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_10 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_10_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_10 select</comment>
     <options>
            <option name="fun_GPIO_10_sel" value ="0"></option>
            <option name="fun_SPI1_CLK_sel" value ="1"></option>
            <option name="fun_DBG_DO_10_sel" value ="6"></option>
            <option name="fun_digrf_tx_en_m_sel" value ="7"></option>
            <option name="fun_digrf_tx_en_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_cts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdin_sel" value ="10"></option>
            <option name="fun_wcn_tdi_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_11_cfg" protect="rw">
     <bits name="pad_GPIO_11_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_11 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_11_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_11 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_11_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_11 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_11_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_11 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_11_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_11 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_11_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_11 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_11_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_11 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_11_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_11 select</comment>
     <options>
            <option name="fun_GPIO_11_sel" value ="0"></option>
            <option name="fun_SPI1_CS_0_sel" value ="1"></option>
            <option name="fun_DBG_DO_11_sel" value ="6"></option>
            <option name="fun_digrf_tx_data_m_sel" value ="7"></option>
            <option name="fun_digrf_tx_data_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_rts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdout_sel" value ="10"></option>
            <option name="fun_wcn_tdo_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_12_cfg" protect="rw">
     <bits name="pad_GPIO_12_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_12 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_12_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_12 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_12_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_12 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_12_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_12 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_12_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_12 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_12_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_12 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_12_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_12 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_12_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_12 select</comment>
     <options>
            <option name="fun_GPIO_12_sel" value ="0"></option>
            <option name="fun_SPI1_DI_0_sel" value ="1"></option>
            <option name="fun_I2C2_SCL_sel" value ="2"></option>
            <option name="fun_PWL_0_sel" value ="3"></option>
            <option name="fun_DBG_DO_12_sel" value ="6"></option>
            <option name="fun_digrf_tx_strobe_m_sel" value ="7"></option>
            <option name="fun_digrf_tx_strobe_s_sel" value ="8"></option>
            <option name="fun_wcn_uart_rxd_sel" value ="9"></option>
            <option name="fun_wcn_pcmfsync_sel" value ="10"></option>
            <option name="fun_wcn_trstn_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_13_cfg" protect="rw">
     <bits name="pad_GPIO_13_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_13 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_13_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_13 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_13_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_13 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_13_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_13 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_13_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_13 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_13_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_13 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_13_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_13 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_13_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_13 select</comment>
     <options>
            <option name="fun_GPIO_13_sel" value ="0"></option>
            <option name="fun_SPI1_DI_1_sel" value ="1"></option>
            <option name="fun_I2C2_SDA_sel" value ="2"></option>
            <option name="fun_PWL_1_sel" value ="3"></option>
            <option name="fun_LPG_sel" value ="4"></option>
            <option name="fun_DBG_DO_13_sel" value ="6"></option>
            <option name="fun_wcn_uart_txd_sel" value ="9"></option>
            <option name="fun_wcn_pcmclk_sel" value ="10"></option>
            <option name="fun_DBG_TRIG_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_14_cfg" protect="rw">
     <bits name="pad_GPIO_14_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_14 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_14_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_14 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_14_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_14 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_14_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_14 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_14_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_14 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_14_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_14 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_14_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_14 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_14_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_14 select</comment>
     <options>
            <option name="fun_GPIO_14_sel" value ="0"></option>
            <option name="fun_KEYIN_5_sel" value ="1"></option>
            <option name="fun_UART3_CTS_sel" value ="2"></option>
            <option name="fun_SPI1_CS_1_sel" value ="3"></option>
            <option name="fun_XTAL26M_REQ_sel" value ="4"></option>
            <option name="fun_PDM_CLK_sel" value ="5"></option>
            <option name="fun_DBG_DO_14_sel" value ="6"></option>
            <option name="fun_wcn_uart_cts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdin_sel" value ="10"></option>
            <option name="fun_DBG_CLK_sel" value ="11"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_GPIO_15_cfg" protect="rw">
     <bits name="pad_GPIO_15_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>GPIO_15 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_GPIO_15_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>GPIO_15 PUll up</comment>
     </bits>
     <bits name="pad_GPIO_15_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>GPIO_15 PUll down</comment>
     </bits>
     <bits name="pad_GPIO_15_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>GPIO_15 force enable for outoen. </comment>
     </bits>
     <bits name="pad_GPIO_15_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>GPIO_15 force outoen value. </comment>
     </bits>
     <bits name="pad_GPIO_15_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>GPIO_15 force output value for output. </comment>
     </bits>
     <bits name="pad_GPIO_15_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>GPIO_15 pin output value. </comment>
     </bits>
     <bits name="pad_GPIO_15_sel" pos="3:0" access="rw" rst="0"> 
         <comment>GPIO_15 select</comment>
     <options>
            <option name="fun_GPIO_15_sel" value ="0"></option>
            <option name="fun_KEYOUT_5_sel" value ="1"></option>
            <option name="fun_UART3_RTS_sel" value ="2"></option>
            <option name="fun_CAM_SPI_SSN_sel" value ="3"></option>
            <option name="fun_CLK_32K_sel" value ="4"></option>
            <option name="fun_PDM_DATA_sel" value ="5"></option>
            <option name="fun_DBG_DO_15_sel" value ="6"></option>
            <option name="fun_wcn_uart_rts_sel" value ="9"></option>
            <option name="fun_wcn_pcmdout_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYIN_0_cfg" protect="rw">
     <bits name="pad_KEYIN_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYIN_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYIN_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYIN_0 PUll up</comment>
     </bits>
     <bits name="pad_KEYIN_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYIN_0 PUll down</comment>
     </bits>
     <bits name="pad_KEYIN_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYIN_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYIN_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYIN_0 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYIN_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYIN_0 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYIN_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYIN_0 pin output value. </comment>
     </bits>
     <bits name="pad_KEYIN_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYIN_0 select</comment>
     <options>
            <option name="fun_KEYIN_0_sel" value ="0"></option>
            <option name="fun_GPIO_34_sel" value ="1"></option>
            <option name="fun_SPI2_CLK_sel" value ="4"></option>
            <option name="fun_PULP_TCK_sel" value ="6"></option>
            <option name="fun_wcn_m_symbol_tx_0_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_tx_0_sel" value ="10"></option>
            <option name="fun_wcn_rf_apc_out_0_sel" value ="11"></option>
            <option name="fun_wcn_rf_apc_in_0_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYIN_1_cfg" protect="rw">
     <bits name="pad_KEYIN_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYIN_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYIN_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYIN_1 PUll up</comment>
     </bits>
     <bits name="pad_KEYIN_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYIN_1 PUll down</comment>
     </bits>
     <bits name="pad_KEYIN_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYIN_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYIN_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYIN_1 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYIN_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYIN_1 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYIN_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYIN_1 pin output value. </comment>
     </bits>
     <bits name="pad_KEYIN_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYIN_1 select</comment>
     <options>
            <option name="fun_KEYIN_1_sel" value ="0"></option>
            <option name="fun_GPIO_35_sel" value ="1"></option>
            <option name="fun_SPI2_CS_0_sel" value ="4"></option>
            <option name="fun_PULP_TRSTN_sel" value ="6"></option>
            <option name="fun_wcn_m_symbol_tx_1_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_tx_1_sel" value ="10"></option>
            <option name="fun_wcn_rf_apc_out_1_sel" value ="11"></option>
            <option name="fun_wcn_rf_apc_in_1_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYIN_2_cfg" protect="rw">
     <bits name="pad_KEYIN_2_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYIN_2 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYIN_2_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYIN_2 PUll up</comment>
     </bits>
     <bits name="pad_KEYIN_2_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYIN_2 PUll down</comment>
     </bits>
     <bits name="pad_KEYIN_2_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYIN_2 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYIN_2_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYIN_2 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYIN_2_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYIN_2 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYIN_2_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYIN_2 pin output value. </comment>
     </bits>
     <bits name="pad_KEYIN_2_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYIN_2 select</comment>
     <options>
            <option name="fun_KEYIN_2_sel" value ="0"></option>
            <option name="fun_GPIO_36_sel" value ="1"></option>
            <option name="fun_SPI2_DI_0_sel" value ="4"></option>
            <option name="fun_SEGOUT_12_sel" value ="5"></option>
            <option name="fun_PULP_TMS_sel" value ="6"></option>
            <option name="fun_wcn_m_symbol_tx_2_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_tx_2_sel" value ="10"></option>
            <option name="fun_wcn_rf_apc_out_2_sel" value ="11"></option>
            <option name="fun_wcn_rf_apc_in_2_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYIN_3_cfg" protect="rw">
     <bits name="pad_KEYIN_3_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYIN_3 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYIN_3_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYIN_3 PUll up</comment>
     </bits>
     <bits name="pad_KEYIN_3_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYIN_3 PUll down</comment>
     </bits>
     <bits name="pad_KEYIN_3_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYIN_3 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYIN_3_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYIN_3 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYIN_3_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYIN_3 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYIN_3_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYIN_3 pin output value. </comment>
     </bits>
     <bits name="pad_KEYIN_3_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYIN_3 select</comment>
     <options>
            <option name="fun_KEYIN_3_sel" value ="0"></option>
            <option name="fun_GPIO_37_sel" value ="1"></option>
            <option name="fun_UART3_RXD_sel" value ="2"></option>
            <option name="fun_XTAL26M_REQ_sel" value ="3"></option>
            <option name="fun_SEGOUT_13_sel" value ="5"></option>
            <option name="fun_PULP_TDI_sel" value ="6"></option>
            <option name="fun_wcn_m_symbol_flag_tx_0_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_flag_tx_0_sel" value ="10"></option>
            <option name="fun_wcn_rf_agc_index_out_0_sel" value ="11"></option>
            <option name="fun_wcn_rf_agc_index_in_0_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYIN_4_cfg" protect="rw">
     <bits name="pad_KEYIN_4_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYIN_4 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYIN_4_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYIN_4 PUll up</comment>
     </bits>
     <bits name="pad_KEYIN_4_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYIN_4 PUll down</comment>
     </bits>
     <bits name="pad_KEYIN_4_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYIN_4 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYIN_4_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYIN_4 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYIN_4_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYIN_4 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYIN_4_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYIN_4 pin output value. </comment>
     </bits>
     <bits name="pad_KEYIN_4_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYIN_4 select</comment>
     <options>
            <option name="fun_KEYIN_4_sel" value ="0"></option>
            <option name="fun_GPIO_38_sel" value ="1"></option>
            <option name="fun_UART3_TXD_sel" value ="2"></option>
            <option name="fun_CLK_32K_sel" value ="3"></option>
            <option name="fun_SEGOUT_14_sel" value ="5"></option>
            <option name="fun_PULP_TDO_sel" value ="6"></option>
            <option name="fun_wcn_m_symbol_flag_tx_1_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_flag_tx_1_sel" value ="10"></option>
            <option name="fun_wcn_rf_agc_index_out_1_sel" value ="11"></option>
            <option name="fun_wcn_rf_agc_index_in_1_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYOUT_0_cfg" protect="rw">
     <bits name="pad_KEYOUT_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYOUT_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYOUT_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYOUT_0 PUll up</comment>
     </bits>
     <bits name="pad_KEYOUT_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYOUT_0 PUll down</comment>
     </bits>
     <bits name="pad_KEYOUT_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYOUT_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYOUT_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYOUT_0 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYOUT_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYOUT_0 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYOUT_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYOUT_0 pin output value. </comment>
     </bits>
     <bits name="pad_KEYOUT_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYOUT_0 select</comment>
     <options>
            <option name="fun_KEYOUT_0_sel" value ="0"></option>
            <option name="fun_GPIO_39_sel" value ="1"></option>
            <option name="fun_TCO_0_sel" value ="3"></option>
            <option name="fun_RF_RXD_sel" value ="6"></option>
            <option name="fun_wcn_m_symbol_flag_tx_2_sel" value ="9"></option>
            <option name="fun_wcn_s_symbol_flag_tx_2_sel" value ="10"></option>
            <option name="fun_wcn_rf_agc_index_out_2_sel" value ="11"></option>
            <option name="fun_wcn_rf_agc_index_in_2_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYOUT_1_cfg" protect="rw">
     <bits name="pad_KEYOUT_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYOUT_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYOUT_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYOUT_1 PUll up</comment>
     </bits>
     <bits name="pad_KEYOUT_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYOUT_1 PUll down</comment>
     </bits>
     <bits name="pad_KEYOUT_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYOUT_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYOUT_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYOUT_1 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYOUT_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYOUT_1 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYOUT_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYOUT_1 pin output value. </comment>
     </bits>
     <bits name="pad_KEYOUT_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYOUT_1 select</comment>
     <options>
            <option name="fun_KEYOUT_1_sel" value ="0"></option>
            <option name="fun_GPIO_40_sel" value ="1"></option>
            <option name="fun_PWT_0_sel" value ="3"></option>
            <option name="fun_RF_TXD_sel" value ="6"></option>
            <option name="fun_wcn_m_bb_txon_sel" value ="9"></option>
            <option name="fun_wcn_s_bb_txon_sel" value ="10"></option>
            <option name="fun_wcn_rf_agc_index_out_3_sel" value ="11"></option>
            <option name="fun_wcn_rf_agc_index_in_3_sel" value ="12"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYOUT_2_cfg" protect="rw">
     <bits name="pad_KEYOUT_2_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYOUT_2 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYOUT_2_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYOUT_2 PUll up</comment>
     </bits>
     <bits name="pad_KEYOUT_2_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYOUT_2 PUll down</comment>
     </bits>
     <bits name="pad_KEYOUT_2_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYOUT_2 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYOUT_2_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYOUT_2 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYOUT_2_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYOUT_2 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYOUT_2_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYOUT_2 pin output value. </comment>
     </bits>
     <bits name="pad_KEYOUT_2_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYOUT_2 select</comment>
     <options>
            <option name="fun_KEYOUT_2_sel" value ="0"></option>
            <option name="fun_GPIO_41_sel" value ="1"></option>
            <option name="fun_SEGOUT_15_sel" value ="5"></option>
            <option name="fun_HST_CLK_sel" value ="6"></option>
            <option name="fun_wcn_m_bb_rxon_sel" value ="9"></option>
            <option name="fun_wcn_s_bb_rxon_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYOUT_3_cfg" protect="rw">
     <bits name="pad_KEYOUT_3_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYOUT_3 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYOUT_3_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYOUT_3 PUll up</comment>
     </bits>
     <bits name="pad_KEYOUT_3_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYOUT_3 PUll down</comment>
     </bits>
     <bits name="pad_KEYOUT_3_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYOUT_3 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYOUT_3_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYOUT_3 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYOUT_3_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYOUT_3 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYOUT_3_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYOUT_3 pin output value. </comment>
     </bits>
     <bits name="pad_KEYOUT_3_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYOUT_3 select</comment>
     <options>
            <option name="fun_KEYOUT_3_sel" value ="0"></option>
            <option name="fun_GPIO_42_sel" value ="1"></option>
            <option name="fun_UART3_CTS_sel" value ="2"></option>
            <option name="fun_SPI2_CS_1_sel" value ="4"></option>
            <option name="fun_SEGOUT_16_sel" value ="5"></option>
            <option name="fun_DBG_TRIG_sel" value ="6"></option>
            <option name="fun_wcn_m_edr2_sel" value ="9"></option>
            <option name="fun_wcn_s_edr2_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_KEYOUT_4_cfg" protect="rw">
     <bits name="pad_KEYOUT_4_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>KEYOUT_4 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_KEYOUT_4_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>KEYOUT_4 PUll up</comment>
     </bits>
     <bits name="pad_KEYOUT_4_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>KEYOUT_4 PUll down</comment>
     </bits>
     <bits name="pad_KEYOUT_4_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>KEYOUT_4 force enable for outoen. </comment>
     </bits>
     <bits name="pad_KEYOUT_4_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>KEYOUT_4 force outoen value. </comment>
     </bits>
     <bits name="pad_KEYOUT_4_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>KEYOUT_4 force output value for output. </comment>
     </bits>
     <bits name="pad_KEYOUT_4_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>KEYOUT_4 pin output value. </comment>
     </bits>
     <bits name="pad_KEYOUT_4_sel" pos="3:0" access="rw" rst="0"> 
         <comment>KEYOUT_4 select</comment>
     <options>
            <option name="fun_KEYOUT_4_sel" value ="0"></option>
            <option name="fun_GPIO_43_sel" value ="1"></option>
            <option name="fun_UART3_RTS_sel" value ="2"></option>
            <option name="fun_SPI2_DI_1_sel" value ="4"></option>
            <option name="fun_SEGOUT_17_sel" value ="5"></option>
            <option name="fun_DBG_CLK_sel" value ="6"></option>
            <option name="fun_wcn_m_edr3_sel" value ="9"></option>
            <option name="fun_wcn_s_edr3_sel" value ="10"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_HST_RXD_cfg" protect="rw">
     <bits name="pad_HST_RXD_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>HST_RXD force enable for pu/pd </comment>
     </bits>
     <bits name="pad_HST_RXD_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>HST_RXD PUll up</comment>
     </bits>
     <bits name="pad_HST_RXD_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>HST_RXD PUll down</comment>
     </bits>
     <bits name="pad_HST_RXD_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>HST_RXD force enable for outoen. </comment>
     </bits>
     <bits name="pad_HST_RXD_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>HST_RXD force outoen value. </comment>
     </bits>
     <bits name="pad_HST_RXD_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>HST_RXD force output value for output. </comment>
     </bits>
     <bits name="pad_HST_RXD_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>HST_RXD pin output value. </comment>
     </bits>
     <bits name="pad_HST_RXD_sel" pos="3:0" access="rw" rst="0"> 
         <comment>HST_RXD select</comment>
     <options>
            <option name="fun_HST_RXD_sel" value ="0"></option>
            <option name="fun_GPIO_44_sel" value ="1"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_HST_TXD_cfg" protect="rw">
     <bits name="pad_HST_TXD_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>HST_TXD force enable for pu/pd </comment>
     </bits>
     <bits name="pad_HST_TXD_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>HST_TXD PUll up</comment>
     </bits>
     <bits name="pad_HST_TXD_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>HST_TXD PUll down</comment>
     </bits>
     <bits name="pad_HST_TXD_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>HST_TXD force enable for outoen. </comment>
     </bits>
     <bits name="pad_HST_TXD_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>HST_TXD force outoen value. </comment>
     </bits>
     <bits name="pad_HST_TXD_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>HST_TXD force output value for output. </comment>
     </bits>
     <bits name="pad_HST_TXD_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>HST_TXD pin output value. </comment>
     </bits>
     <bits name="pad_HST_TXD_sel" pos="3:0" access="rw" rst="0"> 
         <comment>HST_TXD select</comment>
     <options>
            <option name="fun_HST_TXD_sel" value ="0"></option>
            <option name="fun_GPIO_45_sel" value ="1"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SIM_CLK_0_cfg" protect="rw">
     <bits name="pad_SIM_CLK_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SIM_CLK_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SIM_CLK_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SIM_CLK_0 PUll up</comment>
     </bits>
     <bits name="pad_SIM_CLK_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SIM_CLK_0 PUll down</comment>
     </bits>
     <bits name="pad_SIM_CLK_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SIM_CLK_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SIM_CLK_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SIM_CLK_0 force outoen value. </comment>
     </bits>
     <bits name="pad_SIM_CLK_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SIM_CLK_0 force output value for output. </comment>
     </bits>
     <bits name="pad_SIM_CLK_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SIM_CLK_0 pin output value. </comment>
     </bits>
     <bits name="pad_SIM_CLK_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SIM_CLK_0 select</comment>
     <options>
            <option name="fun_SIM_CLK_0_sel" value ="0"></option>
            <option name="fun_GPIO_46_sel" value ="1"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SIM_RST_0_cfg" protect="rw">
     <bits name="pad_SIM_RST_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SIM_RST_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SIM_RST_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SIM_RST_0 PUll up</comment>
     </bits>
     <bits name="pad_SIM_RST_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SIM_RST_0 PUll down</comment>
     </bits>
     <bits name="pad_SIM_RST_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SIM_RST_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SIM_RST_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SIM_RST_0 force outoen value. </comment>
     </bits>
     <bits name="pad_SIM_RST_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SIM_RST_0 force output value for output. </comment>
     </bits>
     <bits name="pad_SIM_RST_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SIM_RST_0 pin output value. </comment>
     </bits>
     <bits name="pad_SIM_RST_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SIM_RST_0 select</comment>
     <options>
            <option name="fun_SIM_RST_0_sel" value ="0"></option>
            <option name="fun_GPIO_47_sel" value ="1"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SIM_DIO_0_cfg" protect="rw">
     <bits name="pad_SIM_DIO_0_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SIM_DIO_0 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SIM_DIO_0_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SIM_DIO_0 PUll up</comment>
     </bits>
     <bits name="pad_SIM_DIO_0_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SIM_DIO_0 PUll down</comment>
     </bits>
     <bits name="pad_SIM_DIO_0_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SIM_DIO_0 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SIM_DIO_0_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SIM_DIO_0 force outoen value. </comment>
     </bits>
     <bits name="pad_SIM_DIO_0_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SIM_DIO_0 force output value for output. </comment>
     </bits>
     <bits name="pad_SIM_DIO_0_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SIM_DIO_0 pin output value. </comment>
     </bits>
     <bits name="pad_SIM_DIO_0_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SIM_DIO_0 select</comment>
     <options>
            <option name="fun_SIM_DIO_0_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SIM_CLK_1_cfg" protect="rw">
     <bits name="pad_SIM_CLK_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SIM_CLK_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SIM_CLK_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SIM_CLK_1 PUll up</comment>
     </bits>
     <bits name="pad_SIM_CLK_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SIM_CLK_1 PUll down</comment>
     </bits>
     <bits name="pad_SIM_CLK_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SIM_CLK_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SIM_CLK_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SIM_CLK_1 force outoen value. </comment>
     </bits>
     <bits name="pad_SIM_CLK_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SIM_CLK_1 force output value for output. </comment>
     </bits>
     <bits name="pad_SIM_CLK_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SIM_CLK_1 pin output value. </comment>
     </bits>
     <bits name="pad_SIM_CLK_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SIM_CLK_1 select</comment>
     <options>
            <option name="fun_SIM_CLK_1_sel" value ="0"></option>
            <option name="fun_GPIO_48_sel" value ="1"></option>
            <option name="fun_UART1_RXD_sel" value ="2"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SIM_RST_1_cfg" protect="rw">
     <bits name="pad_SIM_RST_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SIM_RST_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SIM_RST_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SIM_RST_1 PUll up</comment>
     </bits>
     <bits name="pad_SIM_RST_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SIM_RST_1 PUll down</comment>
     </bits>
     <bits name="pad_SIM_RST_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SIM_RST_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SIM_RST_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SIM_RST_1 force outoen value. </comment>
     </bits>
     <bits name="pad_SIM_RST_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SIM_RST_1 force output value for output. </comment>
     </bits>
     <bits name="pad_SIM_RST_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SIM_RST_1 pin output value. </comment>
     </bits>
     <bits name="pad_SIM_RST_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SIM_RST_1 select</comment>
     <options>
            <option name="fun_SIM_RST_1_sel" value ="0"></option>
            <option name="fun_GPIO_49_sel" value ="1"></option>
            <option name="fun_UART1_TXD_sel" value ="2"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
  <reg name="pad_SIM_DIO_1_cfg" protect="rw">
     <bits name="pad_SIM_DIO_1_pull_frc" pos="14" access="rw" rst="0x0"> 
         <comment>SIM_DIO_1 force enable for pu/pd </comment>
     </bits>
     <bits name="pad_SIM_DIO_1_pull_dn" pos="13" access="rw" rst="0x0"> 
         <comment>SIM_DIO_1 PUll up</comment>
     </bits>
     <bits name="pad_SIM_DIO_1_pull_up" pos="12" access="rw" rst="0x0"> 
         <comment>SIM_DIO_1 PUll down</comment>
     </bits>
     <bits name="pad_SIM_DIO_1_oen_frc" pos="9" access="rw" rst="0x0"> 
         <comment>SIM_DIO_1 force enable for outoen. </comment>
     </bits>
     <bits name="pad_SIM_DIO_1_oen_reg" pos="8" access="rw" rst="0x0"> 
         <comment>SIM_DIO_1 force outoen value. </comment>
     </bits>
     <bits name="pad_SIM_DIO_1_out_frc" pos="5" access="rw" rst="0x0"> 
         <comment>SIM_DIO_1 force output value for output. </comment>
     </bits>
     <bits name="pad_SIM_DIO_1_out_reg" pos="4" access="rw" rst="0x0"> 
         <comment>SIM_DIO_1 pin output value. </comment>
     </bits>
     <bits name="pad_SIM_DIO_1_sel" pos="3:0" access="rw" rst="0"> 
         <comment>SIM_DIO_1 select</comment>
     <options>
            <option name="fun_SIM_DIO_1_sel" value ="0"></option>
            <mask/><shift/><default/>
     </options>
     </bits>
  </reg>
   </module>
</archive>


<archive relative = "itlv.xml">

<include file="globals.xml"/>

<module name="itlv" category="Baseband">
  <reg name="command" protect="rw">
    <bits access="rw" name="nb_bits" pos="30:20" rst="0x0">
      <comment>Number of bits to be (De)Interleaved.</comment>
    </bits>

    <bits access="rw" name="burst_offset" pos="12:8" rst="0x0">
      <comment>This value gives the write offset (in number of bursts) to be
      added to a Burst Base address (ignored for Type 1b). For normal
      operation, this offset should be even (lsb will be ignored).</comment>
    </bits>

    <bits access="rw" name="itlv_type" pos="7:4" rst="0x0">
      <comment>Selects (de-)interleaving type.</comment>
            <options>
                <option name="TYPE_1A" value="0">
                    <comment>TCH/FS, TCH/EFS, FACCH/F, TCH/F2.4, TCH/AFS (speech, ratscch, sid_first)</comment>
                </option>
                <option name="TYPE_1B" value="1">
                    <comment>SACCH, TCH/AFS(sid_update), PDTCH(CS-1 to CS-4), BCCH, PCH, AGCH, PACCH, PBCCH, PAGCH, PPCH, PNCH, PTCCH/D</comment>
                </option>
                <option name="TYPE_1C" value="2">
                    <comment>FACCH/H</comment>
                </option>
                <option name="TYPE_2A" value="3">
                    <comment>TCH/HS and TCH/AHS</comment>
                </option>
                <option name="TYPE_2B" value="4">
                    <comment>TCH/HS and TCH/AHS</comment>
                </option>
                <option name="TYPE_3" value="5">
                    <comment>TCH/F14.4, TCH/F9.6, TCH/F4.8, TCH/H4.8, and TCH/H2.4</comment>
                </option>
                <default/>
                <mask/>
                <shift/>
            </options>
    </bits>

    <bits access="rw" name="int_mask" pos="3" rst="0x0">
      <comment>Sets the interrupt mask ('1': interruption enabled)</comment>
    </bits>

    <bits access="rw" name="ditlv_start" pos="1" rst="0x0">
      <comment>Starts the de-interleaving process.</comment>
    </bits>

    <bits access="rw" name="itlv_start" pos="0" rst="0x0">
      <comment>Starts the interleaving process.</comment>
    </bits>
  </reg>

  <reg name="status" protect="r">
    <bits access="r" name="busy" pos="0" rst="0x0">
      <comment>This bit is high when a (de-)interleaving process is ongoing. It
      stays high if the module is stalled during operation.</comment>
    </bits>
  </reg>

  <reg name="burst_base" protect="rw">
    <bits access="rw" name="burst_base" pos="BB_SRAM_ADDR_WIDTH+1:4" rst="0x0">
      <comment>This is the start address of the burst buffer in SRAM
      </comment>
    </bits>
  </reg>

  <reg name="frame_base" protect="rw">
    <bits access="rw" name="frame_base" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
      <comment>This is the start address of the frame buffer in
      SRAM.</comment>
    </bits>
  </reg>

  <reg name="int_status" protect="r">
    <bits access="r" name="it_status" pos="16" rst="0x0">
      <comment>This bit is the unmasked version of the IT_CAUSE bit.</comment>
    </bits>

    <bits access="r" name="it_cause" pos="0" rst="0x0">
      <comment>This bit is set when the ITLV module finishes an ongoing
      operation. It can be masked by setting ITLV_CMD(IT_MASK) to '1'.
      Resetting this bit is done by writing in IT_CLEAR register. IT_CAUSE is
      the image of the ITLV_DONE_H interrupt line to the CPU. </comment>
    </bits>
  </reg>

  <reg name="int_clear" protect="w">
    <bits access="w" name="it_clear" pos="0" rst="0x0">
      <comment>Setting this bit to '1' resets the Interleaver's
      interrupt.</comment>
    </bits>
  </reg>
</module>

</archive>

<archive relative = "keypad.xml">
<module name="keypad" category="Periph">
  <var name="KEY_NB" value="64">
    <comment> Number of key in the keypad
    </comment>
  </var>
  <var name="LOW_KEY_NB" value="32">
    <comment> Number of key in the low data register 
    </comment>
  </var>
  <var name="HIGH_KEY_NB" value="32">
    <comment> Number of key in the high data register
    </comment>
  </var>

  <reg protect="r" name="KP_DATA_L">
    <bits access="r" name="KP_DATA_L" pos="31:0" rst="0">
      <comment>For keys in column Idx_KeyOut(from 0 to 3) and in line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_L(Idx_KeyOut*8+Idx_KeyIn) :<br />0 = Released<br />1 = Pressed
      </comment>
      <options>
        <mask/>
        <shift/>
      </options>  
    </bits>

  </reg>

  <reg protect="r" name="KP_DATA_H">
    <bits access="r" name="KP_DATA_H" pos="31:0" rst="0">
      <comment>For keys in column Idx_KeyOut(from 4 to 7) and line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_H(Idx_KeyIn*8-32+Idx_KeyIn):<br />0 = Released<br />1 = Pressed
      </comment>
      <options>
        <mask/>
        <shift/>
      </options>  
    </bits>

  </reg>

  <reg protect="r" name="KP_STATUS">

    <bits access="r" name="KEYIN_STATUS" pos="7:0" rst="0x08">
      <comment>For keys in lines status <br />0 = Released<br />1 = Pressed
      </comment>
      <options>
        <mask/>
        <shift/>
      </options>  
  </bits>

    <bits access="r" name="KP_ON" pos="31" rst="0">
      <comment>Indicate Key ON pressing status :<br />0 = Release<br />1 = Pressed
      </comment>
      <options><default/><mask/><shift/></options>
    </bits>

  </reg>

  
  <reg protect="rw" name="KP_CTRL">
    <bits access="rw" name="KP_En" pos="0" rst="0">
        <comment>This bit enables key detection. If this bit is '0', the key detection function 
            is disabled. Key ON is an exception, it can be still detected and generate key interrupt
            even if KP_En = '0', however in this case, the debouncing time configuration in key
            control register is ignored and the key ON state is considerred to be stable if it keeps
            same in consecutive 2 cycles of 16KHz clock.<br />
        <br />0 = keypad disable<br />1 = keypad enable  
      </comment>
    </bits>
   
    <bits access="rw" name="KP_DBN_Time" pos="9:2" rst="0">
      <comment>De-bounce time = (KP_DBN_TIME + 1) * SCAN_TIME, SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*0.3125*6=15 ms. The maximum debounce time is 480 ms.
      </comment>
    </bits>

   <bits access="rw" name="KP_ITV_Time" pos="15:10" rst="0">
      <comment>Configure interval of generating an IRQ if one key or several keys are pressed long time. Interval of IRQ generation = (KP_ITV_Time + 1) * (KP_DBN_TIME + 1) * SCAN_TIME. SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_ITV_TIME = 7, KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*(7+1)*0.3125*6=120 ms. 
      </comment>
    </bits>
    
    <bits access="rw" name="KP_IN_MASK" pos="23:16" rst="0xff">
        <comment>each bit masks one input lines.<br />
            '1' = enabled <br /> '0' = disabled
            
            <br/>The Key In pins 0 to 5 are muxed with the boot mode pins, latched during Reset.
                <br/> Key_In 0: BOOT_MODE_NO_AUTO_PU.
                <br/> Key_In 1: BOOT_MODE_FORCE_MONITOR.
                <br/> Key_In 2: BOOT_MODE_UART_MONITOR_ENABLE.
                <br/> Key_In 3: BOOT_MODE_USB_MONITOR_DISABLE.
                <br/> Key_In 4: reserved

        </comment>
    </bits>

    <bits access="rw" name="KP_OUT_MASK" pos="31:24" rst="0xff">
        <comment>each bit masks one output lines.<br />
            '1' = enabled <br /> '0' = disabled </comment>
    </bits>

  </reg>

  <reg protect="rw" name="KP_IRQ_MASK">
    <bits access="rw" name="KP_EVT0_IRQ_MASK" pos="0" rst="0">
      <comment>This bit mask keypad irq generated by event0 (key press or key release event, not including all keys release event which is event1). 
        <br />0 = keypad event irq disable<br />1 = keypad event irq enable  
      </comment>
    </bits>
    
    <bits access="rw" name="KP_EVT1_IRQ_MASK" pos="1" rst="0">
      <comment>This bit mask keypad irq generated by event1 (all keys release event). 
        <br />0 = keypad event irq disable<br />1 = keypad event irq enable  
      </comment>
    </bits>
    
    <bits access="rw" name="KP_ITV_IRQ_MASK" pos="2" rst="0">
      <comment>This bit mask keypad irq generated by key pressed long time (generated each interval configured in KP_ITV_Time. 
        <br />0 = keypad interval irq disable<br />1 = keypad interval irq enable  
      </comment>
    </bits>

  </reg>

  <reg protect="r" name="KP_IRQ_CAUSE">
    <bits access="r" name="KP_EVT0_IRQ_CAUSE" pos="0" rst="0">
      <comment>keypad event0(key press or key release event, not including all keys release which is event1) IRQ cause. 
      </comment>
    </bits>

    <bits access="r" name="KP_EVT1_IRQ_CAUSE" pos="1" rst="0">
      <comment>keypad event1(all keys release event) IRQ cause. 
      </comment>
    </bits>

    <bits access="r" name="KP_ITV_IRQ_CAUSE" pos="2" rst="0">
      <comment>keypad interval irq cause. 
      </comment>
    </bits>
    
    <bits access="r" name="KP_EVT0_IRQ_STATUS" pos="16" rst="0">
      <comment>keypad event0(key press or key release event, not including all keys release which is event1) irq status. 
      </comment>
    </bits>

    <bits access="r" name="KP_EVT1_IRQ_STATUS" pos="17" rst="0">
      <comment>keypad event1(all keys release event) irq status. 
      </comment>
    </bits>
  
    <bits access="r" name="KP_ITV_IRQ_STATUS" pos="18" rst="0">
      <comment>keypad interval irq status. 
      </comment>
    </bits>

  </reg>
  
  <reg protect="rw" name="KP_IRQ_CLR">
    <bits access="c" name="KP_IRQ_CLR" pos="0" rst="0">
      <comment>Write '1' to this bit clears key IRQ. </comment>
    </bits>
  </reg>

</module>
</archive>
<archive relative = "lps.xml">

<module name="lps" category="Modem">

    
    
	<var name="LP_FRAC_NB_BITS" value="16"/>
	<var name="LP_COUNT_INT_NB_BITS" value="19"/>
	<var name="LP_COUNT_NB_BITS" value="LP_COUNT_INT_NB_BITS + LP_FRAC_NB_BITS"/>
	<var name="LP_RATE_INT_NB_BITS" value="12"/>
	<var name="LP_RATE_NB_BITS" value="LP_RATE_INT_NB_BITS + LP_FRAC_NB_BITS"/>
	<var name="SYS_COUNT_NB_BITS" value="29"/>
	<var name="FRAME_COUNT_NB_BITS" value="32"/>
    
	<var name="PU_COUNT_NB_BITS" value="12"/>
    
    
    <reg name="LPS_SF_Ctrl" protect="rw">
        <bits name="LPS_SF_Enable" pos="0" access="rw" rst="0">
            <comment>Lps Skip Frame Enable.
                <br/>When enabled the frame interrupt are masked until the programmed number of frames are elapsed.
                <br/>This is done by masking the frame interrupt line from the regular TCU counter, and counting the frames. Also when activating the LowPower SkipFrame the frame counter is tranfered to the low power counter that will update it based on the 32kHz Clock.
            </comment>
        </bits>
        <bits name="LPS_SF_LowPower" pos="5:4" access="rw" rst="0">
            <comment>Controls the Lps Low Power Counters (counters at 32kHz) usage.
            </comment>
            <options>
                <option name="Stop" value="0"><comment>Disable the Low Power Counters.</comment></option>
                <option name="SkipFrame" value="1"><comment>The Low Power Counters are started in Skip Frame Mode. In this mode the Low Power Counter are used to maintain the Time base, The Skip Frame Must be enabled as this is the Low Power extention of the Skip Frame feature.</comment></option>
                <option name="Calib" value="3"><comment>Start the calibration. The Low Power Counters are used to Calibrate the 32kHz clock against the System Clock, The Calibration is required to compensate from temperature variation. Note that the Skip Frame can also be enabled during calibration (but not with low power).</comment></option>
                <mask/>
                <shift/>
                <default/>
            </options>
        </bits>
        <bits name="LPS_SF_Wakeup0" pos="8" access="rw" rst="0">
            <comment>Enable fake Fint used with wakeupNumber=0. </comment>
            <options>
                <option name="Disabled" value="0"/>
                <option name="Enabled" value="1"/>
            </options>
        </bits>
        <bits name="LPS_SF_Wakeup0_cfg" pos="9" access="rw" rst="0">
            <comment>Enable fake Fint when sys_sf_frame_count>=cfg_sf_frame. 
                <br/>Default sys_sf_frame_count>cfg_sf_frame.
            </comment>
            <options>
                <option name="0" value="0"/>
                <option name="1" value="1"/>
            </options>
        </bits>
    </reg>
    <reg name="LPS_SF_Status" protect="rw">
        <bits name="LPS_SF_Ready" pos="0" access="r" rst="1">
            <comment>Lps Skip Frame Ready, status of the state machines to keep valid state between system clock and 32Khz clock.
                <br/>Must read as '1' before entering Low Power Skip Frame or Calibration mode.
            </comment>
        </bits>
        <bits name="LPS_SF_SlowRunning" pos="4" access="r" rst="0">
            <comment>'1' when Lps Skip Frame Low Power Counters are Running.
                <br/>When entering Low Power Skip Frame, the counters are not immediately started, they wait for the nextFrame interrupt. Reading this status allow to know if the counters are running, and the System Clock can be safely disabled.
            </comment>
        </bits>
        <bits name="LPS_SF_CalibrationDone" pos="8" access="r" rst="0">
            <comment>'1' when the Lps Skip Frame Calibration is Done.
            </comment>
        </bits>
        <bits name="LPS_SF_PU_Reached" pos="12" access="r" rst="0">
            <comment>'1' when the Lps Skip Frame Power-up sequence frame is reached.
            </comment>
        </bits>
        <bits name="LPS_SF_TCU_Restart" pos="16" access="r" rst="0">
            <comment>'1' when tcu counter is restarted.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_SF_Frames" protect="rw">
        <bits name="LPS_SF_Frame" pos="FRAME_COUNT_NB_BITS-1:0" access="rw" rst="0">
            <comment>Number of frames to Skip.
                <br/>If the power up sequence is enabled, frames are skipped until both this number is reached and the powerup sequence has finished.
                <br/>Note: The power up sequence must be <b>Done</b> before the the frame LPS_SF_Frame ends.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_SF_PU_Frames" protect="rw">
        <bits name="LPS_SF_PU_Frame" pos="FRAME_COUNT_NB_BITS-1:0" access="rw" rst="0">
            <comment>Number of frames before activating the Power-up sequence.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_SF_Restart_Time" protect="rw">
        <bits name="LPS_SF_Restart_Time" pos="LP_COUNT_INT_NB_BITS-1:0" access="rw" rst="0">
            <comment>For LowPower SkipFrame mode: Value to restart TCU (and frame interrupt generation) on the system clock counter after a low power phase.
                <br/>For Calibration mode: number of 32k cycles for the calibration.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_SF_Frame_Period" protect="rw">
        <bits name="LPS_SF_Frame_Period" pos="LP_COUNT_INT_NB_BITS-1:0" access="rw" rst="0">
            <comment>Value of the frame period in system clock count.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_SF_Rate" protect="rw">
        <comment>The rate is the number of System Clocks per 32kHz Clocks.
        </comment>
        <bits name="LPS_SF_Rate_Int" pos="LP_RATE_NB_BITS-1:LP_FRAC_NB_BITS" access="rw" rst="0">
            <comment>Integer part of the rate.
            </comment>
        </bits>
        <bits name="LPS_SF_Rate_Frac" pos="LP_FRAC_NB_BITS-1:0" access="rw" rst="0">
            <comment>Fractional part of the rate.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_SF_Elapsed_Frames" protect="rw">
        <bits name="LPS_SF_Elapsed_Frames" pos="FRAME_COUNT_NB_BITS-1:0" access="r" rst="0">
            <comment>Current number of elapsed frames.
                <br/>Valid when Skip Frame is Enabled.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_SF_Sys_Count" protect="rw">
        <bits name="LPS_SF_Sys_Count" pos="SYS_COUNT_NB_BITS-1:0" access="r" rst="0">
            <comment>Value of the system clock counter at the end of calibration (when CalibrationDone is '1' in LPS_SF_Status register).
                <br/>The hardware behind it is reused during other operation, reading that register at any other time will return an undefined value.
            </comment>
        </bits>
    </reg>
    <reg name="LPS_IRQ" protect="rw">
        <bits name="LPS_IRQ_Calibration_Done_Cause" pos="0" access="rc" rst="0">
            <comment>1 when the IRQ was triggered because the calibration is done.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bits name="LPS_IRQ_Slow_Running_Cause" pos="1" access="rc" rst="0">
            <comment>1 when the IRQ was triggered because the Slow Counter started.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bits name="LPS_IRQ_PU_Reached_Cause" pos="2" access="rc" rst="0">
            <comment>1 when the IRQ was triggered because the Power-Up frame was reached.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bits name="LPS_IRQ_TCU_Restart_Cause" pos="3" access="rc" rst="0">
            <comment>1 when the IRQ was triggered because the tcu counter was restarted.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bitgroup name="LPS_PU_IRQ_Cause">
            <entry ref="LPS_IRQ_Calibration_Done_Cause"/>
            <entry ref="LPS_IRQ_Slow_Running_Cause"/>
            <entry ref="LPS_IRQ_PU_Reached_Cause"/>
            <entry ref="LPS_IRQ_TCU_Restart_Cause"/>
        </bitgroup>

        <bits name="LPS_IRQ_Calibration_Done_Status" pos="16" access="rc" rst="0">
            <comment>1 when the calibration is done.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bits name="LPS_IRQ_Slow_Running_Status" pos="17" access="rc" rst="0">
            <comment>1 when the Slow Counter started.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bits name="LPS_IRQ_PU_Reached_Status" pos="18" access="rc" rst="0">
            <comment>1 when the Power-Up frame was reached.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bits name="LPS_IRQ_TCU_Restart_Status" pos="19" access="rc" rst="0">
            <comment>1 when the tcu counter was restarted.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bitgroup name="LPS_PU_IRQ_Status">
            <entry ref="LPS_IRQ_Calibration_Done_Status"/>
            <entry ref="LPS_IRQ_Slow_Running_Status"/>
            <entry ref="LPS_IRQ_PU_Reached_Status"/>
            <entry ref="LPS_IRQ_TCU_Restart_Status"/>
        </bitgroup>
    </reg>
    <reg name="LPS_IRQ_Mask" protect="rw">
        <bits name="LPS_IRQ_Calibration_Done_Mask" pos="0" access="rw" rst="0">
            <comment>when 1 the LPS_IRQ_Calibration_Done is enabled.
            </comment>
        </bits>
        <bits name="LPS_IRQ_Slow_Running_Mask" pos="1" access="rw" rst="0">
            <comment>when 1 the LPS_IRQ_Slow_Running is enabled.
            </comment>
        </bits>
        <bits name="LPS_IRQ_PU_Reached_Mask" pos="2" access="rw" rst="0">
            <comment>when 1 the LPS_IRQ_PU_Reached is enabled.
            </comment>
        </bits>
        <bits name="LPS_IRQ_TCU_Restart_Mask" pos="3" access="rw" rst="0">
            <comment>when 1 the LPS_IRQ_TCU_Restart is enabled.
            </comment>
        </bits>
        <bitgroup name="LPS_IRQ_Mask">
            <entry ref="LPS_IRQ_Calibration_Done_Mask"/>
            <entry ref="LPS_IRQ_Slow_Running_Mask"/>
            <entry ref="LPS_IRQ_PU_Reached_Mask"/>
            <entry ref="LPS_IRQ_TCU_Restart_Mask"/>
        </bitgroup>
    </reg>

</module>

</archive>

<archive relative="lvds.xml">
  <module name="lvds" category="System">
    <reg protect="rw" name="dlhssb_en">
      <bits access="r" name="dlhssb_en_reserved_0" pos="31:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_dlhssb_en" pos="1:0" rst="0">
        <comment>
          2 dedicated enable for 2 DL HSSBs, bit0-lane0, bit1-lane1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ulhssb_en">
      <bits access="r" name="ulhssb_en_reserved_0" pos="31:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_ulhssb_en" pos="1:0" rst="0">
        <comment>
          2 dedicated enable for 2 UL HSSBs, bit0-lane0, bit1-lane1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dlfifo_clr">
      <bits access="r" name="dlfifo_clr_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_dlfifo_clr" pos="0:0" rst="0">
        <comment>
          DL FIFO reset and clear
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ulfifo_clr">
      <bits access="r" name="ulfifo_clr_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_ulfifo_clr" pos="0:0" rst="0">
        <comment>
          UL FIFO reset and clear
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="syncword10b_d">
      <bits access="r" name="syncword10b_d_reserved_0" pos="31:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_syncword10b_d" pos="7:0" rst="90">
        <comment>
          SYNC WORD for lvds dest
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="syncword10b_s">
      <bits access="r" name="syncword10b_s_reserved_0" pos="31:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_syncword10b_s" pos="7:0" rst="90">
        <comment>
          SYNC WORD for lvds src
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reverse_mode_en">
      <bits access="r" name="reverse_mode_en_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_reverse_mode_en" pos="0:0" rst="0">
        <comment>
          bit reverse enable
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="syncidx0">
      <bits access="r" name="syncidx0_reserved_0" pos="31:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_sync_idx0" pos="3:0" rst="0">
        <comment>
          bit offset index used in byte training stage for lane0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="syncidx1">
      <bits access="r" name="syncidx1_reserved_0" pos="31:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_sync_idx1" pos="3:0" rst="0">
        <comment>
          bit offset index used in byte training stage for lane1
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="rx_byte_training_ok">
      <bits access="r" name="rx_byte_training_ok_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_rx_byte_training_ok" pos="0:0" rst="0">
        <comment>
          Byte Training Done from SW
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rx_bit_training_ok">
      <bits access="r" name="rx_bit_training_ok_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_rx_bit_training_ok" pos="0:0" rst="0">
        <comment>
          Bit Training Done from SW
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ulrdy">
      <bits access="r" name="ulrdy_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_ul_rdy" pos="0:0" rst="0">
        <comment>
          data ready from DFE for ulfifo to lvds
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="len_payload">
      <bits access="r" name="len_payload_reserved_0" pos="31:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_len_payload" pos="9:0" rst="0">
        <comment>
          Payload max length for timeout check, 0-disabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="len_sync">
      <bits access="r" name="len_sync_reserved_0" pos="31:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_len_sync" pos="9:0" rst="0">
        <comment>
          Sync max length for timeout check, 0-disabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="fix_pattern">
      <bits access="r" name="fix_pattern_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_fix_pattern" pos="0:0" rst="0">
        <comment>
          LVDS tx fixed pattern instead of data from ulfifo
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pattern0">
      <bits access="rw" name="config_pattern0" pos="31:0" rst="4294967295">
        <comment>
          LVDS tx fixed pattern0[31:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pattern1">
      <bits access="rw" name="config_pattern1" pos="31:0" rst="0">
        <comment>
          LVDS tx fixed pattern1[31:0]
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="sample_width">
      <bits access="r" name="sample_width_reserved_0" pos="31:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_sample_width" pos="1:0" rst="0">
        <comment>
          [1]: 0-2 cycles per word , 1-1cycle per word for  LVDS_TX
[0]: 0-2 cycles per word , 1-1cycle per word for  LVDS_RX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="downsample">
      <bits access="r" name="downsample_reserved_0" pos="31:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_mode_mt_tx" pos="11:10" rst="0">
        <comment>
          0-mode0, 1-mode1, 2-mode2, 3-mode3 for tx
        </comment>
      </bits>
      <bits access="rw" name="config_mode_mt_rx" pos="9:8" rst="0">
        <comment>
          0-mode0, 1-mode1, 2-mode2, 3-mode3 for rx
        </comment>
      </bits>
      <bits access="rw" name="config_rate_cnt_tx" pos="7:6" rst="0">
        <comment>
          number of cycles to read from Fifo under MT mode for both tx
        </comment>
      </bits>
      <bits access="rw" name="config_rate_cnt_rx" pos="5:4" rst="0">
        <comment>
          number of cycles to read from Fifo under MT mode for both rx
        </comment>
      </bits>
      <bits access="rw" name="config_mt_en" pos="3:2" rst="0">
        <comment>
          [3]: 0- Non-MT mode, 1-MT enable for rx
[2]: 0- Non-MT mode, 1-MT enable for tx
        </comment>
      </bits>
      <bits access="rw" name="config_1x2x" pos="1:0" rst="0">
        <comment>
          [1]: 0-1x clock, 1-2x clock for rx
[0]: 0-1x clock, 1-2x clock for tx
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_bit_training_ok">
      <bits access="r" name="tx_bit_training_ok_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_tx_bit_training_ok" pos="0:0" rst="0">
        <comment>
          bit training Done for lvds tx
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_byte_training_ok">
      <bits access="r" name="tx_byte_training_ok_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_tx_byte_training_ok" pos="0:0" rst="0">
        <comment>
          byte training Done for lvds tx
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="latch_word0_0">
      <bits access="r" name="reg_latch_word0_0" pos="31:0" rst="0">
        <comment>
          report bit or byte training results word0 for lane0
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="latch_word0_1">
      <bits access="r" name="reg_latch_word0_1" pos="31:0" rst="0">
        <comment>
          report bit or byte training results word1 for lane0
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="latch_word1_0">
      <bits access="r" name="reg_latch_word1_0" pos="31:0" rst="0">
        <comment>
          report bit or byte training results word0 for lane1
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="latch_word1_1">
      <bits access="r" name="reg_latch_word1_1" pos="31:0" rst="0">
        <comment>
          report bit or byte training results word1 for lane1
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="state_monitor">
      <bits access="r" name="state_monitor_reserved_0" pos="31:24" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="dest_lane1_state" pos="23:21" rst="0">
        <comment>
          dest_lane1_state
        </comment>
      </bits>
      <bits access="r" name="dest_lane1_mstate" pos="20:18" rst="0">
        <comment>
          dest_lane1_mstate
        </comment>
      </bits>
      <bits access="r" name="dest_lane0_state" pos="17:15" rst="0">
        <comment>
          dest_lane0_state
        </comment>
      </bits>
      <bits access="r" name="dest_lane0_mstate" pos="14:12" rst="0">
        <comment>
          dest_lane0_mstate
        </comment>
      </bits>
      <bits access="r" name="src_lane1_state" pos="11:9" rst="0">
        <comment>
          src_lane1_state
        </comment>
      </bits>
      <bits access="r" name="src_lane1_mstate" pos="8:6" rst="0">
        <comment>
          src_lane1_mstate
        </comment>
      </bits>
      <bits access="r" name="src_lane0_state" pos="5:3" rst="0">
        <comment>
          src_lane0_state
        </comment>
      </bits>
      <bits access="r" name="src_lane0_mstate" pos="2:0" rst="0">
        <comment>
          src_lane0_mstate
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="rw" name="res_lvds_bb">
      <bits access="r" name="res_lvds_bb_reserved_0" pos="31:16" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_res_lvds_bb" pos="15:0" rst="0">
        <comment>
          reserved register for lvds bb
[15]: for RX, 1-use SW configure Sync index enable, 0-use HW anto sync detection
[14]: for TX, 1-use SW configure Sync index enable, 0-use HW anto sync detection
[13]: for RX, 1-use LFSR for BIST , 0-use normal data for RX
[12]: for TX, 1-use LFSR for BIST , 0-use normal data for TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clock_lvds">
      <bits access="r" name="clock_lvds_reserved_0" pos="31:16" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_clock_lvds" pos="15:0" rst="0">
        <comment>
          configure register for lvds used by IQMUX:
[15:12]: reserved
[11]: software reset for LVDS digital TX
[10]: software reset for LVDS digital RX
[9]:   software reset for LVDS analog TX
[8]:   software reset for LVDS analog RX
[7:3]:   reserved
[2]:   clock gating enable for MT clock divided from mt2lvds@61.44MHz clock.
[1]:   clock gating enable to LVDS digital rx related clocks
[0]:   clock gating enable to LVDS digital tx related clocks
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="latch">
      <bits access="r" name="latch_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_latch" pos="0:0" rst="0">
        <comment>
          Latch trigger for capturing 8 lvds received Bytes
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="header_config">
      <bits access="r" name="header_config_reserved_0" pos="31:11" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="config_header" pos="10:3" rst="255">
        <comment>
          header to be received or transmitted for LVDS
        </comment>
      </bits>
      <bits access="rw" name="config_header_len" pos="2:0" rst="0">
        <comment>
          number of header to be received or transmitted for LVDS
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rx_state_status">
      <bits access="r" name="rx_state_status_reserved_0" pos="31:6" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="lvds_rx_state_machine" pos="5:0" rst="0">
        <comment>
          mstate and fstate machine rerport for lvds_rx debug purpose
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="tx_state_status">
      <bits access="r" name="tx_state_status_reserved_0" pos="31:6" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="lvds_tx_state_machine" pos="5:0" rst="0">
        <comment>
          mstate and state machine rerport for lvds_tx debug purpose
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rx_pll_stable_time">
      <bits access="r" name="rx_pll_stable_time_reserved_0" pos="31:16" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_pll_stable_time" pos="15:0" rst="0">
        <comment>
          16 bit counter for LVDS_RX PLL stable time wait
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pll_stable_time">
      <bits access="r" name="tx_pll_stable_time_reserved_0" pos="31:16" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_pll_stable_time" pos="15:0" rst="0">
        <comment>
          16 bit counter for LVDS_TX PLL stable time wait
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="interrupt">
      <bits access="r" name="interrupt_reserved_0" pos="31:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="lvds_interrupt_raw" pos="1:1" rst="0">
        <comment>
          raw interrupt status, write 1 to clear
        </comment>
      </bits>
      <bits access="r" name="lvds_interrupt" pos="0:0" rst="0">
        <comment>
          interrupt status after masked raw interrupt status
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="interrupt_ctrl">
      <bits access="r" name="interrupt_ctrl_reserved_0" pos="31:5" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_interrupt_clear" pos="4:4" rst="0">
        <comment>
          write 1 to clear interrupt
        </comment>
      </bits>
      <bits access="rw" name="lvds_interrupt_source_sel" pos="3:1" rst="0">
        <comment>
          raw interrupt source select
        </comment>
      </bits>
      <bits access="rw" name="lvds_interrupt_mask" pos="0:0" rst="0">
        <comment>
          raw interrupt mask for latch done
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="lane0_bist_result">
      <bits access="r" name="lane0_bist_result_reserved_0" pos="31:17" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="bist_error_cnt_lane0" pos="16:1" rst="0">
        <comment>
          number of errors for lvds lane0 bist enabled period
        </comment>
      </bits>
      <bits access="r" name="bist_fail_ind_lane0" pos="0:0" rst="0">
        <comment>
          1: bist fail for lane0, 0: bist pass for lane0
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="lane1_bist_result">
      <bits access="r" name="lane1_bist_result_reserved_0" pos="31:17" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="bist_error_cnt_lane1" pos="16:1" rst="0">
        <comment>
          number of errors for lvds lane1 bist enabled period
        </comment>
      </bits>
      <bits access="r" name="bist_fail_ind_lane1" pos="0:0" rst="0">
        <comment>
          1: bist fail for lane1, 0: bist pass for lane0
        </comment>
      </bits>
    </reg>
    <hole size="544"/>
    <reg protect="rw" name="lvds_reset">
      <bits access="r" name="lvds_reset_reserved_0" pos="31:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_rstn" pos="1:1" rst="1">
        <comment>
          reset for LVDS RX path, active low
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_rstn" pos="0:0" rst="1">
        <comment>
          soft reset for LVDS TX path, active low
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_band">
      <bits access="r" name="clk_band_reserved_0" pos="31:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_clk_band" pos="3:0" rst="1">
        <comment>
          reg for PLL divisor
lvds_clk_band=3'b0001 with pll_din=7'h08
lvds_clk_band=3'b0010 with pll_din=7'h10
lvds_clk_band=3'b0100 with pll_din=7'h20
lvds_clk_band=3'b1000 with pll_din=7'h40
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="phase_sel">
      <bits access="r" name="phase_sel_reserved_0" pos="31:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_phase_sel" pos="2:0" rst="4">
        <comment>
          1st phase coarse tuning between TX_DATA and TX_CLOCK
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rx_data_pnsw">
      <bits access="r" name="rx_data_pnsw_reserved_0" pos="31:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_data_pnsw" pos="1:0" rst="0">
        <comment>
          input P and N switch
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rx_dl8p_sel">
      <bits access="rw" name="lvds_rx_dl8p_sel" pos="31:0" rst="0">
        <comment>
          phase fine tuning between RX_DATA and RX_CLOCK
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="rw" name="rx_dl128p_sel">
      <bits access="r" name="rx_dl128p_sel_reserved_0" pos="31:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_dl128p_sel" pos="13:0" rst="0">
        <comment>
          phase coarse tuning between RX_DATA and RX_CLOCK
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rx_pu_diff2cmos">
      <bits access="r" name="rx_pu_diff2cmos_reserved_0" pos="31:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_pu_diff2cmos" pos="2:0" rst="7">
        <comment>
          RX BUFFER enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rx_vcom_sel">
      <bits access="r" name="rx_vcom_sel_reserved_0" pos="31:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_vcom_sel" pos="2:0" rst="0">
        <comment>
          RX BUFFER select
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_dl8p_sel">
      <bits access="r" name="tx_dl8p_sel_reserved_0" pos="31:9" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_dl8p_sel" pos="8:0" rst="0">
        <comment>
          phase fine tuning between TX_DATA and TX_CLOCK
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_dl128p_sel">
      <bits access="r" name="tx_dl128p_sel_reserved_0" pos="31:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_dl128p_sel" pos="6:0" rst="0">
        <comment>
          2nd phase coarse tuning between TX_DATA and TX_CLOCK
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_hz_enable">
      <bits access="r" name="tx_hz_enable_reserved_0" pos="31:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_hz_enable" pos="2:0" rst="0">
        <comment>
          LVDS DRIVER tri-state enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_iref_bit">
      <bits access="r" name="tx_iref_bit_reserved_0" pos="31:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_iref_bit" pos="3:0" rst="8">
        <comment>
          LVDS DRIVER strength adjust
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_vcm_bit">
      <bits access="r" name="tx_vcm_bit_reserved_0" pos="31:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_vcm_bit" pos="2:0" rst="4">
        <comment>
          LVDS DRIVER output common mode voltage adjust
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_vdm_bit">
      <bits access="r" name="tx_vdm_bit_reserved_0" pos="31:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_vdm_bit" pos="2:0" rst="4">
        <comment>
          LVDS DRIVER output difference mode voltage adjust
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_res">
      <bits access="rw" name="lvds_reg_res" pos="31:0" rst="16722240">
        <comment>
          LVDS reserved register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pll_refdiv2_enable">
      <bits access="r" name="pll_refdiv2_enable_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_refdiv2_enable" pos="0:0" rst="0">
        <comment>
          enable for PLL reference clock being input clock divided by 2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pll_clk_rstb">
      <bits access="r" name="pll_clk_rstb_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_clk_rstb" pos="0:0" rst="0">
        <comment>
          PLL output clock enable
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="rw" name="pll_din">
      <bits access="r" name="pll_din_reserved_0" pos="31:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_din" pos="6:0" rst="8">
        <comment>
          set with lvds_clk_band
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pll_pcon">
      <bits access="r" name="pll_pcon_reserved_0" pos="31:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_pcon" pos="2:0" rst="0">
        <comment>
          PLL divisor decimal part,fixed to 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pll_refmulti2_enable">
      <bits access="r" name="pll_refmulti2_enable_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_refmulti2_en" pos="0:0" rst="0">
        <comment>
          PLL refmulit2 enable
        </comment>
      </bits>
    </reg>
    <hole size="192"/>
    <reg protect="rw" name="pll_vreg_bit">
      <bits access="r" name="pll_vreg_bit_reserved_0" pos="31:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_vreg_bit" pos="3:0" rst="8">
        <comment>
          PLL Regulator voltage adjust
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pu_pll">
      <bits access="r" name="pu_pll_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pu_pll" pos="0:0" rst="0">
        <comment>
          PLL power up
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="pll_lock">
      <bits access="r" name="pll_lock_reserved_0" pos="31:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="lvds_pll_lock" pos="0:0" rst="0">
        <comment>
          PLL lock status
0:unlock
1:lock
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pll_reg0">
      <bits access="r" name="pll_reg0_reserved_0" pos="31:16" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_reg0" pos="15:0" rst="4644">
        <comment>
          PLL 1st  reserved register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pll_reg1">
      <bits access="r" name="pll_reg1_reserved_0" pos="31:16" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="lvds_pll_reg1" pos="15:0" rst="48">
        <comment>
          PLL 2nd  reserved register
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="lvds_reg_config.xml">
</archive>

<archive relative="lzma.xml">
  <module name="lzma" category="System">
    <reg protect="rw" name="lzma_cmd_reg">
      <bits access="r" name="lzma_cmd_reg_reserved_0" pos="31:1" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="rw" name="start" pos="0" rst="0">
        <comment>
          Writing 1 starts block decode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_status_reg">
      <bits access="r" name="lzma_status_reg_reserved_0" pos="31:3" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="rw" name="axi_err" pos="2" rst="0">
        <comment>
          AXI bus error flag. Reading 1 indicates AXI bus operation fails and Lzma should be reset.
        </comment>
      </bits>
      <bits access="rw" name="dec_err" pos="1" rst="0">
        <comment>
          Decode error flag. Reading 1 indicates block decode error and Lzma should be reset.
        </comment>
      </bits>
      <bits access="rw" name="dec_done" pos="0" rst="0">
        <comment>
          Decode done flag. Reading 1 indicates block decode done, writing 1 clears.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_irq_mask">
      <bits access="r" name="lzma_irq_mask_reserved_0" pos="31:3" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="rw" name="axi_errirqmask" pos="2" rst="0">
        <comment>
          Writing 1 indicates a interrupt will be generated when lzma_status_reg[2]=1
        </comment>
      </bits>
      <bits access="rw" name="dec_errirqmask" pos="1" rst="0">
        <comment>
          Writing 1 indicates a interrupt will be generated when lzma_status_reg[1]=1
        </comment>
      </bits>
      <bits access="rw" name="dec_doneirqmask" pos="0" rst="0">
        <comment>
          Writing 1 indicates a interrupt will be generated when lzma_status_reg[0]=1
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reserve0">
      <bits access="r" name="reserve0_reserved_0" pos="31:0" rst="0">
        <comment>
          not used
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_config_reg1">
      <bits access="r" name="lzma_config_reg1_reserved_0" pos="31:30" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="rw" name="reg_dict_size" pos="29:17" rst="0">
        <comment>
          Lzma dictionary size in byte
        </comment>
      </bits>
      <bits access="rw" name="reg_block_size" pos="16:0" rst="0">
        <comment>
          lzma block size in byte
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_config_reg2">
      <bits access="r" name="lzma_config_reg2_reserved_0" pos="31:17" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="rw" name="reg_stream_len" pos="16:0" rst="0">
        <comment>
          lzma zip stream lenght in byte
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_config_reg3">
      <bits access="r" name="lzma_config_reg3_reserved_0" pos="31:3" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="rw" name="reg_refbyte_en" pos="2" rst="0">
        <comment>
          1: refbyte enable; 0: refbyte disable
        </comment>
      </bits>
      <bits access="rw" name="reg_cabac_movebits" pos="1" rst="0">
        <comment>
          1: cabac_movebits=5; 0: cabac_movebits=4
        </comment>
      </bits>
      <bits access="rw" name="reg_cabac_totalbits" pos="0" rst="0">
        <comment>
          1: cabac_totalbits=11; 0: cabac_totalbits=10
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="lzma_status_reg2">
      <bits access="r" name="lzma_status_reg2_reserved_0" pos="31:17" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="r" name="stream_byte_pos" pos="16:0" rst="0">
        <comment>
          current decoding byte position in zip stream
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="lzma_status_reg3">
      <bits access="r" name="lzma_status_reg3_reserved_0" pos="31:17" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="r" name="dict_byte_pos" pos="16:0" rst="0">
        <comment>
          current recovering byte position in dictionary
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="lzma_error_type">
      <bits access="r" name="lzma_error_type_reserved_0" pos="31:7" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="r" name="inbuf_underflow" pos="6" rst="0">
        <comment>
          Equals to 1 when block decode finishes with zip stream reading byte position less than (reg_stream_len-2)
        </comment>
      </bits>
      <bits access="r" name="outbuf_overflow" pos="5" rst="0">
        <comment>
          Equals to 1 when block decode finishes with block buffer writing byte position exceeds the block size
        </comment>
      </bits>
      <bits access="r" name="symbol_len_err" pos="4" rst="0">
        <comment>
          Equals to 1 when a symbol is decoded as match type with length more than 273
        </comment>
      </bits>
      <bits access="r" name="symbol_reps_err0" pos="3" rst="0">
        <comment>
          Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary size
        </comment>
      </bits>
      <bits access="r" name="symbol_reps_err1" pos="2" rst="0">
        <comment>
          Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary recovery byte postion
        </comment>
      </bits>
      <bits access="r" name="symbol_type_err" pos="1" rst="0">
        <comment>
          Equals to 1 when first symbol in a block is decoded as match type
        </comment>
      </bits>
      <bits access="r" name="inbuf_overflow" pos="0" rst="0">
        <comment>
          Equals to 1 when zip stream reading byte position exceeds the stream length
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reserve1">
      <bits access="r" name="reserve1_reserved_0" pos="31:0" rst="0">
        <comment>
          not used
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reserve2">
      <bits access="r" name="reserve2_reserved_0" pos="31:0" rst="0">
        <comment>
          not used
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="lzma_input_crc">
      <bits access="r" name="input_crc" pos="31:0" rst="0">
        <comment>
          Crc of lzma rdma read bytes
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="lzma_output_crc">
      <bits access="r" name="output_crc" pos="31:0" rst="0">
        <comment>
          Crc of lzma wdma write bytes
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reserve3">
      <bits access="r" name="reserve3_reserved_0" pos="31:0" rst="0">
        <comment>
          not used
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reserve4">
      <bits access="r" name="reserve4_reserved_0" pos="31:0" rst="0">
        <comment>
          not used
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_dma_raddr_reg">
      <bits access="rw" name="dma_raddr_reg" pos="31:0" rst="0">
        <comment>
          Base address of lzma rdma
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_dma_waddr_reg">
      <bits access="rw" name="dma_waddr_reg" pos="31:0" rst="0">
        <comment>
          Base address of lzma wdma
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lzma_inbuf_rwmargin_reg">
      <bits access="r" name="lzma_inbuf_rwmargin_reg_reserved_0" pos="31:6" rst="0">
        <comment>
          not used
        </comment>
      </bits>
      <bits access="rw" name="inbuf_rwmargin_reg" pos="5:0" rst="6">
        <comment>
          Set the margin between input_buf wrptr and rdptr for pending the decode process
        </comment>
      </bits>
    </reg>
  </module>
</archive>

<archive relative = "mailbox.xml">
  <var name="MAILBOX_SIZE"   value="2*1024" />    

  
  <module name="mailbox" category="Modem">
    <memory name="ram_array" size="MAILBOX_SIZE">
      <comment>Mailbox Ram Space
        <br/> Memory used for communication between XCPU and BCPU. 
      </comment>
    </memory>
  </module>


</archive>
<archive relative = "mips32r6.xml">
<module name="mips32" category="Debug">
    <hole size="32"/>
    <reg name="rf0_addr" protect="r">
        <bits name="rf0_addr" pos="31:0" access="r" rst="0">
            <comment>program counter for the RF stage.
            </comment>
        </bits>
    </reg>
    <hole size="3008"/>
    <reg name="cp0_rd_addr" protect="r">
        <bits name="cp0_rd_addr" pos="5:0" access="r" rst="0"/>
    </reg>
    <reg name="cp0_dcache_pfn" protect="r">
        <bits name="cp0_dcache_pfn" pos="28:12" access="r" rst="0"/>
    </reg>
    <reg name="cp0_tlb_BadVAddr" protect="r">
        <bits name="cp0_tlb_BadVAddr" pos="31:0" access="r" rst="0"/>
    </reg>
    <reg name="cp0_adr_BadVAddr" protect="r">
        <bits name="cp0_adr_BadVAddr" pos="31:0" access="r" rst="0"/>
    </reg>
    <reg name="cp0_Cause" protect="r">
        <bits name="cp0_Cause_ExcCode" pos="5:2" access="r" rst="0">
            <options>
                <option value="0" name="Int"><comment>Interrupt</comment></option>
                <option value="1" name="Mod"><comment>TLB modification exception</comment></option>
                <option value="2" name="TLBL"><comment>TLB exception (load or instruction fetch)</comment></option>
                <option value="3" name="TLBS"><comment>TLB exception (store)</comment></option>
                <option value="4" name="AdEL"><comment>Address error exception (load or instruction fetch)</comment></option>
                <option value="5" name="AdES"><comment>Address error exception (store)</comment></option>
                <option value="6" name="IBE"><comment>Bus error exception (instruction fetch)</comment></option>
                <option value="7" name="DBE"><comment>Bus error exception (data reference: load or store)</comment></option>
                <option value="8" name="Sys"><comment>Syscall exception</comment></option>
                <option value="9" name="Pb"><comment>Breakpoint exception</comment></option>
                <option value="10" name="Ri"><comment>Reserved instruction exception</comment></option>
                <option value="11" name="CpU"><comment>Coprocessor Unusable exception</comment></option>
                <option value="12" name="Ov"><comment>Arithmetic Overflow exception</comment></option>
                <default/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Cause_IP_soft" pos="9:8" access="r" rst="0">
            <comment>Theses interrupt lines are software interrupts (the cpu can write in the CP0 bits to trigger and clear them).
            </comment>
            <options>
                <default/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Cause_IP_ext" pos="15:10" access="r" rst="0">
            <comment>Theses interrupt lines maps to the hardware interrupt lines from the corresponding irq module.
            </comment>
            <options>
                <default/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bitgroup name="cp0_Cause_IP">
            <entry ref="cp0_Cause_IP_soft"/>
            <entry ref="cp0_Cause_IP_ext"/>
        </bitgroup>
        <bits name="cp0_Cause_CE" pos="29:28" access="r" rst="0">
            <comment>The Coprocessor Error (CE) field indicate the coprocessor unit number referenced when a Coprocessor Unusable exception is taken.
            </comment>
            <options>
                <default/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Cause_BD" pos="31" access="r" rst="0">
            <comment>The Branch Delay (BD) bit indicate whether the last exception was taken while executing in a branch delay slot.
            </comment>
            <options>
                <option value="0" name="Normal"/>
                <option value="1" name="Delay_slot"/>
                <mask/>
                <shift/>
            </options>
        </bits>
    </reg>
    <reg name="cp0_Status" protect="r">
        <bits name="cp0_Status_IEc" pos="0" access="r" rst="0">
            <comment>Current Interrupt Enable
            </comment>
            <options>
                <option value="0" name="disable"/>
                <option value="1" name="enable"/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Status_KUc" pos="1" access="r" rst="0">
            <comment>Current Kernel/User mode
            </comment>
            <options>
                <option value="0" name="kernel"/>
                <option value="1" name="user"/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Status_IEp" pos="2" access="r" rst="0">
            <comment>Previous Interrupt Enable
            </comment>
            <options>
                <option value="0" name="disable"/>
                <option value="1" name="enable"/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Status_KUp" pos="3" access="r" rst="0">
            <comment>Previous Kernel/User mode
            </comment>
            <options>
                <option value="0" name="kernel"/>
                <option value="1" name="user"/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Status_IEo" pos="4" access="r" rst="0">
            <comment>Old Interrupt Enable
            </comment>
            <options>
                <option value="0" name="disable"/>
                <option value="1" name="enable"/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Status_KUo" pos="5" access="r" rst="0">
            <comment>Old Kernel/User mode
            </comment>
            <options>
                <option value="0" name="kernel"/>
                <option value="1" name="user"/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="cp0_Status_KUi" pos="6" access="r" rst="0">
        </bits>
        <bits name="cp0_Status_IntMask" pos="15:8" access="r" rst="0">
            <comment>Interrupt Mask control the enabling of each of the external and software interrupts. (See Cause for more information on interruptions).
            </comment>
        </bits>
        <bits name="cp0_Streaming_Disable" pos="16" access="r" rst="0">
            <comment>This bit control handling of non-cached instruction fetch requests. By default, the system block reads multiple words of data from the AMBA bus in burst transactions and saves them in the Streaming Buffer. Non cached instruction fetch requests get their data directly from the Streaming Buffer.
            When "1" the cpu does not use the streaming buffer and does not ask for burst requests on the AMBA bus for non-cache instruction fetch requests.
            </comment>
        </bits>
        <bits name="cp0_Status_CM" pos="19" access="r" rst="0">
            <comment>Cache Miss
            <br/>Signals that the most recent access to the cachable space resulted in cache miss.
            </comment>
        </bits>
        <bits name="cp0_Status_TS" pos="21" access="r" rst="0">
            <comment>Signals that 2 entries in the TLB matched the virtual address. This is an error condition but the processor takes no action other than signalling it via this bit in the Status Register.
            </comment>
        </bits>
        <bits name="cp0_Status_BEV" pos="22" access="r" rst="1">
            <comment>Select the location of the exception vectors in ROM or in DRAM.
            </comment>
        </bits>
        <bits name="cp0_Status_RE" pos="25" access="r" rst="0">
            <comment>Reverse Endian in User mode. <font color="red">(probably unused in xcpu)</font></comment>
        </bits>
        <bits name="cp0_Status_CU_0" pos="28" access="r" rst="0" cut="1">
            <comment>Control the Usability of the corresponding Coprocessor Unit. (CP0 is always usable when in Kernel mode, regardless of the setting of the CU_0 bit.
            </comment>
        </bits>
        <bits name="cp0_Status_CU_123" pos="31:29" access="r" rst="0" cut="1" cutprefix="cp0_Status_CU" cutstart="1">
            <comment>Control the Usability of the corresponding Coprocessor Unit.
            </comment>
        </bits>
        <bitgroup name="cp0_Status_CU">
            <entry ref="cp0_Status_CU_0"/>
            <entry ref="cp0_Status_CU_123"/>
        </bitgroup>
    </reg>
    <reg name="cp0_EPC" protect="r">
        <bits name="cp0_EPC" pos="31:0" access="r" rst="0">
            <comment>Exception Program Counter. Saves the value of the program counter for the instruction
                that caused the exception.
            </comment>
        </bits>
    </reg>
    <reg name="cp0_entryhi" protect="r">
        <bits name="cp0_EntryHi_PID" pos="11:6" access="r" rst="0">
        </bits>
        <bits name="cp0_EntryHi_VPN" pos="31:12" access="r" rst="0">
        </bits>
    </reg>
    <reg name="cp0_entrylo" protect="r">
        <bits name="cp0_pagemask" pos="7:2" access="r" rst="0">
        </bits>
        <bits name="cp0_EntryLo_G" pos="8" access="r" rst="0">
        </bits>
        <bits name="cp0_EntryLo_V" pos="9" access="r" rst="0">
        </bits>
        <bits name="cp0_EntryLo_D" pos="10" access="r" rst="0">
        </bits>
        <bits name="cp0_EntryLo_N" pos="11" access="r" rst="0">
        </bits>
        <bits name="cp0_EntryLo_PFN" pos="31:12" access="r" rst="0">
        </bits>
    </reg>
    <reg name="cp0_index" protect="r">
        <bits name="cp0_Index" pos="13:8" access="r" rst="0">
        </bits>
        <bits name="cp0_Index_P" pos="31" access="r" rst="0">
        </bits>
    </reg>
    <reg name="cp0_random" protect="r">
        <bits name="cp0_Random" pos="13:8" access="r" rst="0">
        </bits>
        <bits name="cp0_Wired" pos="31:26" access="r" rst="0">
        </bits>
    </reg>
    <reg name="cp0_context" protect="r">
        <bits name="cp0_Context_BadVPN" pos="20:2" access="r" rst="0">
        </bits>
        <bits name="cp0_Context_PTEBase" pos="31:21" access="r" rst="0">
        </bits>
    </reg>
    <reg name="cp0_BadVAddr" protect="r">
        <bits name="cp0_BadVAddr" pos="31:0" access="r" rst="0">
            <comment>Bad virtual address. Saves the address that caused the address exception.
            </comment>
        </bits>
    </reg>
    <reg name="cp0_DEPC" protect="r">
        <bits name="cp0_DEPC" pos="31:0" access="r" rst="0">
            <comment>Exception Program Counter. Saves the value of the program counter for the instruction
                that caused the exception by break point instruction.
            </comment>
        </bits>
    </reg>
    <hole size="576"/>
    <reg name="rf0_data" protect="r">
        <bits name="rf0_data" pos="31:0" access="r" rst="0"/>
    </reg>
    <hole size="160"/>
    <reg name="dc0_result" protect="r">
        <bits name="dc0_result" pos="31:0" access="r" rst="0"/>
    </reg>
    <hole size="2848"/>
    
    <hole size="32"/> 

    <reg name="Regfile_AT" protect="r">
        <bits name="AT" pos="31:0" access="r" rst="no">
            <comment>assembler temporary register;
                their values are not preserved across procedure calls.
            </comment>  
        </bits>    
    </reg>
    <reg name="Regfile_V0" protect="r">
        <bits name="V0" pos="31:0" access="r" rst="no">
            <comment>Used for expression evaluations and for hold integer function results.
            <br/> Also used to pass the statuc link when calling nested procedure.
            </comment>
        </bits>    
    </reg>
    <reg name="Regfile_V1" protect="r">
        <bits name="V1" pos="31:0" access="r" rst="no">
            <comment>Used for expression evaluations and for hold integer function results.
            <br/> Also used to pass the statuc link when calling nested procedure.
            </comment>      
        </bits>    
    </reg>
    <reg name="Regfile_A0" protect="r">
        <bits name="A0" pos="31:0" access="r" rst="no">
            <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.
            </comment>      
        </bits>              
    </reg>
    <reg name="Regfile_A1" protect="r">
        <bits name="A1" pos="31:0" access="r" rst="no">
            <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.
            </comment>             
        </bits>              
    </reg>
    <reg name="Regfile_A2" protect="r">
        <bits name="A2" pos="31:0" access="r" rst="no">
            <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.
            </comment> 
        </bits>              
    </reg>
    <reg name="Regfile_A3" protect="r">
        <bits name="A3" pos="31:0" access="r" rst="no">
            <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.
            </comment>         
        </bits>              
    </reg>
    <reg name="Regfile_T0" protect="r">
        <bits name="T0" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>             
        </bits>              
    </reg>
    <reg name="Regfile_T1" protect="r">
        <bits name="T1" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_T2" protect="r">
        <bits name="T2" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_T3" protect="r">
        <bits name="T3" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_T4" protect="r">
        <bits name="T4" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_T5" protect="r">
        <bits name="T5" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_T6" protect="r">
        <bits name="T6" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_T7" protect="r">
        <bits name="T7" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_S0" protect="r">
        <bits name="S0" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>                   
        </bits>              
    </reg>
    <reg name="Regfile_S1" protect="r">
        <bits name="S1" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>              
        </bits>              
    </reg>
    <reg name="Regfile_S2" protect="r">
        <bits name="S2" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>              
        </bits>              
    </reg>
    <reg name="Regfile_S3" protect="r">
        <bits name="S3" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>              
        </bits>              
    </reg>
    <reg name="Regfile_S4" protect="r">
        <bits name="S4" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>              
        </bits>              
    </reg>
    <reg name="Regfile_S5" protect="r">
        <bits name="S5" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>              
        </bits>              
    </reg>
    <reg name="Regfile_S6" protect="r">
        <bits name="S6" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>              
        </bits>              
    </reg>
    <reg name="Regfile_S7" protect="r">
        <bits name="S7" pos="31:0" access="r" rst="no">
            <comment>saved register;
                their values must preserved across procedure calls.
            </comment>              
        </bits>              
    </reg>
    <reg name="Regfile_T8" protect="r">
        <bits name="T8" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>             
        </bits>              
    </reg>
    <reg name="Regfile_T9" protect="r">
        <bits name="T9" pos="31:0" access="r" rst="no">
            <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.
            </comment>             
        </bits>              
    </reg>
    <reg name="Regfile_K0" protect="r">
        <bits name="K0" pos="31:0" access="r" rst="no">
            <comment>reserved for the operating system kernal.
            </comment>             
        </bits>              
    </reg>
    <reg name="Regfile_K1" protect="r">
        <bits name="K1" pos="31:0" access="r" rst="no">
            <comment>reserved for the operating system kernal.
            </comment>         
        </bits>              
    </reg>
    <reg name="Regfile_GP" protect="r">
        <bits name="GP" pos="31:0" access="r" rst="no">
            <comment>contains the global pointer.
            </comment>         
        </bits>              
    </reg>
    <reg name="Regfile_SP" protect="r">
        <bits name="SP" pos="31:0" access="r" rst="no">
            <comment>contains the stack pointer.
            </comment>             
        </bits>              
    </reg>
    <reg name="Regfile_S8" protect="r">
        <bits name="S8" pos="31:0" access="r" rst="no">
            <comment>a saved register (like s0-s7).
            </comment>             
        </bits>              
    </reg>
    <reg name="Regfile_RA" protect="r">
        <bits name="RA" pos="31:0" access="r" rst="no">
            <comment>contains the return address; used for expression evaluation.
            </comment>             
        </bits>              
    </reg>
    <hole size="512"/>
    <reg name="Debug_Page_Address" protect="rw">
        <bits name="Debug_Page_Address" pos="3:0" access="rw" rst="0">
            <comment>Debug Page Address Register Is a 4 bit register used for extending the address of
the debug to enable full access to the cache RAMs.
                <br/>bit 3 is used when accessing the TAGs to select between Instruction TAG (0) or Data TAG (1).
            </comment>
            <options>
                <option name="ITag" value="0"/>
                <option name="DTag" value="8"/>
                <default/><shift/><mask/>
            </options>
        </bits>
    </reg>
    <reg name="Cache_Control" protect="rw">
        <bits name="Dcache_Inhibit" pos="0" access="rw" rst="no">
            <comment>when "ON" all accesses for data are treated as non cache. Data is fetched directly from main memory. The content of the Data Cache is not altered.
            </comment>
        </bits>
        <bits name="Icache_Inhibit" pos="1" access="rw" rst="no">
            <comment>when "ON" all accesses for instructions are treated as non cache. Data is fetched directly from main memory. The content of the cache is not altered.
            </comment>
        </bits>
        <bits name="Cache Hit Disable" pos="2" access="rw" rst="no">
            <comment>when "ON" all accesses to either Instruction or data caches result in a cache miss and a cache refill. This is a quick way to initialize the caches.
            </comment>
        </bits>
    </reg>
</module>
</archive>

<archive relative = "nb_cell_search.xml">
  <module name="nb_cell_search" category="NBIOT_PHY">
    <reg32 name="rPSS_CTRL" protect="rw">
      <bits name="rPSS_EN" pos="0" access="rw" rst="0">
        <comment>PSS Enable
1'b0: Stop PSS calculation
1'b1: Start PSS calculation
</comment>
      </bits>
      <bits name="rPSS_HYPO_NUM" pos="3:1" access="rw" rst="0">
        <comment>PSS hypothesis number</comment>
      </bits>
      <bits name="rPSS_OUT_BUF_CFG" pos="4" access="rw" rst="0">
        <comment>PSS output ping-pong buffer selection
1'b1:Select the pong buffer as the first output buffer
1'b0: Select the ping buffer as the first output buffer
</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_START_OS" protect="rw">
      <bits name="rPSS_START_SAMPLE_OS" pos="10:0" access="rw" rst="0">
        <comment>PSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920.</comment>
      </bits>
      <bits name="rPSS_START_SF_OS" pos="14:11" access="rw" rst="0">
        <comment>PSS start offset of subframe. Range is from 0 to 9.</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_SF_CNT" protect="r">
      <bits name="rPSS_SF_CNT" pos="3:0" access="r" rst="0">
        <comment>PSS internal sub frame counter(from 0 to 9)</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_OUT_STATUS" protect="r">
      <bits name="rPSS_OBUF_SEL" pos="0" access="r" rst="0">
        <comment>Indicate the buffer selection on current interrupt
1'b0: buffer0 is selection
1'b1: buffer1 is selection</comment>
      </bits>
      <bits name="rPSS_OBUF0_STATUS_0" pos="1" access="w1c" rst="0">
        <comment>PSS output buffer 0 status. Clear by DSP or MCU
1'b1: buffer 0 is ready.
1'b0:buffer0 is idle</comment>
      </bits>
      <bits name="rPSS_OBUF0_STATUS_1" pos="2" access="r" rst="0">
        <comment>PSS output buffer 0 status. 
1'b1: buffer 0 is over written. 
1'b0: buffer 0 is normal
</comment>
      </bits>
      <bits name="rPSS_OBUF1_STATUS_0" pos="3" access="w1c" rst="0">
        <comment>PSS output buffer 1 status. Clear by DSP or MCU
1'b1: buffer 1 is ready.
1'b0:buffer 1 is idle</comment>
      </bits>
      <bits name="rPSS_OBUF1_STATUS_1" pos="4" access="r" rst="0">
        <comment>PSS output buffer 1 status. 
1'b1: buffer 1 is over written. 
1'b0: buffer 1 is normal
</comment>
      </bits>
      <bits name="rPSS_DONE_STATUS" pos="5" access="w1c" rst="0">
        <comment>PSS calculation done status. Update very 1ms and clear by DSP or MCU.
1'b1: PSS calculation done 
1'b0: PSS is idle or under calculating</comment>
      </bits>
      <bits name="rPSS_MEM_ARB_STATUS" pos="7:6" access="r" rst="0">
        <comment>PSS write memory arbitration error status.
1'b1: the memory has conflict
1'b0: the memory is normal</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_NON_ZERO_STATUS" protect="r">
      <bits name="rPSS_NON_ZERO_STATUS" pos="8:0" access="r" rst="0">
        <comment>bit8: pss final output data non-zero status
bit7: pss 148x40 memory out data non-zero status
bit6: pss 148x40 memory in data non-zero status
bit5: pss power non-zero status
bit4: pss 1312x24 memory out data non-zero status
bit3: pss 1312x24 memory in data non-zero status
bit2: pss in local sequence non-zero status
bit1: pss_corr_calc in data non-zero status
bit0: pss_deci in data non-zero status</comment>
      </bits>
    </reg32>
    <hole size="3*32" />
    <reg32 name="rPSS_SAMPLE_POS_PU0" protect="rw">
      <bits name="rPSS_SAMPLE_POS_PU_0" pos="4:0" access="rw" rst="0">
        <comment>PSS sample position for Pu of hypothesis 0</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PU_1" pos="12:8" access="rw" rst="0">
        <comment>PSS sample position for Pu of hypothesis 1</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PU_2" pos="20:16" access="rw" rst="0">
        <comment>PSS sample position for Pu of hypothesis 2</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PU_3" pos="28:24" access="rw" rst="0">
        <comment>PSS sample position for Pu of hypothesis 3</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_SAMPLE_POS_PU1" protect="rw">
      <bits name="rPSS_SAMPLE_POS_PU_4" pos="4:0" access="rw" rst="0">
        <comment>PSS sample position for Pu of hypothesis 0</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PU_5" pos="12:8" access="rw" rst="0">
        <comment>PSS sample position for Pu of hypothesis 1</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PU_6" pos="20:16" access="rw" rst="0">
        <comment>PSS sample position for Pu of hypothesis 2</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_SAMPLE_POS_PL0" protect="rw">
      <bits name="rPSS_SAMPLE_POS_PL_0" pos="4:0" access="rw" rst="0">
        <comment>PSS sample position for Pl of hypothesis 0</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PL_1" pos="12:8" access="rw" rst="0">
        <comment>PSS sample position for Pl of hypothesis 1</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PL_2" pos="20:16" access="rw" rst="0">
        <comment>PSS sample position for Pl of hypothesis 2</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PL_3" pos="28:24" access="rw" rst="0">
        <comment>PSS sample position for Pl of hypothesis 3</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_SAMPLE_POS_PL1" protect="rw">
      <bits name="rPSS_SAMPLE_POS_PL_4" pos="4:0" access="rw" rst="0">
        <comment>PSS sample position for Pl of hypothesis 4</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PL_5" pos="12:8" access="rw" rst="0">
        <comment>PSS sample position for Pl of hypothesis 5</comment>
      </bits>
      <bits name="rPSS_SAMPLE_POS_PL_6" pos="20:16" access="rw" rst="0">
        <comment>PSS sample position for Pl of hypothesis 6</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_COEFF00" protect="rw">
      <bits name="rPSS_COEF_SET0_0" pos="7:0" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 0</comment>
      </bits>
      <bits name="rPSS_COEF_SET0_1" pos="15:8" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 1</comment>
      </bits>
      <bits name="rPSS_COEF_SET0_2" pos="23:16" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 2</comment>
      </bits>
      <bits name="rPSS_COEF_SET0_3" pos="31:24" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 3</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_COEFF01" protect="rw">
      <bits name="rPSS_COEF_SET0_4" pos="7:0" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 4</comment>
      </bits>
      <bits name="rPSS_COEF_SET0_5" pos="15:8" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 5</comment>
      </bits>
      <bits name="rPSS_COEF_SET0_6" pos="23:16" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 7</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_COEFF10" protect="rw">
      <bits name="rPSS_COEF_SET1_0" pos="7:0" access="rw" rst="0">
        <comment>PSS set 1 coefficient for hypothesis 0</comment>
      </bits>
      <bits name="rPSS_COEF_SET1_1" pos="15:8" access="rw" rst="0">
        <comment>PSS set 1 coefficient for hypothesis 1</comment>
      </bits>
      <bits name="rPSS_COEF_SET1_2" pos="23:16" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 2</comment>
      </bits>
      <bits name="rPSS_COEF_SET1_3" pos="31:24" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 3</comment>
      </bits>
    </reg32>
    <reg32 name="rPSS_COEFF11" protect="rw">
      <bits name="rPSS_COEF_SET1_4" pos="7:0" access="rw" rst="0">
        <comment>PSS set 1 coefficient for hypothesis 4</comment>
      </bits>
      <bits name="rPSS_COEF_SET1_5" pos="15:8" access="rw" rst="0">
        <comment>PSS set 1 coefficient for hypothesis 5</comment>
      </bits>
      <bits name="rPSS_COEF_SET1_6" pos="23:16" access="rw" rst="0">
        <comment>PSS set 0 coefficient for hypothesis 6</comment>
      </bits>
    </reg32>
    <hole size="8*32"></hole>
    <struct count="17" name="PSS_SEQ0_GROUP">
      <reg32 name="rPSS_LOCAL_SEQ0" protect="w">
        <bits name="rPSS_LOCAL_SEQ0_RE" pos="11:0" access="w" rst="0">
          <comment>Real part of the local sequence 0</comment>
        </bits>
        <bits name="rPSS_LOCAL_SEQ0_IM" pos="27:16" access="w" rst="0">
          <comment>Imag part of the local sequence 0</comment>
        </bits>
      </reg32>
    </struct>
    <struct count="17" name="PSS_SEQ1_GROUP">
      <reg32 name="rPSS_LOCAL_SEQ1" protect="w">
        <bits name="rPSS_LOCAL_SEQ1_RE" pos="11:0" access="w" rst="0">
          <comment>Real part of the local sequence 1</comment>
        </bits>
        <bits name="rPSS_LOCAL_SEQ1_IM" pos="27:16" access="w" rst="0">
          <comment>Imag part of the local sequence 1</comment>
        </bits>
      </reg32>
    </struct>
    <struct count="17" name="PSS_SEQ2_GROUP">
      <reg32 name="rPSS_LOCAL_SEQ2" protect="w">
        <bits name="rPSS_LOCAL_SEQ2_RE" pos="11:0" access="w" rst="0">
          <comment>Real part of the local sequence 2</comment>
        </bits>
        <bits name="rPSS_LOCAL_SEQ2_IM" pos="27:16" access="w" rst="0">
          <comment>Imag part of the local sequence 2</comment>
        </bits>
      </reg32>
    </struct>
    <struct count="17" name="PSS_SEQ3_GROUP">
      <reg32 name="rPSS_LOCAL_SEQ3" protect="w">
        <bits name="rPSS_LOCAL_SEQ3_RE" pos="11:0" access="w" rst="0">
          <comment>Real part of the local sequence 3</comment>
        </bits>
        <bits name="rPSS_LOCAL_SEQ3_IM" pos="27:16" access="w" rst="0">
          <comment>Imag part of the local sequence 3</comment>
        </bits>
      </reg32>
    </struct>
    <struct count="17" name="PSS_SEQ4_GROUP">
      <reg32 name="rPSS_LOCAL_SEQ4" protect="w">
        <bits name="rPSS_LOCAL_SEQ4_RE" pos="11:0" access="w" rst="0">
          <comment>Real part of the local sequence 4</comment>
        </bits>
        <bits name="rPSS_LOCAL_SEQ4_IM" pos="27:16" access="w" rst="0">
          <comment>Imag part of the local sequence 4</comment>
        </bits>
      </reg32>
    </struct>
    <struct count="17" name="PSS_SEQ5_GROUP">
      <reg32 name="rPSS_LOCAL_SEQ5" protect="w">
        <bits name="rPSS_LOCAL_SEQ5_RE" pos="11:0" access="w" rst="0">
          <comment>Real part of the local sequence 5</comment>
        </bits>
        <bits name="rPSS_LOCAL_SEQ5_IM" pos="27:16" access="w" rst="0">
          <comment>Imag part of the local sequence 5</comment>
        </bits>
      </reg32>
    </struct>
    <struct count="17" name="PSS_SEQ6_GROUP">
      <reg32 name="rPSS_LOCAL_SEQ6" protect="w">
        <bits name="rPSS_LOCAL_SEQ6_RE" pos="11:0" access="w" rst="0">
          <comment>Real part of the local sequence 6</comment>
        </bits>
        <bits name="rPSS_LOCAL_SEQ6_IM" pos="27:16" access="w" rst="0">
          <comment>Imag part of the local sequence 6</comment>
        </bits>
      </reg32>
    </struct>
    <hole size="369*32" />
    <reg32 name="rCFO_START" protect="w">
      <bits name="rCFO_START" pos="0" access="w" rst="0">
        <comment>Start trigger of one CFO calculation process by writing "1" to this register</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_START_OS" protect="rw">
      <bits name="rCFO_START_SAMPLE_OS" pos="10:0" access="rw" rst="0">
        <comment>CFO data capture start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920.</comment>
      </bits>
      <bits name="rCFO_START_SF_OS" pos="14:11" access="rw" rst="0">
        <comment>CFO data capture start offset of sub-frame. Range is from 0 to 13.</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CALC_OS" protect="rw">
      <bits name="rCFO_CALC_SAMPLE_OS" pos="10:0" access="rw" rst="0">
        <comment>CFO calculation start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920.</comment>
      </bits>
      <bits name="rCFO_CALC_SF_OS" pos="14:11" access="rw" rst="0">
        <comment>CFO calculation start offset of sub-frame. Range is from 0 to 13.</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CTRL" protect="rw">
      <bits name="rCFO_FN_NUM" pos="2:0" access="rw" rst="0">
        <comment>Rotated frequency bin number when 'rCFO_MODE=0'.</comment>
      </bits>
      <bits name="rCFO_MODE" pos="3" access="rw" rst="0">
        <comment>1: Normal mode. CFO module only deal with 1 frequency bin(f0) and 9 sampling positions(Tau). 147 correlation results are reported to corresponding ram at most.
0: Searching mode. CFO module deal with 1~7 frequency bins(f0~6) and 21 sampling positions(Tau). 9 correlation results are reported to corresponding registers.
</comment>
      </bits>
      <bits name="rCFO_RPT_ADDR" pos="13:4" access="rw" rst="0">
        <comment>Start write address of CFO correlation results' reporting ram</comment>
      </bits>
      <bits name="rCFO_GAIN" pos="16:14" access="rw" rst="0">
        <comment>Correlation results truncation (32bits to 16bits).
0:&gt;&gt;8    1:&gt;&gt;7    2:&gt;&gt;6    3:&gt;&gt;5 
4:&gt;&gt;4    5:&gt;&gt;3    6:&gt;&gt;2    7:&gt;&gt;1</comment>
      </bits>
      <bits name="rCFO_TAU_NUM" pos="21:17" access="rw" rst="0">
        <comment>Tau number of CFO correlation when rCFO_MODE=0. </comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_OS_F0TO3" protect="rw">
      <bits name="rCFO_OS_F0" pos="7:0" access="rw" rst="0">
        <comment>Sampling position start offset for bin f0</comment>
      </bits>
      <bits name="rCFO_OS_F1" pos="15:8" access="rw" rst="0">
        <comment>Sampling position start offset for bin f1</comment>
      </bits>
      <bits name="rCFO_OS_F2" pos="23:16" access="rw" rst="0">
        <comment>Sampling position start offset for bin f2</comment>
      </bits>
      <bits name="rCFO_OS_F3" pos="31:24" access="rw" rst="0">
        <comment>Sampling position start offset for bin f3</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_OS_F4TO6" protect="rw">
      <bits name="rCFO_OS_F4" pos="7:0" access="rw" rst="0">
        <comment>Sampling position start offset for bin f4</comment>
      </bits>
      <bits name="rCFO_OS_F5" pos="15:8" access="rw" rst="0">
        <comment>Sampling position start offset for bin f5</comment>
      </bits>
      <bits name="rCFO_OS_F6" pos="23:16" access="rw" rst="0">
        <comment>Sampling position start offset for bin f6</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_A_F0" protect="rw">
      <bits name="rCFO_A_F0" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_A_F1" protect="rw">
      <bits name="rCFO_A_F1" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_A_F2" protect="rw">
      <bits name="rCFO_A_F2" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_A_F3" protect="rw">
      <bits name="rCFO_A_F3" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_A_F4" protect="rw">
      <bits name="rCFO_A_F4" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_A_F5" protect="rw">
      <bits name="rCFO_A_F5" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_A_F6" protect="rw">
      <bits name="rCFO_A_F6" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_B_F0" protect="rw">
      <bits name="rCFO_B_F0" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_B_F1" protect="rw">
      <bits name="rCFO_B_F1" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_B_F2" protect="rw">
      <bits name="rCFO_B_F2" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_B_F3" protect="rw">
      <bits name="rCFO_B_F3" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_B_F4" protect="rw">
      <bits name="rCFO_B_F4" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_B_F5" protect="rw">
      <bits name="rCFO_B_F5" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_B_F6" protect="rw">
      <bits name="rCFO_B_F6" pos="31:0" access="rw" rst="0">
        <comment>The complex value of  e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
      </bits>
    </reg32>
    <hole size="4*32" />
    <reg32 name="rCFO_STATUS" protect="r">
      <bits name="rCFO_DONE_STATUS" pos="0" access="w1c" rst="0">
        <comment>CFO calculation done status. Clear by DSP or MCU.
1'b1: CFO calculation done 
1'b0: CFO is idle or under calculating</comment>
      </bits>
      <bits name="rCFO_WRAM_ERR" pos="2:1" access="r" rst="0">
        <comment>Memory request error for writing of CFO reporting ram when 'rCFO_MOED=0'
0: Normal
1: Error
Bit 2: DSP control bus error
Bit 1: accelerator memory access collusion</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR0" protect="r">
      <bits name="rCFO_CORR0" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = -4' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR1" protect="r">
      <bits name="rCFO_CORR1" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = -3' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR2" protect="r">
      <bits name="rCFO_CORR2" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = -2' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR3" protect="r">
      <bits name="rCFO_CORR3" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = -1' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR4" protect="r">
      <bits name="rCFO_CORR4" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = 0' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR5" protect="r">
      <bits name="rCFO_CORR5" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = +1' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR6" protect="r">
      <bits name="rCFO_CORR6" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = +2' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR7" protect="r">
      <bits name="rCFO_CORR7" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = +3' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <reg32 name="rCFO_CORR8" protect="r">
      <bits name="rCFO_CORR8" pos="0" access="r" rst="0">
        <comment>When 'rCFO_MODE=1', correlation value of PSS sequence for frequency bin 'rCFO_A/B_F0' and sampling position 'Tau = +4' is reported
[31:16]: imag part
[15:0]: real part</comment>
      </bits>
    </reg32>
    <hole size="30*32" />
    <reg32 name="rSSS_EN" protect="rw">
      <bits name="rSSS_EN" pos="0" access="rw" rst="0">
        <comment>SSS Enable
1'b0:Stop SSS calculation
1'b1: Start SSS calculation</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_START_OS" protect="rw">
      <bits name="rSSS_START_SAMPLE_OS" pos="10:0" access="rw" rst="0">
        <comment>SSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920.</comment>
      </bits>
      <bits name="rSSS_START_SF_OS" pos="14:11" access="rw" rst="0">
        <comment>SSS start offset of subframe. Range is from 0 to 9.</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_START_CALC_OS" protect="rw">
      <bits name="rSSS_START_CALC_SAMPLE_OS" pos="10:0" access="rw" rst="0">
        <comment>SSS start calculation offset of sample within a subframe. Based on 1.92MHz. Range is from 0 to 1920.</comment>
      </bits>
      <bits name="rSSS_START_CALC_SF_OS" pos="14:11" access="rw" rst="0">
        <comment>SSS start calculation offset of subframe. Range is from 0 to 9.</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT0" protect="rw">
      <bits name="rSSS_PHASE_SHIFT0_RE" pos="11:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT0_IM" pos="27:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT1" protect="rw">
      <bits name="rSSS_PHASE_SHIFT1_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 1</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT1_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 1</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT2" protect="rw">
      <bits name="rSSS_PHASE_SHIFT2_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 2</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT2_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 2</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT3" protect="rw">
      <bits name="rSSS_PHASE_SHIFT3_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 3</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT3_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 3</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT4" protect="rw">
      <bits name="rSSS_PHASE_SHIFT4_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 4</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT4_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 4</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT5" protect="rw">
      <bits name="rSSS_PHASE_SHIFT5_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 5</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT5_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 5</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT6" protect="rw">
      <bits name="rSSS_PHASE_SHIFT6_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 6</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT6_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 6</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT7" protect="rw">
      <bits name="rSSS_PHASE_SHIFT7_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 7</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT7_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 7</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT8" protect="rw">
      <bits name="rSSS_PHASE_SHIFT8_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 8</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT8_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 8</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT9" protect="rw">
      <bits name="rSSS_PHASE_SHIFT9_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 9</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT9_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 9</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PHASE_SHIFT10" protect="rw">
      <bits name="rSSS_PHASE_SHIFT10_RE" pos="15:0" access="rw" rst="0">
        <comment>Real part of SSS phase shift 10</comment>
      </bits>
      <bits name="rSSS_PHASE_SHIFT10_IM" pos="31:16" access="rw" rst="0">
        <comment>Imag part of SSS phase shift 10</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_SF_CNT" protect="r">
      <bits name="rSSS_SF_CNT" pos="3:0" access="r" rst="0">
        <comment>SSS internal sub frame counter(from 0 to 9)</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_GLB_CNT" protect="r">
      <bits name="rSSS_GLB_SAMPLE_CNT" pos="10:0" access="r" rst="0">
        <comment>global sample count value at SSS subframe start</comment>
      </bits>
      <bits name="rSSS_GLB_SF_CNT" pos="14:11" access="r" rst="0">
        <comment>global subframe count value at SSS subframe start</comment>
      </bits>
      <bits name="rSSS_GLB_RF_CNT" pos="17:15" access="r" rst="0">
        <comment>Global radio frame count value at SSS subframe start</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_OUT_STATUS" protect="r">
      <bits name="rSSS_OBUF_SEL" pos="0" access="r" rst="0">
        <comment>Indicate the buffer selection on current interrupt
1'b0: MEM0 is selection
1'b1: MEM1 is selection</comment>
      </bits>
      <bits name="RESERVED" pos="1" access="rw" rst="0">
        <comment>RESERVED</comment>
      </bits>
      <bits name="rSSS_OBUF0_STATUS_0" pos="2" access="w1c" rst="0">
        <comment>SSS output buffer 0 status. Clear by DSP or MCU
bit 2: 1'b1: MEM2 or MEM0  is ready.1'b0:buffer0 is idle</comment>
      </bits>
      <bits name="rSSS_OBUF0_STATUS_1" pos="3" access="r" rst="0">
        <comment>SSS output buffer 0 status. 
bit 3: 1'b1: MEM2 or MEM0  is over written. 1'b0: buffer 0 is normal</comment>
      </bits>
      <bits name="rSSS_OBUF1_STATUS_0" pos="4" access="w1c" rst="0">
        <comment>SSS output buffer 1 status. Clear by DSP or MCU
bit 4: 1'b1: MEM3 or MEM1  is ready.1'b0:buffer1 is idle</comment>
      </bits>
      <bits name="rSSS_OBUF1_STATUS_1" pos="5" access="r" rst="0">
        <comment>SSS output buffer 1 status.
bit 5: 1'b1: MEM3 or MEM1  is over written. 1'b0: buffer 1 is normal</comment>
      </bits>
      <bits name="rSSS_DONE_STATUS" pos="6" access="w1c" rst="0">
        <comment>SSS calculation done status. Update very 1ms and clear by DSP or MCU.
1'b1: SSS calculation done 
1'b0: SSS is idle or under calculating</comment>
      </bits>
      <bits name="rSSS_MEM_ARB_STATUS" pos="8:7" access="r" rst="0">
        <comment>SSS write memory arbitration error status.
0: Normal
1: Error
Bit 7: DSP control bus error
Bit 8: accelerator memory access collusion</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_FFT_CTRL" protect="rw">
      <bits name="rSSS_FFT_CP_OS" pos="3:0" access="rw" rst="0">
        <comment>OFDM symbol CP offset which use to locate the FFT windows start position for serving cell.
Value:[0:9]</comment>
      </bits>
      <bits name="rSSS_FFT_SCALE" pos="6:4" access="rw" rst="0">
        <comment>FFT result scaling
3'd0: 2^-3
3'd1: 2^-2
3'd2: 2^-1
3'd3: 2^0
3'd4: 2^1
3'd5: 2^2</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_CORR_CTRL" protect="rw">
      <bits name="rSSS_CORR_SCAL" pos="2:0" access="rw" rst="5">
        <comment>Correlation result sScaling for both power and correlation
3'd0: 20
3'd1: 2-1
3'd2: 2-2
3'd3: 2-3
3'd4: 2-4
3'd5: 2-5(Default)
3'd6: 2-6
3'd7: 2-7</comment>
      </bits>
      <bits name="rSSS_CYCLIC_SHIFT" pos="4:3" access="rw" rst="0">
        <comment>Cyclic shift value 
It is used when rSSS_CYCLIC_SHIFT_FIX_EN = 1'b1.Rang is from 0 to 2.</comment>
      </bits>
      <bits name="rSSS_CYCLIC_SHIFT_FIX_EN" pos="5" access="rw" rst="0">
        <comment>Fix cyclic shift enable</comment>
      </bits>
      <bits name="rSSS_PCI_ID" pos="14:6" access="rw" rst="0">
        <comment>PCI ID 
It is used when rSSS_PCI_ID_FIX_RN = 1'b1 or rSSS_SIC_EN = 1'b1. Range is from 0 to 503.</comment>
      </bits>
      <bits name="rSSS_PCI_ID_FIX_EN" pos="15" access="rw" rst="0">
        <comment>Fix PCI ID Enable.</comment>
      </bits>
      <bits name="RESERVED" pos="16" access="rw" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rSSS_SIC_EN" pos="17" access="rw" rst="0">
        <comment>SIC Enable
Used for succesive interference cancellation.</comment>
      </bits>
      <bits name="rSSS_OUT_BUF_CFG" pos="18" access="rw" rst="0">
        <comment>SSS output ping-pong buffer selection
1'b1:Select the pong buffer as the first output buffer
1'b0: Select the ping buffer as the first output buffer</comment>
      </bits>
      <bits name="rSSS_CORR_SCAL2" pos="21:19" access="rw" rst="4">
        <comment>Scaling for correlation only
3'd0: 2-4
3'd1: 2-3
3'd2: 2-2
3'd3: 2-1
3'd4: 20(Default)
3'd5: 21
3'd6: 22
3'd7: 23</comment>
      </bits>
    </reg32>
    <reg32 name="rSSS_PWR" protect="rw">
      <bits name="rSSS_PWR" pos="15:0" access="rw" rst="0x0">
        <comment>SSS total power</comment>
      </bits>
    </reg32>
  </module>
</archive>

<archive relative = "nb_common.xml">
  <module name="nb_common" category="NBIOT_PHY">
    <reg32 name="rRX_INT_DSP_SYM_BMP_MSK" protect="rw">
      <bits name="rRX_INT_DSP_SYM_BMP_MSK" pos="13:0" access="rw" rst="0x1">
        <comment>RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0.</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_INT_MCU_SYM_BMP_MSK" protect="rw">
      <bits name="rRX_INT_MCU_SYM_BMP_MSK" pos="13:0" access="rw" rst="0x1">
        <comment>RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0.</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_INT_OS" protect="rw">
      <bits name="rRX_INT_OS" pos="6:0" access="rw" rst="0x40">
        <comment>RX interrupt output OS 0 - 127</comment>
      </bits>
    </reg32>
    <hole size="5*32" />
    <reg32 name="rRX_ADJ_CCTRL" protect="rw">
      <bits name="rRX_ADJ_SF_CNT" pos="3:0" access="rw" rst="0">
        <comment>RX adjustment subframe count from 0 - 9 (auto clear in next subframe)</comment>
      </bits>
      <bits name="rRX_ADJ_SYM_CNT" pos="7:4" access="rw" rst="0">
        <comment>RX adjustment symbol count from 0 - 13 (auto clear in next subframe)</comment>
      </bits>
      <bits name="rRX_ADJ_SYM_DIR" pos="8" access="rw" rst="0">
        <comment>RX adjustment symbol direction (auto clear in next subframe)
0: advance
1: postpone</comment>
      </bits>
      <bits name="rRX_ADJ_CSAMPLE_CNT" pos="23:16" access="rw" rst="0">
        <comment>RX coarse adjustment sample count from 0 - 138 in (chip unit) - (auto clear in next subframe)</comment>
      </bits>
      <bits name="rRX_ADJ_CSAMPLE_DIR" pos="24" access="rw" rst="0">
        <comment>RX coarse adjustment sample direction (auto clear in next subframe)
0: advance
1: postpone</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_ADJ_FCTRL" protect="rw">
      <bits name="rRX_ADJ_FSAMPLE_CNT" pos="3:0" access="rw" rst="0">
        <comment>RX fine adjustment sample count from 0 - 9 in (chip unit) -  (auto clear in next subframe)</comment>
      </bits>
      <bits name="rRX_ADJ_FSAMPLE_DIR" pos="4" access="rw" rst="0">
        <comment>RX fine adjustment sample direction (auto clear in next subframe)
0: advance
1: postpone</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_INT_POS_STATUS_DSP" protect="r">
      <bits name="rRX_INT_SYM_DSP" pos="3:0" access="r" rst="0">
        <comment>RX interrupt symbol number 0-13</comment>
      </bits>
      <bits name="rRX_INT_SF_DSP" pos="7:4" access="r" rst="0">
        <comment>RX interrupt symbol number 0-13</comment>
      </bits>
      <bits name="rRX_INT_BUF_IDX_DSP" pos="8" access="r" rst="0">
        <comment>RX interrupt buffer index
Mirror rRX_INT_BUF_IDX_MCU register</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_INT_POS_STATUS_MCU" protect="r">
      <bits name="rRX_INT_SYM_MCU" pos="3:0" access="r" rst="0">
        <comment>RX interrupt symbol number 0-13</comment>
      </bits>
      <bits name="rRX_INT_SF_MCU" pos="7:4" access="r" rst="0">
        <comment>RX interrupt symbol number 0-13</comment>
      </bits>
      <bits name="rRX_INT_BUF_IDX_MCU" pos="8" access="r" rst="0">
        <comment>RX interrupt buffer index</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_SFN" protect="rw">
      <bits name="rRX_SFN" pos="9:0" access="rw" rst="0">
        <comment>RX SFN number 0-1023</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_GLB_CNT_SF" protect="r">
      <bits name="rRX_GLB_SAMPLE_CNT_SF" pos="10:0" access="r" rst="0">
        <comment>global sample count value at RX subframe start</comment>
      </bits>
      <bits name="rRX_GLB_SF_CNT_SF" pos="14:11" access="r" rst="0">
        <comment>global subframe count value at RX subframe start</comment>
      </bits>
      <bits name="rRX_GLB_RF_CNT_SF" pos="17:15" access="r" rst="0">
        <comment>global sample count value at RX subframe start</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_GLB_CNT_RF" protect="r">
      <bits name="rRX_GLB_SAMPLE_CNT_RF" pos="10:0" access="r" rst="0">
        <comment>global sample count value at RX radio frame start</comment>
      </bits>
      <bits name="rRX_GLB_SF_CNT_RF" pos="14:11" access="r" rst="0">
        <comment>global subframe count value at RX radio frame start</comment>
      </bits>
      <bits name="rRX_GLB_RF_CNT_RF" pos="17:15" access="r" rst="0">
        <comment>global sample count value at RX radio frame start</comment>
      </bits>
    </reg32>
    <reg32 name="rTCU_GLB_CNT" protect="r">
      <bits name="rTCU_GLB_SAMPLE_CNT" pos="10:0" access="r" rst="0">
        <comment>global sample count value at TCU subframe start</comment>
      </bits>
      <bits name="rTCU_GLB_SF_CNT" pos="14:11" access="r" rst="0">
        <comment>global subframe count value at TCU subframe start</comment>
      </bits>
      <bits name="rTCU_GLB_RF_CNT" pos="17:15" access="r" rst="0">
        <comment>global sample count value at TCU subframe start</comment>
      </bits>
    </reg32>
    <hole size="4*32" />
    <reg32 name="rTX_ADJ_CCTRL" protect="rw">
      <bits name="rTX_ADJ_CSAMPLE_CNT" pos="10:0" access="rw" rst="0">
        <comment>TX coarse adjustment sample count from 0 - 1919 in (chip unit) - (auto clear in next subframe)</comment>
      </bits>
      <bits name="rTX_ADJ_CSAMPLE_DIR" pos="11" access="rw" rst="0">
        <comment>TX coarse adjustment sample direction - (auto clear in next subframe)
0: advance
1: postpone</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_ADJ_FCTRL" protect="rw">
      <bits name="rTX_ADJ_FSAMPLE_CNT" pos="5:0" access="rw" rst="0">
        <comment>15KHz: TX fine adjustment sample count from 0 - 9 in (chip unit)
3.75Hz: TX fine adjustment sample count from (0 - 9) x 4 in (chip unit) 
Remark: SW should configure the sample boundary which is aligned to 3.75Hz sample if the timing adjustment between TX transmission.
(auto clear in next subframe)</comment>
      </bits>
      <bits name="rTX_ADJ_CSAMPLE_DIR" pos="6" access="rw" rst="0">
        <comment>TX fine adjustment sample direction -  (auto clear in next subframe)
0: advance
1: postpone</comment>
      </bits>
      <bits name="rTX_ADJ_FMODE" pos="8" access="rw" rst="0">
        <comment>TX fine adjustment mode control:
0: adjust the boundary at the end of the current subframe
1: adjust the CP at the first symbol of the next TX </comment>
      </bits>
    </reg32>
    <hole size="1*32"></hole>
    <reg32 name="rTX_GLB_CNT_SF" protect="r">
      <bits name="rTX_GLB_SAMPLE_CNT_SF" pos="10:0" access="r" rst="0">
        <comment>global sample count value at TX subframe start</comment>
      </bits>
      <bits name="rTX_GLB_SF_CNT_SF" pos="14:11" access="r" rst="0">
        <comment>global subframe count value at TX subframe start</comment>
      </bits>
      <bits name="rTX_GLB_RF_CNT_SF" pos="17:15" access="r" rst="0">
        <comment>global radio frame count value at TX subframe start</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_SUBSAMPLE_CTRL" protect="rw">
      <bits name="rTX_SUBSAMPLE_CTRL" pos="0" access="rw" rst="0">
        <comment>TX subsample control
0: sync with global subsample counter
1: only sync with RX subsample counter when TX is not on transmission</comment>
      </bits>
    </reg32>
    <reg32 name="rCTRL_STATUS" protect="rw">
      <bits name="rCTRL_RX_CADJ_STATUS" pos="0" access="w1c" rst="0">
        <comment>Control RX coarse adjustment status</comment>
      </bits>
      <bits name="rCTRL_RX_FADJ_STATUS" pos="1" access="w1c" rst="0">
        <comment>Control RX fine adjustment status</comment>
      </bits>
      <bits name="rCTRL_TX_CADJ_STATUS" pos="2" access="w1c" rst="0">
        <comment>Control TX coarse adjustment status</comment>
      </bits>
      <bits name="rCTRL_TX_FADJ_STATUS" pos="3" access="w1c" rst="0">
        <comment>Control TX fine adjustment status</comment>
      </bits>
    </reg32>
    <reg32 name="rCTRL_ADJ_EN" protect="rw">
      <bits name="rCTRL_ADJ_EN" pos="0" access="rw" rst="0">
        <comment>Control adjustment enable
1: enable
0: disable</comment>
      </bits>
    </reg32>
    <hole size="1*32"></hole>
    <reg32 name="CAPTURE1_GLB_CNT" protect="w">
      <bits name="CAPTURE1_GLB_CNT" pos="0" access="w" rst="0">
        <comment>Trigger to sample global counter position for DSP debegging</comment>
      </bits>
    </reg32>
    <reg32 name="rCAPTURE1_GLB_CNT" protect="r">
      <bits name="rCAPTURE1_GLB_CNT" pos="10:0" access="r" rst="0">
        <comment>global counter sample position when CAPTURE1_GLB_CNT is accessed</comment>
      </bits>
      <bits name="rCAPTURE1_GLB_SF_CNT" pos="14:11" access="r" rst="0">
        <comment>global counter subframe position when CAPTURE1_GLB_CNT is accessed</comment>
      </bits>
      <bits name="rCAPTURE1_GLB_RF_CNT" pos="17:15" access="r" rst="0">
        <comment>global counter radio frame position when CAPTURE1_GLB_CNT is accessed</comment>
      </bits>
    </reg32>
    <reg32 name="CAPTURE2_GLB_CNT" protect="w">
      <bits name="CAPTURE2_GLB_CNT" pos="0" access="w" rst="0">
        <comment>Trigger to sample global counter position for MCU debegging</comment>
      </bits>
    </reg32>
    <reg32 name="rCAPTURE2_GLB_CNT" protect="r">
      <bits name="rCAPTURE2_GLB_CNT" pos="10:0" access="r" rst="0">
        <comment>global counter sample position when CAPTURE2_GLB_CNT is accessed</comment>
      </bits>
      <bits name="rCAPTURE2_GLB_SF_CNT" pos="14:11" access="r" rst="0">
        <comment>global counter subframe position when CAPTURE2_GLB_CNT is accessed</comment>
      </bits>
      <bits name="rCAPTURE2_GLB_RF_CNT" pos="17:15" access="r" rst="0">
        <comment>global counter radio frame position when CAPTURE2_GLB_CNT is accessed</comment>
      </bits>
    </reg32>
    <reg32 name="SLEEP_W" protect="w">
      <bits name="SLEEP_W" pos="0" access="w" rst="0">
        <comment>For sleep operation
When SLEEP_W is accessed, the start values needed for wake-up are loaded. Then values have to be written before the SLEEP_W is accessed</comment>
      </bits>
    </reg32>
    <reg32 name="rSLEEP_GLB_CNT" protect="rw">
      <bits name="rGLB_SUB_SAMPLE_CNT" pos="4:0" access="r" rst="0">
        <comment>Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for alignment of the DFE input valid.
0-31</comment>
      </bits>
      <bits name="rGLB_SAMPLE_CNT" pos="15:5" access="rw" rst="0">
        <comment>global counter sample position in sleep mode (in chip unit)</comment>
      </bits>
      <bits name="rGLB_SF_CNT" pos="19:16" access="rw" rst="0">
        <comment>global counter subframe position </comment>
      </bits>
      <bits name="rGLB_RF_CNT" pos="22:20" access="rw" rst="0">
        <comment>global counter radio frame position</comment>
      </bits>
    </reg32>
    <reg32 name="rSLEEP_RX_TX_CNT" protect="rw">
      <bits name="rTX_SAMPLE_CNT" pos="10:0" access="rw" rst="0">
        <comment>Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for align the DFE input valid.
0-31</comment>
      </bits>
      <bits name="rRX_SAMPLE_CNT" pos="23:16" access="rw" rst="0">
        <comment>RX sample count value</comment>
      </bits>
      <bits name="rRX_SYM_CNT" pos="27:24" access="rw" rst="0">
        <comment>RX OFDM symbol count value</comment>
      </bits>
      <bits name="rRX_SF_CNT" pos="31:28" access="rw" rst="0">
        <comment>RX subframe count value</comment>
      </bits>
    </reg32>
    <reg32 name="rSLEEP_ELAPSED_CNT" protect="ro">
      <bits name="rSLEEP_ELAPSED_SUBSAMPLE_CNT" pos="4:0" access="ro" rst="0">
        <comment>Sleep Elapsed Subsample counter
Range: 0-31</comment>
      </bits>
      <bits name="rSLEEP_ELAPSED_SAMPLE_CNT" pos="18:8" access="ro" rst="0">
        <comment>Sleep Elapsed Subsample counter
Range: 0-1919</comment>
      </bits>
    </reg32>
    <reg32 name="rSLEEP_ELAPSED_SF_CNT" protect="ro">
      <bits name="rSLEEP_ELAPSED_SF_CNT" pos="31:0" access="ro" rst="0">
        <comment>Sleep Elapsed SF counter
Range: 0-2^32-1</comment>
      </bits>
    </reg32>
    <hole size="27*32" />
    <reg32 name="rTCU_EVENT_TRIG" protect="rw">
      <bits name="rTCU_EVENT_SAMPLE_TIME" pos="15:5" access="rw" rst="0">
        <comment>TCU event subsample time</comment>
      </bits>
      <bits name="rTCU_EVENT_SF_TIME" pos="19:16" access="rw" rst="0">
        <comment>TCU event subframe time</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_SYNC_MODE" protect="rw">
      <bits name="rRX_SYNC_MODE" pos="0" access="rw" rst="0">
        <comment>RX synchronization method mode
0: normal mode
1: sync counter with input i_rx_sync_start pulse in DUMP mode only (For testing only)
</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_SYNC_INIT_1" protect="rw">
      <bits name="rRX_SF_SYNC_INIT_1" pos="3:0" access="rw" rst="0x9">
        <comment>RX subframe count sync initialization value - 1</comment>
      </bits>
      <bits name="rGLB_SF_SYNC_INIT_1" pos="11:8" access="rw" rst="0x9">
        <comment>Global subframe count sync initialization value - 1</comment>
      </bits>
      <bits name="rGLB_RF_SYNC_INIT_1" pos="14:12" access="rw" rst="0x7">
        <comment>Global radio frame count sync initialization value - 1</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_CAPTURE_EVENT_TRIG" protect="rw">
      <bits name="rRX_CAPTURE_SAMPLE_TIME" pos="15:5" access="rw" rst="0">
        <comment>RX Capture event sample time</comment>
      </bits>
      <bits name="rRX_CAPTURE_SF_TIME" pos="19:16" access="rw" rst="0">
        <comment>RX Capture event subframe time</comment>
      </bits>
    </reg32>
    <hole size="60*32" />
    <reg32 name="rDSP_MEM0_CTRL" protect="rw">
      <bits name="rDSP_MEM0_CTRL" pos="1:0" access="rw" rst="0">
        <comment>DSP memory 0 control 
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
      </bits>
    </reg32>
    <reg32 name="rDSP_MEM1_CTRL" protect="rw">
      <bits name="rDSP_MEM1_CTRL" pos="1:0" access="rw" rst="0">
        <comment>DSP memory 1 control 
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
      </bits>
    </reg32>
    <reg32 name="rDSP_MEM2_CTRL" protect="rw">
      <bits name="rDSP_MEM2_CTRL" pos="1:0" access="rw" rst="0">
        <comment>DSP memory 2 control 
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
      </bits>
    </reg32>
    <reg32 name="rDSP_MEM3_CTRL" protect="rw">
      <bits name="rDSP_MEM3_CTRL" pos="1:0" access="rw" rst="0">
        <comment>DSP memory 3 control 
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
      </bits>
    </reg32>
    <reg32 name="rDSP_MEM4_CTRL" protect="rw">
      <bits name="rDSP_MEM4_CTRL" pos="1:0" access="rw" rst="0">
        <comment>DSP memory 4 control 
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
      </bits>
    </reg32>
    <reg32 name="rDSP_MEM5_CTRL" protect="rw">
      <bits name="rDSP_MEM5_CTRL" pos="1:0" access="rw" rst="0">
        <comment>DSP memory 5 control 
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
      </bits>
    </reg32>
    <hole size="1*32" />
    <reg32 name="rDSP_MEM7_CTRL" protect="rw">
      <bits name="rDSP_MEM7_CTRL" pos="1:0" access="rw" rst="0">
        <comment>DSP memory 7 control 
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
      </bits>
    </reg32>
  </module>
</archive>

<archive relative = "nb_ctrl.xml">
  <module name="nb_ctrl" category="NBIOT_PHY">
    <reg32 name="rNBIOT_SW_RST" protect="w">
      <bits name="rRX_FFT_SW_RST" pos="0" access="w" rst="0">
        <comment>RX FFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rRX_PSS_SW_RST" pos="1" access="w" rst="0">
        <comment>RX Cell Search PSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.
</comment>
      </bits>
      <bits name="rRX_SSS_SW_RST" pos="2" access="w" rst="0">
        <comment>RX Cell Search SSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rRX_CFO_SW_RST" pos="3" access="w" rst="0">
        <comment>RX CFO sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rRX_VIT_SW_RST" pos="4" access="w" rst="0">
        <comment>RX Viterbi sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rRX_AGC_SW_RST" pos="5" access="w" rst="0">
        <comment>RX AGC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rDS_BSEL_SW_RST" pos="6" access="w" rst="0">
        <comment>RX DS_BSEL sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rTX_FRONTEND_SW_RST" pos="7" access="w" rst="0">
        <comment>TX frontend sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rPUSCH_ENC_SW_RST" pos="8" access="w" rst="0">
        <comment>PUSCH encoder sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rTX_CHSC_SW_RST" pos="9" access="w" rst="0">
        <comment>TX CHSC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rFFT_512_SW_RST" pos="10" access="w" rst="0">
        <comment>FFT 512 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rNPRS_ACC1_SW_RST" pos="11" access="w" rst="0">
        <comment>NPRS acc1 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rFINE_IFFT_SW_RST" pos="12" access="w" rst="0">
        <comment>FINE_IFFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rNBIOT_SW_RST" pos="13" access="w" rst="0">
        <comment>rNBIOT general part reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
      <bits name="rNBIOT_RSRP_RST" pos="14" access="w" rst="0">
        <comment>NC_RSRP sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
    </reg32>
    <reg32 name="rNBIOT_CLK_EN" protect="rw">
      <bits name="rRX_FFT_CLK_EN" pos="0" access="rw" rst="0">
        <comment>Enable/disable the clock for RX FFT/RSRP module 
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rRX_PSS_CLK_EN" pos="1" access="rw" rst="0">
        <comment>Enable/disable the clock for RX Cell Search module PSS
0: clock disabled
1: clock enabled.
</comment>
      </bits>
      <bits name="rRX_SSS_CLK_EN" pos="2" access="rw" rst="0">
        <comment>Enable/disable the clock for RX Cell Search module SSS
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rRX_CFO_CLK_EN" pos="3" access="rw" rst="0">
        <comment>Enable/disable the clock for RX CFO module 
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rRX_VIT_CLK_EN" pos="4" access="rw" rst="0">
        <comment>Enable/disable the clock for RX Viterbi module 
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rRX_AGC_CLK_EN" pos="5" access="rw" rst="0">
        <comment>Enable/disable the clock for RX AGC module 
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rDS_BSEL_CLK_EN" pos="6" access="rw" rst="0">
        <comment>Enable/disable the clock for DS_BSEL module 
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rTX_FRONTEND_CLK_EN" pos="7" access="rw" rst="0">
        <comment>Enable/disable the clock for TX Frontend module.
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rPUSCH_ENC_CLK_EN" pos="8" access="rw" rst="0">
        <comment>Enable/disable the clock for PUSCH encoder module.
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rTX_CHSC_CLK_EN" pos="9" access="rw" rst="0">
        <comment>Enable/disable the clock for TX TX channel-interleaver and scrambling module.
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rFFT_512_CLK_EN" pos="10" access="rw" rst="0">
        <comment>Enable/disable the clock for FFT 512 module.
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rNPRS_ACC1_CLK_EN" pos="11" access="rw" rst="0">
        <comment>Enable/disable the clock for NPRS ACC1 module.
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rFINE_FFT_CLK_EN" pos="12" access="rw" rst="0">
        <comment>Enable/disable the clock for FINE ifft module
0: clock disabled
1: clock enabled.</comment>
      </bits>
      <bits name="rNBIOT_CLK_EN" pos="13" access="rw" rst="0">
        <comment>Enable/disable the clock for NBIOT module
0: clock disabled
1: clock enabled.</comment>
      </bits>
    </reg32>
    <reg32 name="rNBIOT_MONITOR" protect="rw">
      <bits name="rNBIOT_MONITOR_SEL" pos="7:0" access="rw" rst="0">
        <comment>Debug signal selection</comment>
      </bits>
      <bits name="rNBIOT_MONITOR_EN" pos="8" access="rw" rst="0">
        <comment>Debug signal output enable</comment>
      </bits>
    </reg32>
    <reg32 name="rNBIOT_RFIN_SW_RST" protect="w">
      <bits name="rNBIOT_RFIN_SW_RST" pos="0" access="w" rst="0">
        <comment>RFIN reset by DSP, it is used to re-timing the global timer to balance the timing of IQ data input from DFE in sample boundary. Write 1 and auto-clear by HW.
0: default value
1: reset to re-timing the sample boundary in global timer.</comment>
      </bits>
    </reg32>
    <reg32 name="rNBIOT_RFIN_STATUS" protect="r">
      <bits name="rNBIOT_RFIN_SUBSMAPLE_CNT" pos="12:8" access="r" rst="0">
        <comment>Sample the glb_subsample_cnt with input rx_data_vld to check the phase change of the input</comment>
      </bits>
      <bits name="rNBIOT_RFIN_STATUS_ERR" pos="0" access="r" rst="0">
        <comment>Keep track the RFIN data strobe in valid window.
0: Normal
1: Error</comment>
      </bits>
    </reg32>
    <reg32 name="rNBIOT_COARSE_CLK_GATING" protect="rw">
      <bits name="rPSS_COS_CLK_GATING" pos="1" access="rw" rst="0">
        <comment>PSS Correlator coarse clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator.</comment>
      </bits>
      <bits name="rSSS_COS_CLK_GATING" pos="2" access="rw" rst="0">
        <comment>SSS Correlator coarse clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator.</comment>
      </bits>
      <bits name="Reserved" pos="12:3" access="rw" rst="0">
        <comment></comment>
      </bits>
    </reg32>
    <reg32 name="rNBIOT_FINE_CLK_GATING" protect="rw">
      <bits name="rFFT_RSRP_FT_CLK_GATING" pos="0" access="rw" rst="0">
        <comment>FFT_RSRP fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module FFT_RSRP.
</comment>
      </bits>
      <bits name="rPSS_FT_CLK_GATING" pos="1" access="rw" rst="0">
        <comment>PSS Correlator fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator.</comment>
      </bits>
      <bits name="rSSS_FT_CLK_GATING" pos="2" access="rw" rst="0">
        <comment>SSS Correlator fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator.</comment>
      </bits>
      <bits name="rCFO_FT_CLK_GATING" pos="3" access="rw" rst="0">
        <comment>CFO Correlator fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module CFO Correlator.</comment>
      </bits>
      <bits name="rVIT_FT_CLK_GATING" pos="4" access="rw" rst="0">
        <comment>Viterbi fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module Viterbi.</comment>
      </bits>
      <bits name="rAGC_FT_CLK_GATING" pos="5" access="rw" rst="0">
        <comment>AGC fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module AGC.</comment>
      </bits>
      <bits name="rDS_BSEL_FT_CLK_GATING" pos="6" access="rw" rst="0">
        <comment>DS_BSEL fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module DS_BSEL.
</comment>
      </bits>
      <bits name="rTX_FRONTEND_FT_CLK_GATING" pos="7" access="rw" rst="0">
        <comment>TX_FRONTEND fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module TX_FRONTEND.
</comment>
      </bits>
      <bits name="rPUSCH_ENC_CLK_GATING" pos="8" access="rw" rst="0">
        <comment>PUSCH_ENC fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module PUSCH_ENC.</comment>
      </bits>
      <bits name="rTX_CHSC_CLK_GATING" pos="9" access="rw" rst="0">
        <comment>TX_CHSC fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module TX_CHSC.</comment>
      </bits>
      <bits name="rFFT_512_CLK_GATING" pos="10" access="rw" rst="0">
        <comment>FFT 512 fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module FFT 512.</comment>
      </bits>
      <bits name="rNPRS_ACC1_CLK_GATING" pos="11" access="rw" rst="0">
        <comment>NPRS ACC1 fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module NPRS ACC1.</comment>
      </bits>
      <bits name="rFINE_IFFT_CLK_GATING" pos="12" access="rw" rst="0">
        <comment>FIne IFFT fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module FINE_IFFT.</comment>
      </bits>
    </reg32>
    <reg32 name="rAPB_SW_RST" protect="w">
      <bits name="rAPB_SW_RST" pos="0" access="w" rst="0">
        <comment>NBIOT CORE APB domain reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
      </bits>
    </reg32>
    <reg32 name="rNBIOT_DEBUG_GPO" protect="rw">
      <bits name="rNBIOT_DEBUF_GPO" pos="3:0" access="rw" rst="0">
        <comment>Debug General Purpose Output 
Remark: need to set rNBIOT_MONITOR to 0x1a3</comment>
      </bits>
    </reg32>
    <hole size="55*32"></hole>
    <reg32 name="rNBIOT_REVISION" protect="r">
      <bits name="rMINOR_REV" pos="7:0" access="r" rst="0">
        <comment>Minor Revision</comment>
      </bits>
      <bits name="rMAJOR_REV" pos="15:8" access="r" rst="0">
        <comment>MAJOR Revision</comment>
      </bits>
    </reg32>
  </module>
</archive>

<archive relative = "nb_ds_bsel.xml">
  <module name="nb_ds_bsel" category="NBIOT_PHY">
    <reg32 name="rDS_BSEL_START" protect="w1c">
      <bits name="rDS_BSEL_START" pos="0" access="w1c" rst="0x0">
        <comment>DS_BSEL accelerator start</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_BSEL_CTRL" protect="rw">
      <bits name="rTIMEOUT_VAL" pos="15:0" access="rw" rst="0x7fff">
        <comment>Maximum time out value for TX bit level processing in 61.44Mhz unit</comment>
      </bits>
      <bits name="rNUM_CANDIDATE" pos="17:16" access="rw" rst="0">
        <comment>Number of Candidate
0: 1 candidate
1: 2 candidate
2: 3 candidate
3: 4 candidate</comment>
      </bits>
      <bits name="rDBSP_EN" pos="18" access="rw" rst="0">
        <comment>Bit de-selection and combining
0: Disable
1: enable
Remark: When this bit is disabled, the output data number is equal to rDESCR_SIZE0 and it only support 1 candidate.</comment>
      </bits>
      <bits name="rDESCR_EN" pos="19" access="rw" rst="0">
        <comment>Descramble enable
0: Disable
1: enable</comment>
      </bits>
      <bits name="rNCB_MINUS_SIZE" pos="27:20" access="rw" rst="0">
        <comment>NCB minus:  NCB - 3ND</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X1_0" protect="rw">
      <bits name="rDS_X1_0" pos="30:0" access="rw" rst="0">
        <comment>Descramble X1 value for candidate 0</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X1_1" protect="rw">
      <bits name="rDS_X1_1" pos="30:0" access="rw" rst="0">
        <comment>Descramble X1 value for candidate 1</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X1_2" protect="rw">
      <bits name="rDS_X1_2" pos="30:0" access="rw" rst="0">
        <comment>Descramble X1 value for candidate 2</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X1_3" protect="rw">
      <bits name="rDS_X1_3" pos="30:0" access="rw" rst="0x40">
        <comment>Descramble X1 value for candidate 3</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X2_0" protect="rw">
      <bits name="rDS_X2_0" pos="30:0" access="rw" rst="0">
        <comment>Descramble X2 value for candidate 0</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X2_1" protect="rw">
      <bits name="rDS_X2_1" pos="30:0" access="rw" rst="0">
        <comment>Descramble X2 value for candidate 1</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X2_2" protect="rw">
      <bits name="rDS_X2_2" pos="30:0" access="rw" rst="0">
        <comment>Descramble X2 value for candidate 2</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_X2_3" protect="rw">
      <bits name="rDS_X2_3" pos="30:0" access="rw" rst="0x40">
        <comment>Descramble X2 value for candidate 3</comment>
      </bits>
    </reg32>
    <reg32 name="rDESR_CFG1" protect="rw">
      <bits name="rDESR_SIZE0" pos="8:0" access="rw" rst="0">
        <comment>Descramble size 0</comment>
      </bits>
      <bits name="rDESR_SIZE1" pos="24:16" access="rw" rst="0">
        <comment>Descramble size 1</comment>
      </bits>
    </reg32>
    <reg32 name="rDESR_CFG2" protect="rw">
      <bits name="rDESR_SIZE3" pos="8:0" access="rw" rst="0">
        <comment>Descramble size 3</comment>
      </bits>
      <bits name="rDESR_SIZE2" pos="24:16" access="rw" rst="0">
        <comment>Descramble size 2</comment>
      </bits>
    </reg32>
    <reg32 name="rDESR_CFG3" protect="rw">
      <bits name="rDESR_IBUF_START_ADDR_0" pos="9:0" access="rw" rst="0">
        <comment>Descramble input buffer start address 0</comment>
      </bits>
      <bits name="rDESR_IBUF_START_ADDR_1" pos="25:16" access="rw" rst="0">
        <comment>Descramble input buffer start address 1</comment>
      </bits>
    </reg32>
    <reg32 name="rDESR_CFG4" protect="rw">
      <bits name="rDESR_IBUF_START_ADDR_3" pos="9:0" access="rw" rst="0">
        <comment>Descramble input buffer start address 3</comment>
      </bits>
      <bits name="rDESR_IBUF_START_ADDR_2" pos="25:16" access="rw" rst="0">
        <comment>Descramble input buffer start address 4</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_BSEL_OMEM_START_ADDR" protect="rw">
      <bits name="rDS_BSEL_OMEM_START_ADDR" pos="9:0" access="rw" rst="0">
        <comment>DS_BSEL output memory start address</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_BSEL_DS_X1" protect="r">
      <bits name="rDS_BSEL_DS_X1" pos="30:0" access="r" rst="0">
        <comment>The last candidate Descramble X2 state value</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_BSEL_DS_X2" protect="r">
      <bits name="rDS_BSEL_DS_X2" pos="30:0" access="r" rst="0">
        <comment>The last candidate Descramble X2 state value</comment>
      </bits>
    </reg32>
    <reg32 name="rDS_BSEL_STATUS" protect="r">
      <bits name="rDone" pos="0" access="wc" rst="0">
        <comment>(This bit is write 1 clear)
0: No Done
1: Done</comment>
      </bits>
      <bits name="rOverwritten" pos="1" access="r" rst="0">
        <comment>If Done bit would not clear before this engine re-engine would indicate overwritten output buffer
0: Normal
1: Error</comment>
      </bits>
      <bits name="rBUS_Error" pos="3:2" access="r" rst="0">
        <comment>0: Normal
1: Error
Bit 0: DSP control bus error
Bit 1: accelerator memory access collusion</comment>
      </bits>
      <bits name="rTimeout" pos="4" access="r" rst="0">
        <comment>0: Normal
1: Error</comment>
      </bits>
    </reg32>
  </module>
</archive>

<archive relative = "nb_fft_rsrp.xml">
  <module name="nb_fft_rsrp" category="NBIOT_PHY">
    <reg32 name="rFFT_CTRL" protect="rw">
      <bits name="rFFT_EN" pos="0" access="rw" rst="0x0">
        <comment>FFT calculation enable</comment>
      </bits>
      <bits name="rFFT_DONE_INT_PERIOD" pos="1" access="rw" rst="0x0">
        <comment>the period of FFT done interrupt, 0: one time per-subframe; 1: twice per-subframe.</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_RSRP_CFG" protect="rw">
      <bits name="rFFT_RSRP_EN" pos="0:0" access="rw" rst="0x0">
        <comment>FFT/RSRP enable</comment>
      </bits>
      <bits name="rSCALING_ALPHA" pos="3:1" access="rw" rst="0x3">
        <comment>FFT result scaling</comment>
      </bits>
      <bits name="rFFT_RSRP_MODE" pos="4" access="rw" rst="0x0">
        <comment>0: FFT disabled, 5 RSRP CELLs calculation mode; 1:  FFT + 2 RSRP Cell calculation mode.</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_OFDM_CP_OS" protect="rw">
      <bits name="rFFT_OFDM_CP_OS" pos="3:0" access="rw" rst="0x0">
        <comment>FFT OFDM symbol CP offset</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_CELL_EN" protect="rw">
      <bits name="rRSRP_CELL0_EN" pos="0" access="rw" rst="0">
        <comment>RSRP Cell0 Enabled.</comment>
      </bits>
      <bits name="rRSRP_CELL1_EN" pos="1" access="rw" rst="0">
        <comment>RSRP Cell1 Enabled.</comment>
      </bits>
      <bits name="rRSRP_CELL2_EN" pos="2" access="rw" rst="0">
        <comment>RSRP Cell2 Enabled.</comment>
      </bits>
      <bits name="rRSRP_CELL3_EN" pos="3" access="rw" rst="0">
        <comment>RSRP Cell3 Enabled.</comment>
      </bits>
      <bits name="rRSRP_CELL4_EN" pos="4" access="rw" rst="0">
        <comment>RSRP Cell4 Enabled.</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_CELL0_START_POS" protect="rw">
      <bits name="rRSRP_CELL0_START_POS" pos="14:0" access="rw" rst="0">
        <comment>Frame start position of RSRP Cell0 based on global timer.</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_CELL1_START_POS" protect="rw">
      <bits name="rRSRP_CELL1_START_POS" pos="14:0" access="rw" rst="0">
        <comment>Frame start position of RSRP Cell1 based on global timer.</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_CELL2_START_POS" protect="rw">
      <bits name="rRSRP_CELL2_START_POS" pos="14:0" access="rw" rst="0">
        <comment>Frame start position of RSRP Cell2 based on global timer.</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_CELL3_START_POS" protect="rw">
      <bits name="rRSRP_CELL3_START_POS" pos="14:0" access="rw" rst="0">
        <comment>Frame start position of RSRP Cell3 based on global timer.</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_CELL4_START_POS" protect="rw">
      <bits name="rRSRP_CELL4_START_POS" pos="14:0" access="rw" rst="0">
        <comment>Frame start position of RSRP Cell4 based on global timer.</comment>
      </bits>
    </reg32>
    <reg32 name="rCELL0_OFDM_CP_OS" protect="rw">
      <bits name="rCELL0_OFDM_CP_OS" pos="3:0" access="rw" rst="0">
        <comment>OFDM symbol CP offset for NCELL0.</comment>
      </bits>
    </reg32>
    <reg32 name="rCELL1_OFDM_CP_OS" protect="rw">
      <bits name="rCELL1_OFDM_CP_OS" pos="3:0" access="rw" rst="0">
        <comment>OFDM symbol CP offset for NCELL1.</comment>
      </bits>
    </reg32>
    <reg32 name="rCELL2_OFDM_CP_OS" protect="rw">
      <bits name="rCELL2_OFDM_CP_OS" pos="3:0" access="rw" rst="0">
        <comment>OFDM symbol CP offset for NCELL2.</comment>
      </bits>
    </reg32>
    <reg32 name="rCELL3_OFDM_CP_OS" protect="rw">
      <bits name="rCELL3_OFDM_CP_OS" pos="3:0" access="rw" rst="0">
        <comment>OFDM symbol CP offset for NCELL3.</comment>
      </bits>
    </reg32>
    <reg32 name="rCELL4_OFDM_CP_OS" protect="rw">
      <bits name="rCELL4_OFDM_CP_OS" pos="3:0" access="rw" rst="0">
        <comment>OFDM symbol CP offset for NCELL4.</comment>
      </bits>
    </reg32>
    <reg32 name="rNCELL_V_SHIFT" protect="rw">
      <bits name="rNCELL0_V_SHIFT" pos="2:0" access="rw" rst="0">
        <comment>vshift of NCELL0.</comment>
      </bits>
      <bits name="rNCELL1_V_SHIFT" pos="5:3" access="rw" rst="0">
        <comment>vshift of NCELL1.</comment>
      </bits>
      <bits name="rNCELL2_V_SHIFT" pos="8:6" access="rw" rst="0">
        <comment>vshift of NCELL2.</comment>
      </bits>
      <bits name="rNCELL3_V_SHIFT" pos="11:9" access="rw" rst="0">
        <comment>vshift of NCELL3.</comment>
      </bits>
      <bits name="rNCELL4_V_SHIFT" pos="14:12" access="rw" rst="0">
        <comment>vshift of NCELL4.</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_SUBF_IDX" protect="rw">
      <bits name="rNCELL0_CFG_SUBF_IDX" pos="3:0" access="rw" rst="0">
        <comment>confiugred subframe idx when RSRX cell enabled.</comment>
      </bits>
      <bits name="rNCELL1_CFG_SUBF_IDX" pos="7:4" access="rw" rst="0">
        <comment>confiugred subframe idx when RSRX cell enabled.</comment>
      </bits>
      <bits name="rNCELL2_CFG_SUBF_IDX" pos="11:8" access="rw" rst="0">
        <comment>confiugred subframe idx when RSRX cell enabled.</comment>
      </bits>
      <bits name="rNCELL3_CFG_SUBF_IDX" pos="15:12" access="rw" rst="0">
        <comment>confiugred subframe idx when RSRX cell enabled.</comment>
      </bits>
      <bits name="rNCELL4_CFG_SUBF_IDX" pos="19:16" access="rw" rst="0">
        <comment>confiugred subframe idx when RSRX cell enabled.</comment>
      </bits>
    </reg32>
    <reg32 name="rRSRP_MEM_BADDR" protect="rw">
      <bits name="rRSRP_MEM_BADDR" pos="8:0" access="rw" rst="0">
        <comment>Offset address for RSRP write memory buffer.</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_RSRP_STATUS" protect="r">
      <bits name="RESERVED" pos="0" access="rw" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rFFT_BUF_STATUS" pos="2:1" access="w1c" rst="0">
        <comment>Indicated whether the data in ping-pong buffer is updated.</comment>
      </bits>
      <bits name="rFFT_BUF_SWITCH_STATUS" pos="3" access="r" rst="0">
        <comment>FFT buffer ping-pong flag</comment>
      </bits>
      <bits name="rNCELL0_TRIPLE_BUF_STATUS" pos="6:4" access="w1c" rst="0">
        <comment>Indicated which triple buffer is UPDATED</comment>
      </bits>
      <bits name="rNCELL0_TRIPLE_BUF_SWITCH_FLAG" pos="8:7" access="r" rst="3">
        <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
      </bits>
      <bits name="rNCELL1_TRIPLE_BUF_STATUS" pos="11:9" access="w1c" rst="0">
        <comment>Indicated which triple buffer is UPDATED</comment>
      </bits>
      <bits name="rNCELL1_TRIPLE_BUF_SWITCH_FLAG" pos="13:12" access="r" rst="3">
        <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
      </bits>
      <bits name="rNCELL2_TRIPLE_BUF_STATUS" pos="16:14" access="w1c" rst="0">
        <comment>Indicated which triple buffer is UPDATED</comment>
      </bits>
      <bits name="rNCELL2_TRIPLE_BUF_SWITCH_FLAG" pos="18:17" access="r" rst="3">
        <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
      </bits>
      <bits name="rNCELL3_TRIPLE_BUF_STATUS" pos="21:19" access="w1c" rst="0">
        <comment>Indicated which triple buffer is UPDATED</comment>
      </bits>
      <bits name="rNCELL3_TRIPLE_BUF_SWITCH_FLAG" pos="23:22" access="r" rst="3">
        <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
      </bits>
      <bits name="rNCELL4_TRIPLE_BUF_STATUS" pos="26:24" access="w1c" rst="0">
        <comment>Indicated which triple buffer is UPDATED</comment>
      </bits>
      <bits name="rNCELL4_TRIPLE_BUF_SWITCH_FLAG" pos="28:27" access="r" rst="3">
        <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
      </bits>
    </reg32>
    <reg32 name="rSV_CELL_SUBF_IDX" protect="r">
      <bits name="rSV_CELL_SUBF_IDX" pos="3:0" access="r" rst="0">
        <comment>subframe index of serving cell</comment>
      </bits>
    </reg32>
    <reg32 name="rNCELL_SUBF_IDX" protect="r">
      <bits name="rNCELL0_SUBF_IDX" pos="3:0" access="r" rst="0">
        <comment>subframe idx of NCELL0</comment>
      </bits>
      <bits name="rNCELL1_SUBF_IDX" pos="7:4" access="r" rst="0">
        <comment>subframe idx of NCELL1</comment>
      </bits>
      <bits name="rNCELL2_SUBF_IDX" pos="11:8" access="r" rst="0">
        <comment>subframe idx of NCELL2</comment>
      </bits>
      <bits name="rNCELL3_SUBF_IDX" pos="15:12" access="r" rst="0">
        <comment>subframe idx of NCELL3</comment>
      </bits>
      <bits name="rNCELL4_SUBF_IDX" pos="19:16" access="r" rst="0">
        <comment>subframe idx of NCELL4</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_RSRP_BUF_OVWR" protect="r">
      <bits name="rFFT_BUF_OVWR" pos="1:0" access="r" rst="0">
        <comment>FFT pingpong buffer overwritten status</comment>
      </bits>
      <bits name="rRSRP_CELL0_BUF_OVWR" pos="4:2" access="r" rst="0">
        <comment>RSRP Cell0 triple buffer over-written status.</comment>
      </bits>
      <bits name="rRSRP_CELL1_BUF_OVWR" pos="7:5" access="r" rst="0">
        <comment>RSRP Cell1 triple buffer over-written status.</comment>
      </bits>
      <bits name="rRSRP_CELL2_BUF_OVWR" pos="10:8" access="r" rst="0">
        <comment>RSRP Cell2 triple buffer over-written status.</comment>
      </bits>
      <bits name="rRSRP_CELL3_BUF_OVWR" pos="13:11" access="r" rst="0">
        <comment>RSRP Cell3 triple buffer over-written status.</comment>
      </bits>
      <bits name="rRSRP_CELL4_BUF_OVWR" pos="16:14" access="r" rst="0">
        <comment>RSRP Cell4 triple buffer over-written status.</comment>
      </bits>
      <bits name="rFFT_MEM_WR_ERR" pos="18:17" access="r" rst="0">
        <comment>FFT write buffer bus error</comment>
      </bits>
      <bits name="rRSRP0_MEM_WR_ERR" pos="20:19" access="r" rst="0">
        <comment>RSRP CELL0 write buffer bus error</comment>
      </bits>
      <bits name="rRSRP1_MEM_WR_ERR" pos="22:21" access="r" rst="0">
        <comment>RSRP CELL1 write buffer bus error</comment>
      </bits>
      <bits name="rRSRP2_MEM_WR_ERR" pos="24:23" access="r" rst="0">
        <comment>RSRP CELL2 write buffer bus error</comment>
      </bits>
      <bits name="rRSRP3_MEM_WR_ERR" pos="26:25" access="r" rst="0">
        <comment>RSRP CELL3 write buffer bus error</comment>
      </bits>
      <bits name="rRSRP4_MEM_WR_ERR" pos="28:27" access="r" rst="0">
        <comment>RSRP CELL4 write buffer bus error</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_RSRP_BUF_IDX" protect="r">
      <bits name="rFFT_PINGPONG_BUF_IDX" pos="0" access="r" rst="0">
        <comment>FFT pingpong buf idx</comment>
      </bits>
      <bits name="rRSRP0_TRI_BUF_IDX" pos="2:1" access="r" rst="0">
        <comment>RSRP0 Triple buffer idx</comment>
      </bits>
      <bits name="rRSRP1_TRI_BUF_IDX" pos="4:3" access="r" rst="0">
        <comment>RSRP1 Triple buffer idx</comment>
      </bits>
      <bits name="rRSRP2_TRI_BUF_IDX" pos="6:5" access="r" rst="0">
        <comment>RSRP2 Triple buffer idx</comment>
      </bits>
      <bits name="rRSRP3_TRI_BUF_IDX" pos="8:7" access="r" rst="0">
        <comment>RSRP3 Triple buffer idx</comment>
      </bits>
      <bits name="rRSRP4_TRI_BUF_IDX" pos="10:9" access="r" rst="0">
        <comment>RSRP4 Triple buffer idx</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_RSRP_SUBF_IDX" protect="r">
      <bits name="rFFT_SUBF_IDX" pos="3:0" access="r" rst="0">
        <comment>FFT subframe idx</comment>
      </bits>
      <bits name="rRSRP0_SUBF_IDX" pos="7:4" access="r" rst="0">
        <comment>RSRP Cell0 subframe idx</comment>
      </bits>
      <bits name="rRSRP1_SUBF_IDX" pos="11:8" access="r" rst="0">
        <comment>RSRP Cell1 subframe idx</comment>
      </bits>
      <bits name="rRSRP2_SUBF_IDX" pos="15:12" access="r" rst="0">
        <comment>RSRP Cell2 subframe idx</comment>
      </bits>
      <bits name="rRSRP3_SUBF_IDX" pos="19:16" access="r" rst="0">
        <comment>RSRP Cell3 subframe idx</comment>
      </bits>
      <bits name="rRSRP4_SUBF_IDX" pos="23:20" access="r" rst="0">
        <comment>RSRP Cell4 subframe idx</comment>
      </bits>
    </reg32>
  </module>
</archive>

<archive relative = "nb_intc.xml">
  <module name="nb_intc" category="NBIOT_PHY">
    <reg32 name="rRX_INT_DSP_MASKING" protect="rw">
      <bits name="rRX_INT_DSP_MASKING" pos="0:0" access="rw" rst="0x0">
        <comment>Interrupt Masking bit for RX_INT_DSP</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_INT_MCU_MASKING" protect="rw">
      <bits name="rRX_INT_MCU_MASKING" pos="0:0" access="rw" rst="0x0">
        <comment>Interrupt Masking bit for RX_INT_MCU</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_INT_DSP_MASKING" protect="rw">
      <bits name="rTX_INT_DSP_MASKING" pos="0:0" access="rw" rst="0x0">
        <comment>Interrupt Masking bit for TX_INT_DSP</comment>
      </bits>
    </reg32>
    <reg32 name="rACC_INT_MASKING" protect="rw">
      <bits name="rFFT_DONE_INT_MASKING" pos="0:0" access="rw" rst="0">
        <comment>Interrupt masking bit from the interrupt of fft_done_int</comment>
      </bits>
      <bits name="rNCELL0_RSRP_DEC_DONE_INT_MASKING" pos="1:1" access="rw" rst="0">
        <comment>Interrupt masking bit of NCELL0 decode done intterupt</comment>
      </bits>
      <bits name="rNCELL1_RSRP_DEC_DONE_INT_MASKING" pos="2:2" access="rw" rst="0">
        <comment>Interrupt masking bit of NCELL1 decode done interrupt</comment>
      </bits>
      <bits name="rNCELL2_RSRP_DEC_DONE_INT_MASKING" pos="3:3" access="rw" rst="0">
        <comment>Interrupt masking bit of NCELL2 decode done interrpt</comment>
      </bits>
      <bits name="rNCELL3_RSRP_DEC_DONE_INT_MASKING" pos="4:4" access="rw" rst="0">
        <comment>Interrupt masking bit of NCELL3 decode done interrupt</comment>
      </bits>
      <bits name="rNCELL4_RSRP_DEC_DONE_INT_MASKING" pos="5:5" access="rw" rst="0">
        <comment>Interrupt masking bit of NCELL4 decode done interrupt</comment>
      </bits>
      <bits name="rPSS_SF_DONE_INT_MASKING" pos="6:6" access="rw" rst="0">
        <comment>Interrupt masking bit of PSS SF done interrupt</comment>
      </bits>
      <bits name="rSSS_SF_DONE_INT_MASKING" pos="7:7" access="rw" rst="0">
        <comment>Interrupt masking bit of SSS SF done interrupt</comment>
      </bits>
      <bits name="rCFO_SF_DONE_INT_MASKING" pos="8:8" access="rw" rst="0">
        <comment>Interrupt masking bit of CFO SF done interrupt</comment>
      </bits>
      <bits name="rVIT_DEC_DONE_INT_MASKING" pos="9:9" access="rw" rst="0">
        <comment>Interrupt masking bit of Viterbi decode done interrupt</comment>
      </bits>
      <bits name="rAGC_PWR_INT_MASKING" pos="10:10" access="rw" rst="0">
        <comment>Interrupt masking bit of AGC interrupt masking</comment>
      </bits>
      <bits name="rDS_BSEL_INT_MASKING" pos="11:11" access="rw" rst="0">
        <comment>Interrupt masking bit of DS_BSEL interrupt</comment>
      </bits>
      <bits name="rPUSCH_ENC_INT_MASKING" pos="12:12" access="rw" rst="0">
        <comment>Interrupt masking bit of PUSCH encoder interrupt</comment>
      </bits>
      <bits name="rTX_CHSC_INT_MASKING" pos="13:13" access="rw" rst="0">
        <comment>Interrupt masking bit of TX_CHSC interrupt</comment>
      </bits>
      <bits name="rFFT_512_DONE_INT_MASKING" pos="14:14" access="rw" rst="0">
        <comment>Interrupt masking bit of FFT_512 done interrupt</comment>
      </bits>
      <bits name="rNPRS_ACC1_DONE_INT_MASKING" pos="15:15" access="rw" rst="0">
        <comment>Interrupt masking bit of NPRS_ACC1 done interrupt</comment>
      </bits>
      <bits name="rFINE_IFFT_DONE_INT_MASKING" pos="16:16" access="rw" rst="0">
        <comment>Interrupt masking bit of FINE_IFFT done interrupt</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_INT_DSP_STATUS" protect="w1c">
      <bits name="rRX_INT_DSP_STATUS" pos="0" access="w1c" rst="0">
        <comment>interrupt status of RX_INT_DSP, write 1 clear.</comment>
      </bits>
    </reg32>
    <reg32 name="rRX_INT_MCU_STATUS" protect="w1c">
      <bits name="rRX_INT_MCU_STATUS" pos="0:0" access="w1c" rst="0">
        <comment>Interrupt status of RX_INT_MCU, write 1 clear.</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_INT_DSP_STATUS" protect="w1c">
      <bits name="rTX_INT_DSP_STATUS" pos="0:0" access="w1c" rst="0">
        <comment>Interrupt status of TX_INT_DSP, write 1 clear.</comment>
      </bits>
    </reg32>
    <reg32 name="rACC_INT_STATUS" protect="w1c">
      <bits name="rFFT_INT_STATUS" pos="0:0" access="w1c" rst="0">
        <comment>Interrupt status of fft_sf_done_int</comment>
      </bits>
      <bits name="rNCELL0_RSRP_DEC_DONE_INT_STATUS" pos="1:1" access="w1c" rst="0">
        <comment>Interrupt status of RSRP Cell0 decode done interrupt</comment>
      </bits>
      <bits name="rNCELL1_RSRP_DEC_DONE_INT_STATUS" pos="2" access="w1c" rst="0">
        <comment>Interrupt status of RSRP Cell1 decode done interrupt</comment>
      </bits>
      <bits name="rNCELL2_RSRP_DEC_DONE_INT_STATUS" pos="3" access="w1c" rst="0">
        <comment>Interrupt status of RSRP Cell20 decode done interrupt</comment>
      </bits>
      <bits name="rNCELL3_RSRP_DEC_DONE_INT_STATUS" pos="4" access="w1c" rst="0">
        <comment>Interrupt status of RSRP Cell3 decode done interrupt</comment>
      </bits>
      <bits name="rNCELL4_RSRP_DEC_DONE_INT_STATUS" pos="5" access="w1c" rst="0">
        <comment>Interrupt status of RSRP Cell4 decode done interrupt</comment>
      </bits>
      <bits name="rPSS_SF_DONE_INT_STATUS" pos="6" access="w1c" rst="0">
        <comment>Interrupt status of PSS SF done interrupt</comment>
      </bits>
      <bits name="rSSS_SF_DONE_INT_STATUS" pos="7" access="w1c" rst="0">
        <comment>Interrupt status of SSS SF done interrupt</comment>
      </bits>
      <bits name="rCFO_SF_DONE_INT_STATUS" pos="8" access="w1c" rst="0">
        <comment>Interrupt status of CFO SF done interrupt</comment>
      </bits>
      <bits name="rVIT_DEC_DONE_INT_STATUS" pos="9" access="w1c" rst="0">
        <comment>Interrupt status of Viterbi decode done</comment>
      </bits>
      <bits name="rAGC_INT_STATUS" pos="10" access="w1c" rst="0">
        <comment>Interrupt status of AGC interrupt</comment>
      </bits>
      <bits name="rDS_BSEL_INT_STATUS" pos="11" access="w1c" rst="0">
        <comment>Interrupt status of DS_BSEL interrupt</comment>
      </bits>
      <bits name="rPUSCH_ENC_INT_STATUS" pos="12" access="w1c" rst="0">
        <comment>Interrupt status of PUSCH Encoder interrupt</comment>
      </bits>
      <bits name="rTX_CHSC_INT_STATUS" pos="13" access="w1c" rst="0">
        <comment>Interrupt status of TX_CHSC interrupt</comment>
      </bits>
      <bits name="rFFT_512_DONE_INT_STATUS" pos="14" access="w1c" rst="0">
        <comment>Interrupt status of FFT_512 done interrupt</comment>
      </bits>
      <bits name="rNPRS_ACC1_DONE_INT_STATUS" pos="15" access="w1c" rst="0">
        <comment>Interrupt status of NPRS_ACC1 done interrupt</comment>
      </bits>
      <bits name="rFINT_IFFT_DONE_INT_STATUS" pos="16" access="w1c" rst="0">
        <comment>Interrupt status of FINE IFFT done interrupt</comment>
      </bits>
    </reg32>
  </module>
</archive>

<archive relative = "nb_meas.xml">
  <module name="nb_meas" category="NBIOT_PHY">
    <reg32 name="rASP_ON" protect="w">
      <bits name="rASP_ON" pos="0" access="w" rst="0">
        <comment>Symbol power accumulation enable/disable signal and effective at subframe boundary.
      1 : enable
      0 : disable</comment>
      </bits>
    </reg32>
    <reg32 name="rASP_CTRL" protect="rw">
      <bits name="rASP_GAIN" pos="12:9" access="rw" rst="0">
        <comment>Gain used in shift and saturation of accumulation power value.
Bit[3:0]	Gain
0000	        2^-24 (default)
0001	        2^-23 
0010	        2^-22
0011	        2^-21</comment>
      </bits>
      <bits name="rASP_LENGTH" pos="8:7" access="rw" rst="0">
        <comment>Accumulation length of samples in every symbol.
    0: 128   
    1: 64
    2: 32
    3: 16</comment>
      </bits>
      <bits name="rASP_OFFSET" pos="6:0" access="rw" rst="0">
        <comment>Offset of samples from symbols' boundaries which is the start boundary of agc symbol power calculation.</comment>
      </bits>
    </reg32>
    <reg32 name="rASP_RD_ADDR" protect="rw">
      <bits name="rASP_RD_ADDR" pos="5:0" access="rw" rst="0">
        <comment>Reading address for DSP to read asp response ram, and this register would auto-increment whenever access the 'rASP_RD_DATA' register
PING buffer address: 0~20
PONG buffer address: 21~41
</comment>
      </bits>
    </reg32>
    <reg32 name="rDC_OFS_CFG_DATA" protect="rw">
      <bits name="rDC_OFS_CFG_DATA" pos="31:0" access="rw" rst="0">
        <comment>Bit[27:16]: Q DC offset configuration
Bit[11:0]:   I DC offset configuration
</comment>
      </bits>
    </reg32>
    <hole size="7*32"></hole>
    <reg32 name="rASP_STATUS" protect="r">
      <bits name="rASP_DONE_STATUS" pos="0" access="w1c" rst="0">
        <comment>Report agc symbol power and DCC done status, write '1' to clear this status</comment>
      </bits>
      <bits name="rASP_BUF_PING_PONG_IDX" pos="1" access="r" rst="0">
        <comment>Index bit to indicate which buffer is updated of PING-PONG   
1: PONG buffer data is updated
0: PING buffer data is updated</comment>
      </bits>
    </reg32>
    <reg32 name="rASP_RD_DATA" protect="r">
      <bits name="rASP_RD_DATA" pos="31:0" access="r" rst="0">
        <comment>Data = mem[rASP_RD_ADDR] which is the ASP response memory data content. The ASP_RD_ADDR would auto increase whenever access this register. 
ASP response Memory address range is 0-41
Address(0~6,21~27): symbol power, bit[15:0] for symbol 0,2,4,6,8,10,12 and bit[31:16] for symbol 1,3,5,7,9,11,13
Address(7~20,28~41):dc_offset value, bit[15:0] for I and bit[31:16] for Q
</comment>
      </bits>
    </reg32>
    <hole size="51*32"></hole>
    <reg32 name="rFFT_512_CTRL" protect="rw">
      <bits name="rFFT_FWD_INV" pos="0" access="rw" rst="0">
        <comment>Forward/Inverse FFT transform computing selection</comment>
      </bits>
      <bits name="rFFT_BUF_IDX" pos="1" access="rw" rst="0">
        <comment>PING-PONG memory selection
1'b0: Memory0;
1'b1: Memory1.</comment>
      </bits>
      <bits name="rFFT_SCALING_FACTOR" pos="4:2" access="rw" rst="0">
        <comment>alphaFFT scaling, it can be implemented by bit shift,
3'd0: 2^-3
3'd1: 2^-2
3'd2: 2^-1
3'd3: 2^0  (default)
3'd4: 2^1
3'd5: 2^2
3'd6: 2^3
3'd7: 2^4
</comment>
      </bits>
      <bits name="rFFT_AMP_SCALING_FACTOR" pos="7:5" access="rw" rst="0">
        <comment>alphaFFT_amp_out scaling for amplitude square output, it can be implemented by bit shift,
3'd0: 2^-3
3'd1: 2^-2
3'd2: 2^-1
3'd3: 2^0  (default)
3'd4: 2^1
3'd5: 2^2
3'd6: 2^3
3'd7: 2^4 
</comment>
      </bits>
      <bits name="rFFT_AMP_CAL_EN" pos="8" access="rw" rst="0">
        <comment>IFFT Output amptitude data
1'b0: IFFT output normal data(I+j*Q);
1'b1: IFFT output amptitude data(I^2+Q^2).</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_512_START" protect="w">
      <bits name="rFFT_512_START" pos="0" access="w" rst="0">
        <comment>FFT start indication, when write 1 to this register, a high active pulse will be generated and input to FFT engine to start FFT calculation.</comment>
      </bits>
    </reg32>
    <reg32 name="rFFT_512_STATUS" protect="r">
      <bits name="rFFT_DONE" pos="0" access="w1c" rst="0">
        <comment>FFT done status, write 1 clear.</comment>
      </bits>
      <bits name="rMEM_BUS_ERR" pos="2:1" access="r" rst="0">
        <comment>An error grant is received when FFT request memory write bus to store FFT result. 
Bit1: DSP control error;
Bit0: Accelerator memory access error.</comment>
      </bits>
      <bits name="rFFT_IN_UNDERFLOW" pos="3" access="r" rst="0">
        <comment>This register is used to check the range of FFT/IFFT input,  
1'b1: absolute maximum FFT/IFFT input less than 32, in this case, the resolution of FFT/IFFT output will loss 1bit;
1'b0: normally.
</comment>
      </bits>
    </reg32>
    <hole size="61*32"></hole>
    <reg32 name="rNPRS_ACC1_START" protect="w">
      <bits name="rNPRS_ACC1_START" pos="0" access="w" rst="0">
        <comment>NPRS accelerator 1 Start</comment>
      </bits>
    </reg32>
    <reg32 name="rNPRS_ACC1_CTRL" protect="rw">
      <bits name="rTIMEOUT_VAL" pos="15:0" access="rw" rst="0x7ff">
        <comment>Maximum time out value in 61.44Mhz unit</comment>
      </bits>
      <bits name="rMODE" pos="17:16" access="rw" rst="0">
        <comment>Mode selection:
2'b00: copy + dot product
2'b01: dot product 
2'b10: copy</comment>
      </bits>
      <bits name="rCP_SRC_MEM" pos="18" access="rw" rst="0">
        <comment>Copy Source memory before sequence dot product
0: Memory 0
1: Memory 1</comment>
      </bits>
      <bits name="rCP_BR_ADDR_EN" pos="19" access="rw" rst="0">
        <comment>Copy memory with bit-reversed address write location enable
0: Disable
1: Enable</comment>
      </bits>
      <bits name="rDP_DST_MEM" pos="20" access="rw" rst="0">
        <comment>Destination memory after sequence dot product
0: Memory 0
1: Memory 1</comment>
      </bits>
      <bits name="rDP_BR_ADDR_EN" pos="21" access="rw" rst="0">
        <comment>Dot Product from memory 5 to memory 0/1 with bit-reversed address write location enable
0: Disable
1: Enable</comment>
      </bits>
      <bits name="rCONJ_SEQ_EN" pos="22" access="rw" rst="0">
        <comment>Conjugate Sequence data Enable
0: Disable
1: Enable</comment>
      </bits>
    </reg32>
    <reg32 name="rNPRS_ACC1_LEN" protect="rw">
      <bits name="rNPRS_ACC1_LEN" pos="8:0" access="rw" rst="0x1ff">
        <comment>Operation length -1 
Default : (511)</comment>
      </bits>
    </reg32>
    <reg32 name="rSEQ_START_OFS_ADDR" protect="rw">
      <bits name="rSEQ_START_OFS_ADDR" pos="10:0" access="rw" rst="0">
        <comment>Sequence Memory Start Offset Address</comment>
      </bits>
    </reg32>
    <reg32 name="rNPRS_ACC1_STATUS" protect="r">
      <bits name="rDone" pos="0" access="w1c" rst="0">
        <comment>(This bit is read write 1 clear)
0: No Done
1: Done</comment>
      </bits>
      <bits name="rOverwritten" pos="1" access="r" rst="0">
        <comment>If Done bit would not clear before this engine re-engine would indicate overwritten output buffer
0: Normal
1: Error</comment>
      </bits>
      <bits name="rBUS Error 0" pos="3:2" access="r" rst="0">
        <comment>Read/Write process in Memory 0/1 (FFT/IFFT input/output memory)
0: Normal
1: Error
Bit 0: DSP control bus error
Bit 1: accelerator memory access collusion</comment>
      </bits>
      <bits name="rBUS Error 1" pos="5:4" access="r" rst="0">
        <comment>Read/Write process in Memory 5 (Copied FFT memory)</comment>
      </bits>
      <bits name="rBUS Error 2" pos="7:6" access="r" rst="0">
        <comment>Read process in Memory 4 (Sequence memory)</comment>
      </bits>
      <bits name="rTimeout" pos="8" access="r" rst="0">
        <comment>0: Normal
1: Error</comment>
      </bits>
    </reg32>
    <hole size="59*32"></hole>
    <reg32 name="rFINE_IFFT_START" protect="w">
      <bits name="rFINE_IFFT_START" pos="0" access="w" rst="0">
        <comment>Fine IFFT START
A pulse to grigger the Fine IFFT</comment>
      </bits>
    </reg32>
    <reg32 name="rFINE_IFFT_CALC_CTRL" protect="rw">
      <bits name="rFINE_IFFT_T" pos="8:0" access="rw" rst="0">
        <comment>NPRS Coarse Timing Result  
Range is from 0 to 272</comment>
      </bits>
      <bits name="rFINE_IFFT_CALC_OS" pos="22:16" access="rw" rst="0">
        <comment>Fine IFFT calculation offset. Range is from 0 to 95.</comment>
      </bits>
      <bits name="rFINE_IFFT_CALC_LEN" pos="30:24" access="rw" rst="0">
        <comment>Fine IFFT calculation length. Range is from 1 to 96.</comment>
      </bits>
    </reg32>
    <reg32 name="rFINE_IFFT_IOOUT_CTRL" protect="rw">
      <bits name="rFINE_IFFT_OUT_IQ_SCALE" pos="2:0" access="rw" rst="0">
        <comment>Fine IFFT output a+bj scaling
3'd0:x2^0(default)
3'd1:x2^-1
3'd2:x2^-2
3'd3:x2^-3
3'd4:x2^-4
3'd5:x2^-5
3'd6:x2^-6
3'd7:x2^-7
</comment>
      </bits>
      <bits name="rFINE_IFFT_OUT_PWR_SCALE" pos="10:8" access="rw" rst="0">
        <comment>Fine IFFT output power scaling
3'd0:x2^-3
3'd1:x2^-2
3'd2:x2^-1
3'd3:x2^0 (default)
3'd4:x2^1
3'd5:x2^2
3'd6:x2^3
3'd7:x2^4</comment>
      </bits>
      <bits name="rFINE_IFFT_OUT_SEL" pos="16" access="rw" rst="0">
        <comment>Fine IFFT output selection
1'b0: Output IFFT result: a+bj
1'b1: Output power result: a^2+b^2</comment>
      </bits>
      <bits name="rFINE_IFFT_IN_CTRL" pos="17" access="rw" rst="0">
        <comment>Fine IFFT input data control
1'b0: Input data in inverse order 
1'b1: Input data in inverse order and swap bit0~bit255 with bit256~bit511</comment>
      </bits>
    </reg32>
    <reg32 name="rFINE_IFFT_INPUT_ADDR" protect="rw">
      <bits name="rFINE_IFFT_INPUT_ADDR" pos="10:0" access="rw" rst="0">
        <comment>Fine IFFT input data start address</comment>
      </bits>
    </reg32>
    <reg32 name="rFINE_IFFT_OUTPUT_ADDR" protect="rw">
      <bits name="rFINE_IFFT_OUTPUT_ADDR" pos="10:0" access="rw" rst="0">
        <comment>Fine IFFT output data start address</comment>
      </bits>
    </reg32>
    <reg32 name="rFINE_IFFT_STATUS" protect="r">
      <bits name="rFINE_IFFT_DONE_STATUS" pos="0" access="w1c" rst="0">
        <comment>Fine IFFT calculation done status.
1'b1: Fine IFFT calculation done
1'b0: Fine IFFT is idle or under calculating</comment>
      </bits>
      <bits name="rFINE_IFFT_OW_STATUS" pos="1" access="w1c" rst="0">
        <comment>Fine IFFT output buffer status
1'b1: Fine IFFT output buffer is over written
1'b0: Fine IFFT output buffer is normal</comment>
      </bits>
      <bits name="rFINE_IFFT_ERR_STATUS" pos="3:2" access="r" rst="0">
        <comment>Fine IFFT calculation done status.
1'b1: Fine IFFT calculation done
1'b0: Fine IFFT is idle or under calculating</comment>
      </bits>
    </reg32>
  </module>
</archive>


<archive relative = "nb_tx_chsc.xml">

<module name="nb_tx_chsc" category="NBIOT_PHY">
 
  <reg32 name="rTX_CHSC_CTRL" protect="rw">
    <bits access="rw" name="rTIMEOUT_VAL" pos="15:0" rst="0x0">
      <comment>Maximum time out value for  TX channel-interleaver and scrambling in 61.44Mhz unit. </comment>
    </bits>
    <bits access="rw" name="rTX_CHSC_START_CTRL" pos="16" rst="0x0">
      <comment>Start control:
                     0: Trigger by SW start
                     1: Trigger by HW start.
      </comment>
    </bits>
    <bits access="rw" name="rCH_INTRLVR_EN" pos="17" rst="0x0">
      <comment>Channel interleaver enable
                     0: Disable
                     1: Enable.
      </comment>
    </bits>
    <bits access="rw" name="rSCR_EN" pos="18" rst="0x0">
      <comment>Scramble enable
                    0: Disable
                    1: Enable.
      </comment>
    </bits>
  </reg32>

  <reg32 name="rTX_CHSC_START" protect="w1c">
    <bits access="w1c" name="rTX_CHSC_START" pos="0" rst="0x0">
        <comment>TX channel-interleaver and scrambling accelerator 2 start. </comment>
    </bits>
  </reg32>
  
  <reg32 name="rMEM_START_ADDR" protect="rw">
    <bits access="rw" name="rBSEL_MEM_START_ADDR" pos="9:0" rst="0x0">
        <comment>Bit selection memory start address. </comment>
    </bits>
    <bits access="rw" name="rSCR_MEM_START_ADDR" pos="25:16" rst="0x0">
        <comment>Scramble memory start output address. </comment>
    </bits>
  </reg32>
  
  <reg32 name="rBSEL_CFG" protect="rw">
    <bits access="rw" name="NCB Minus" pos="14:0" rst="0x0">
        <comment>Ncb minus NCB - 3ND. </comment>
    </bits>
    <bits access="rw" name="rK0_MINUS" pos="30:16" rst="0x0">
        <comment>K0 minus: K0 position without dummy bit.. </comment>
    </bits>
  </reg32>
  
 <reg32 name="rCH_INTRLVR_CFG" protect="rw">
    <bits access="rw" name="rROW_SZ" pos="7:4" rst="0x0">
        <comment>Row size for ch-interleaver. </comment>
    </bits>
    <bits access="rw" name="rMOD_TYPE" pos="8" rst="0x0">
        <comment>Modulation type
                        0: BPSK
                        1: QPSK. 
        </comment>
    </bits>
    <bits access="rw" name="rCOL_SZ_PRE_RSE_UNIT" pos="22:16" rst="0x0">
        <comment>Column size in each resource unit:
                 (NUL_sym-1)* Nul_slot. 
        </comment>
    </bits>
  </reg32>
  
  <reg32 name="rSCR_SIZE" protect="rw">
    <bits access="rw" name="rSCR_SIZE" pos="7:0" rst="0x0">
        <comment>scrambling size in current subframe. </comment>
    </bits>
  </reg32>  
  
  <reg32 name="rSCR_X1" protect="rw">
    <bits access="rw" name="rSCR_X1" pos="30:0" rst="0x0">
        <comment>scrambling X1. </comment>
    </bits>
  </reg32>  

  <reg32 name="rSCR_X2" protect="rw">
    <bits access="rw" name="rSCR_X2" pos="30:0" rst="0x0">
        <comment>scrambling X2. </comment>
    </bits>
  </reg32> 

 <reg32 name="rLAST_SCR_X1" protect="rw">
    <bits access="rw" name="rLAST_SCR_X1" pos="30:0" rst="0x0">
        <comment>Last scrambling state in X1. </comment>
    </bits>
  </reg32> 

 <reg32 name="rLAST_SCR_X2" protect="rw">
    <bits access="rw" name="rLAST_SCR_X2" pos="30:0" rst="0x0">
        <comment>Last scrambling state in X2. </comment>
    </bits>
  </reg32>

 <reg32 name="rTX_CHSC_STATUS" protect="ro">
    <bits access="rw1c" name="Done" pos="0" rst="0x0">
        <comment>(This bit is read write 1 clear)
                   0: No Done
                   1: Done.
        </comment>
    </bits>
    <bits access="ro" name="Overwritten" pos="1" rst="0x0">
        <comment>If Done bit would not clear before this engine re-engine would indicate overwritten output buffer
                              0: Normal
                              1: Error
        </comment>
    </bits>
    <bits access="ro" name="BUS Error" pos="3:2" rst="0x0">
        <comment>0: Normal
                 1: Error
                 Bit 0: DSP control bus error
                 Bit 1: accelerator memory access collusion
        </comment>
    </bits>
    <bits access="ro" name="Timeout " pos="4" rst="0x0">
        <comment>0: Normal
                 1: Error
        </comment>
    </bits>
  </reg32>  
  

</module>

</archive>


<archive relative = "nb_tx_frontend.xml">
  <module name="nb_tx_frontend" category="NBIOT_PHY">
    <reg32 name="rTX_OS" protect="rw">
      <bits name="rPUSCH_OS1" pos="7:0" access="rw" rst="0xb">
        <comment>PUSCH offset1 for 3.75K process delay</comment>
      </bits>
      <bits name="rPUSCH_OS0" pos="15:8" access="rw" rst="0x63">
        <comment>PUSCH offset0 for 15K process delay</comment>
      </bits>
      <bits name="rPRACH_OS" pos="23:16" access="rw" rst="0xb">
        <comment>PRACH offset for process delay</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_TA_VALUE" protect="rw">
      <bits name="rTX_TA_VALUE" pos="10:0" access="rw" rst="0x0">
        <comment>TA Value</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_RACH_START_ADJ" protect="rw">
      <bits name="rTX_RACH_START_ADJ" pos="10:0" access="rw" rst="0x0">
        <comment>the advance time of PRACH start adjustment</comment>
      </bits>
    </reg32>
   <reg32 name="rTX_RF_DELAY" protect="rw">
      <bits name="rTX_RF_DELAY" pos="15:0" access="rw" rst="0x0">
        <comment>RF delay from NBIOT_CORE to chip output</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_EN" protect="rw">
      <bits name="rPUSCH_EN" pos="0" access="rw" rst="0">
        <comment>PUSCH Enable</comment>
      </bits>
      <bits name="rPRACH_EN" pos="1" access="rw" rst="0">
        <comment>PRACH Enable</comment>
      </bits>
    </reg32>
    <reg32 name="rDELTA_CP_ADJ" protect="rw">
      <bits name="rDELTA_CP_ADJ" pos="5:0" access="rw" rst="0">
        <comment>Delta CP adjustment</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_CFG" protect="rw">
      <bits name="rTX_FRM_MODE" pos="0" access="rw" rst="0">
        <comment>TX frame mode for PUSCH</comment>
      </bits>
      <bits name="rMOD_TYPE" pos="1" access="rw" rst="0">
        <comment>Module type</comment>
      </bits>
      <bits name="rTX_BUF_IDX" pos="2" access="rw" rst="0">
        <comment>TX Buffer idx</comment>
      </bits>
      <bits name="rPRACH_CP_MODE" pos="3" access="rw" rst="0">
        <comment>CP length of PRACH0/1</comment>
      </bits>
      <bits name="rTONE_MODE" pos="4" access="rw" rst="0">
        <comment>PUSCH Tone mode</comment>
      </bits>
      <bits name="rSHORTEN_PUSCH_EN" pos="5" access="rw" rst="0">
        <comment>Shorten PUSCH Enable</comment>
      </bits>
      <bits name="rPUSCH_SC_IDX" pos="11:6" access="rw" rst="0">
        <comment>PUSCH Subcarrier POsition</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_GAIN" protect="rw">
      <bits name="rTX_GAIN" pos="11:0" access="rw" rst="0">
        <comment>TX Gain</comment>
      </bits>
    </reg32>
    <reg32 name="rPUSCH_CFG" protect="rw">
      <bits name="rTHETAL_SYMB_INCR" pos="7:0" access="rw" rst="0">
        <comment>thetal symbol incremental step value</comment>
      </bits>
      <bits name="rSYMB_NUM_MOD2" pos="8" access="rw" rst="0">
        <comment>symbol number modulo 2</comment>
      </bits>
    </reg32>
    <reg32 name="rMEM_BUS_ERR" protect="rw">
      <bits name="rMEM_BUS_ERR" pos="1:0" access="r" rst="0">
        <comment>memory bus access error</comment>
      </bits>
      <bits name="rTX_STATUS" pos="3:2" access="r" rst="0">
        <comment>TX Status, 2'b00: IDLE; 2'b01: PRACH; 2'b10: PUSCH 3.75K; 2'b11: PUSCH 15K</comment>
      </bits>
      <bits name="rTX_START_SF_IDX" pos="7:4" access="r" rst="0">
        <comment>Subframe index of NPRACH or NPUSCH transmitted</comment>
      </bits>
    </reg32>
    <hole size="2*32" />
    <reg32 name="rPRACH_CMD_FIFO0" protect="rw">
      <bits name="rPRACH_SC_IDX" pos="5:0" access="rw" rst="0">
        <comment>PRACH sub-carrier index 0~47</comment>
      </bits>
      <bits name="RSV" pos="29:6" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rPRACH_CFG_STATUS" pos="30" access="rw" rst="0">
        <comment>PRACH CFG Status</comment>
      </bits>
      <bits name="rPRACH_NXT_EN" pos="31" access="rw" rst="0">
        <comment>Next PRACH symbol group enabled</comment>
      </bits>
    </reg32>
    <reg32 name="rPRACH_CMD_FIFO1" protect="rw">
      <bits name="rPRACH_SC_IDX" pos="5:0" access="rw" rst="0">
        <comment>PRACH sub-carrier index 0~47</comment>
      </bits>
      <bits name="RSV" pos="29:6" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rPRACH_CFG_STATUS" pos="30" access="rw" rst="0">
        <comment>PRACH CFG Status</comment>
      </bits>
      <bits name="rPRACH_NXT_EN" pos="31" access="rw" rst="0">
        <comment>Next PRACH symbol group enabled</comment>
      </bits>
    </reg32>
    <reg32 name="rPRACH_CMD_FIFO2" protect="rw">
      <bits name="rPRACH_SC_IDX" pos="5:0" access="rw" rst="0">
        <comment>PRACH sub-carrier index 0~47</comment>
      </bits>
      <bits name="RSV" pos="29:6" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rPRACH_CFG_STATUS" pos="30" access="rw" rst="0">
        <comment>PRACH CFG Status</comment>
      </bits>
      <bits name="rPRACH_NXT_EN" pos="31" access="rw" rst="0">
        <comment>Next PRACH symbol group enabled</comment>
      </bits>
    </reg32>
    <reg32 name="rPRACH_CMD_FIFO3" protect="rw">
      <bits name="rPRACH_SC_IDX" pos="5:0" access="rw" rst="0">
        <comment>PRACH sub-carrier index 0~47</comment>
      </bits>
      <bits name="RSV" pos="29:6" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rPRACH_CFG_STATUS" pos="30" access="rw" rst="0">
        <comment>PRACH CFG Status</comment>
      </bits>
      <bits name="rPRACH_NXT_EN" pos="31" access="rw" rst="0">
        <comment>Next PRACH symbol group enabled</comment>
      </bits>
    </reg32>
    <reg32 name="rPRACH_NXT_CMD_RD_PTR" protect="r">
      <bits name="rPRACH_NXT_CMD_RD_PTR" pos="1:0" access="r" rst="0">
        <comment>PRACH Nxt Command Read Pointer</comment>
      </bits>
      <bits name="RSV" pos="31:2" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
    </reg32>
    <reg32 name="rLPF1_COEF0" protect="rw">
      <bits name="rLPF1_COEF00" pos="9:0" access="rw" rst="0">
        <comment>LPF1 coefficient0</comment>
      </bits>
      <bits name="RESERVED" pos="15:10" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rLPF1_COEF01" pos="25:16" access="rw" rst="0">
        <comment>LPF1 coefficient1</comment>
      </bits>
      <bits name="RESERVED" pos="31:26" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
    </reg32>
    <reg32 name="rLPF1_COEF1" protect="rw">
      <bits name="rLPF1_COEF10" pos="9:0" access="rw" rst="0">
        <comment>LPF1 coefficient2</comment>
      </bits>
      <bits name="RESERVED" pos="15:10" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rLPF1_COEF11" pos="25:16" access="rw" rst="0">
        <comment>LPF1 coefficient3</comment>
      </bits>
      <bits name="RESERVED" pos="31:26" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
    </reg32>
    <reg32 name="rLPF2_COEF0" protect="rw">
      <bits name="rLPF2_COEF00" pos="9:0" access="rw" rst="0">
        <comment>LPF2 coefficient0</comment>
      </bits>
      <bits name="RESERVED" pos="15:10" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
      <bits name="rLPF2_COEF01" pos="25:16" access="rw" rst="0">
        <comment>LPF2 coefficient1</comment>
      </bits>
      <bits name="RESERVED" pos="31:26" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
    </reg32>
    <reg32 name="rLPF2_COEF1" protect="rw">
      <bits name="rLPF2_COEF10" pos="9:0" access="rw" rst="0">
        <comment>LPF2 coefficient2</comment>
      </bits>
      <bits name="RESERVED" pos="31:10" access="r" rst="0">
        <comment>Reserved</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_DOUT_CHECKSUM" protect="r">
      <bits name="rTX_DOUT_CHECKSUM" pos="30:0" access="r" rst="0">
        <comment>TX dout checksum</comment>
      </bits>
      <bits name="rTX_DOUT_CHECKSUM_EN" pos="31" access="rw" rst="0">
        <comment>TX dout Checksum Enable</comment>
      </bits>
    </reg32>
    <reg32 name="rTX_FLT_TAIL_BIT_NUM" protect="rw">
      <bits name="rTX_FLT_TAIL_BIT_NUM" pos="7:0" access="rw" rst="0x80">
        <comment>Configurable Number of zero data padded at the end of TX transmission</comment>
      </bits>
    </reg32>
  </module>
</archive>


<archive relative = "nb_tx_pusch_encoder.xml">
<module name="nb_tx_pusch_encoder" category="NBIOT_PHY">

  <reg32 name="PUSCH_ENC_CTRL" protect="rw">
    <bits access="rw" name="rTIMEOUT_VAL" pos="15:0" rst="0x0">
      <comment>Maximum time out value for pusch encoder in 61.44Mhz unit. </comment>
  </bits>    
  <bits access="rw" name="Swap" pos="18:16" rst="0x0">
      <comment>Endian SWAP control for bit, byte and word. </comment>
  </bits>             
  </reg32>

  <reg32 name="PUSCH_ENC_START" protect="wo">
    <bits access="wo" name="PUSCH_ENC_START" pos="0" rst="0x0">
      <comment> Write this register will trigger pusch encoder start </comment>
  </bits>              
  </reg32> 

  <reg32 name="TBS" protect="rw">
    <bits access="rw" name="TBS" pos="12:0" rst="0x0">
      <comment>TB Size for PUSCH. </comment>
  </bits>              
  </reg32>                 

  <reg32 name="Alpha_ini" protect="rw">
    <bits access="rw" name="Alpha_ini" pos="12:0" rst="0x0">
      <comment>Alpha init value for QPP interleaver. </comment>
  </bits>              
  </reg32> 

  <reg32 name="Alpha_step" protect="rw">
    <bits access="rw" name="Alpha_step" pos="12:0" rst="0x0">
      <comment>Alpha Step value for QPP interleaver. </comment>
  </bits>              
  </reg32> 

  <reg32 name="PUSCH_ENC_RD_ADDR" protect="rw">
    <bits access="rw" name="PUSCH_ENC_RD_ADDR" pos="9:0" rst="0x0">
      <comment>Rd address to DSP memory for pusch encoder. </comment>
  </bits>              
  </reg32>

  <reg32 name="PUSCH_ENC_WR_ADDR" protect="rw">
    <bits access="rw" name="PUSCH_ENC_WR_ADDR" pos="9:0" rst="0x0">
      <comment>WR address to DSP memory for pusch encoder. </comment>
  </bits>              
  </reg32>     

  <reg32 name="PUSCH_ENC_STATUS" protect="ro">
    <bits access="rw1c" name="Done" pos="0" rst="0x0">
        <comment>(This bit is read write 1 clear)
                   0: No Done
                   1: Done.
        </comment>
    </bits>
    <bits access="ro" name="Overwritten" pos="1" rst="0x0">
        <comment>Indicate overwritten happen for pusch encoder
                  0: Normal
                  1: Error
        </comment>
    </bits>
    <bits access="ro" name="BUS Error" pos="3:2" rst="0x0">
        <comment>Bit 0: DSP control bus error, 0-Normal, 1-Error
                 Bit 1: accelerator memory access collusion, 0-Normal, 1-Error
        </comment>
    </bits>
    <bits access="ro" name="Timeout " pos="4" rst="0x0">
        <comment>0: Normal
                 1: Error
        </comment>
    </bits>                                                    
  </reg32>     

</module>

</archive>


<archive relative = "nb_viterbi.xml">
  <module name="nb_viterbi" category="NBIOT_PHY">
    <reg32 name="rVD_DEC_START" protect="w">
      <bits name="rVD_DEC_START" pos="0" access="w" rst="0">
        <comment>Start trigger of one sequential decoding of viterbi decoder which is generated by writing '1' to this register</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_CTRL" protect="rw">
      <bits name="rVD_PL_SIZE" pos="27:16" access="rw" rst="0">
        <comment>Payload size of CBs to be decoded in one sequential decoding</comment>
      </bits>
      <bits name="rVD_DEC_NUM" pos="15:13" access="rw" rst="0">
        <comment>Indicate the number(1~4) of coded blocks to be decoded in one sequential decoding process</comment>
      </bits>
      <bits name="rVD_DEINT_EN" pos="12" access="rw" rst="1">
        <comment>Function of de-interleaving in hardware enable/disable
        1: Enable
        0: Disable
        </comment>
      </bits>
      <bits name="rVD_CRCMASK_EN" pos="11" access="rw" rst="0">
        <comment>CRC mask checking enable/disable(for RNTI and antenna port number)
        1: Enable
        0: Disable
        </comment>
      </bits>
      <bits name="rVD_CRC_TYPE" pos="10" access="rw" rst="0">
        <comment>Indicate the CRC type of  sequential decoding
        1:24
        0:16
        </comment>
      </bits>
      <bits name="Reserved" pos="9:1" access="rw" rst="0">
        <comment>Reserved bits</comment>
      </bits>
      <bits name="rVD_LVA_EN" pos="0" access="rw" rst="0">
        <comment>List viterbi mode enable/disable
        1: Enable
        0: Disable
        </comment>
      </bits>
    </reg32>
    <reg32 name="rVD_ADDR_CTRL" protect="rw">
      <bits name="rVD_VOR_ADDR_O" pos="29:21" access="rw" rst="0">
        <comment>This register indicates the start address of viterbi output odd buffer for payload.</comment>
      </bits>
      <bits name="rVD_VOR_ADDR_E" pos="20:12" access="rw" rst="0">
        <comment>This register indicates the start address of viterbi output even buffer for payload.</comment>
      </bits>
      <bits name="rVD_VIR_ADDR" pos="11:0" access="rw" rst="0">
        <comment>This register indicates the start address of data in viterbi input ram.</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_CRC_MASK01" protect="rw">
      <bits name="rVD_CRC_MASK1" pos="31:16" access="rw" rst="0">
        <comment>Indicate CRC mask1(for RNTI and antenna port number)</comment>
      </bits>
      <bits name="rVD_CRC_MASK0" pos="15:0" access="rw" rst="0">
        <comment>Indicate CRC mask0(for RNTI and antenna port number)</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_CRC_MASK23" protect="rw">
      <bits name="rVD_CRC_MASK3" pos="31:16" access="rw" rst="0">
        <comment>Indicate CRC mask1(for RNTI and antenna port number)</comment>
      </bits>
      <bits name="rVD_CRC_MASK2" pos="15:0" access="rw" rst="0">
        <comment>Indicate CRC mask0(for RNTI and antenna port number)</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_LONG_CFG" protect="rw">
      <bits name="rVD_PL_SWAP" pos="18:16" access="rw" rst="0">
        <comment>Reorder the 32bit data written to viterbi output buffer
    2:Reverse the word sequence in the Dword(1Dword)
    1: Reverse the byte sequence in every word(2words).
    0: Reverse the bit sequence in every byte(4bytes).</comment>
      </bits>
      <bits name="rVD_TIMECNT_LIMIT" pos="15:0" access="rw" rst="0xFFFF">
        <comment>In a sequential decoding process, if the corresponding time counter exceeds this set value of rVD_TIMECNT_LIMIT, bit4 of rVD_DEC_SATUS will be set to 1 and sent to high layer.</comment>
      </bits>
    </reg32>
    <hole size="2*32" />
    <reg32 name="rVD_VOR_EO" protect="rw">
      <bits name="rVD_VOR_EO" pos="0" access="rw" rst="0">
        <comment>Indicate even/odd viterbi output buffer to be written by decoder:
1: odd output buffer
0: even output buffer</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_DEC_CTRL" protect="rw">
      <bits name="rVD_SCALING_BW_Y" pos="31:28" access="rw" rst="0">
        <comment>Bit width of output scaling data's fractional part(S8.y)</comment>
      </bits>
      <bits name="rVD_SCALING_BW_X" pos="27:24" access="rw" rst="0">
        <comment>Bit width of input scaling data's fractional part(S16.x)</comment>
      </bits>
      <bits name="rVD_SCALING_FACTOR" pos="23:16" access="rw" rst="0">
        <comment>This register(U8.7) is multiplied by scaling input data(S16.x)</comment>
      </bits>
      <bits name="rVD_CRCMASK_BITMAP3" pos="15:12" access="rw" rst="0">
        <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB3 to be decoded</comment>
      </bits>
      <bits name="rVD_CRCMASK_BITMAP2" pos="11:8" access="rw" rst="0">
        <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB2 to be decoded</comment>
      </bits>
      <bits name="rVD_CRCMASK_BITMAP1" pos="7:4" access="rw" rst="0">
        <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB1 to be decoded</comment>
      </bits>
      <bits name="rVD_CRCMASK_BITMAP0" pos="3:0" access="rw" rst="0">
        <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB0 to be decoded</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_CANDI_CFG" protect="rw">
      <bits name="rVD_SF_IDX" pos="19:16" access="rw" rst="0">
        <comment>Subframe index of current subframe on which DSP configure the decoding start siganl 'rVD_DEC_START'
        </comment>
      </bits>
      <bits name="rVD_CANDI_CFG_CB3" pos="15:12" access="rw" rst="0">
        <comment>15: Antenna number for candidate CB3(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB3
</comment>
      </bits>
      <bits name="rVD_CANDI_CFG_CB2" pos="11:8" access="rw" rst="0">
        <comment>15: Antenna number for candidate CB2(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB2
</comment>
      </bits>
      <bits name="rVD_CANDI_CFG_CB1" pos="7:4" access="rw" rst="0">
        <comment>15: Antenna number for candidate CB1(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB1
</comment>
      </bits>
      <bits name="rVD_CANDI_CFG_CB0" pos="3:0" access="rw" rst="0">
        <comment>15: Antenna number for candidate CB0(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB0
</comment>
      </bits>
    </reg32>
    <hole size="1*32" />
    <reg32 name="rVD_CRCREAD" protect="r">
      <bits name="rVD_CRCRESULT_O" pos="31:16" access="r" rst="0">
        <comment>CRC checking result of the corresponding code block for output buffer odd, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. 
1: good    0: fail
If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB
    [31:28] for CB3(28:MASK0, 29:MASK1, 30:MASK2, 31:MASK3)
    [27:24] for CB2(24:MASK0, 25: MASK1, 26: MASK2, 27: MASK3)
    [23:20] for CB1(20: MASK0, 21: MASK1, 22: MASK2, 23: MASK3)
    [19:16] for CB0(16: MASK0, 17: MASK1, 18: MASK2, 19: MASK3)
And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB
    [28] for CB3
    [24] for CB2
    [20] for CB1
    [16] for CB0</comment>
      </bits>
      <bits name="rVD_CRCRESULT_E" pos="15:0" access="r" rst="0">
        <comment>CRC check result of the corresponding code block for output buffer even, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. 
1: good    0: fail
If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB
    [15:12] for CB3(12: MASK0, 13: MASK1, 14: MASK2, 15: MASK3)
    [11:8] for CB2(8: MASK0, 9: MASK1, 10: MASK2, 11: MASK3)
    [7:4] for CB1(4: MASK0, 5: MASK1, 6: MASK2, 7: MASK3)
    [3:0] for CB0(0: MASK0, 1: MASK1, 2: MASK2, 3: MASK3)
And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB
    [12] for CB3
    [8] for CB2
    [4] for CB1
    [0] for CB0</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_SERREAD01_E" protect="r">
      <bits name="rVD_SER_1" pos="27:16" access="r" rst="0">
        <comment>Symbol error number of the candidate CB1</comment>
      </bits>
      <bits name="Reserved" pos="15:12" access="r" rst="0">
        <comment></comment>
      </bits>
      <bits name="rVD_SER_0" pos="11:0" access="r" rst="0">
        <comment>Symbol error number of the candidate CB0</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_SERREAD01_O" protect="r">
      <bits name="rVD_SER_1" pos="27:16" access="r" rst="0">
        <comment>Symbol error number of the candidate CB1</comment>
      </bits>
      <bits name="Reserved" pos="15:12" access="r" rst="0">
        <comment></comment>
      </bits>
      <bits name="rVD_SER_0" pos="11:0" access="r" rst="0">
        <comment>Symbol error number of the candidate CB0</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_SERREAD23_E" protect="r">
      <bits name="rVD_SER_3" pos="27:16" access="r" rst="0">
        <comment>Symbol error number of the candidate CB1</comment>
      </bits>
      <bits name="Reserved" pos="15:12" access="r" rst="0">
        <comment></comment>
      </bits>
      <bits name="rVD_SER_2" pos="11:0" access="r" rst="0">
        <comment>Symbol error number of the candidate CB0</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_SERREAD23_O" protect="r">
      <bits name="rVD_SER_3" pos="27:16" access="r" rst="0">
        <comment>Symbol error number of the candidate CB1</comment>
      </bits>
      <bits name="Reserved" pos="15:12" access="r" rst="0">
        <comment></comment>
      </bits>
      <bits name="rVD_SER_2" pos="11:0" access="r" rst="0">
        <comment>Symbol error number of the candidate CB0</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_CANDI_RPT_E" protect="r">
      <bits name="rVD_CANDI_RPT_E" pos="31:0" access="r" rst="0">
        <comment>Report some configurations to MCU for output buffer even
    [31:20] Report payload size
    [19:0]  Report configuration of register 'rVD_CANDI_CFG'</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_CANDI_RPT_O" protect="r">
      <bits name="rVD_CANDI_RPT_O" pos="31:0" access="r" rst="0">
        <comment>Report some configurations to MCU for output buffer even
    [31:20] Report payload size
    [19:0]  Report configuration of register 'rVD_CANDI_CFG'</comment>
      </bits>
    </reg32>
    <reg32 name="rVD_DEC_STATUS" protect="ro">
      <bits name="rVD_VOR_REQ_FAIL" pos="8:7" access="ro" rst="0">
        <comment>Viterbi-in ram reading error</comment>
      </bits>
      <bits name="rVD_VIR_REQ_FAIL" pos="6:5" access="ro" rst="0">
        <comment>Viterbi output buffer writing error</comment>
      </bits>
      <bits name="rVD_TIMECNT_OUT" pos="4" access="w1c" rst="0">
        <comment>This bit indicate that the time counter is exceed the limit of set value</comment>
      </bits>
      <bits name="rVD_VOR_OVERWRITE" pos="3:2" access="w1c" rst="0">
        <comment>3: This bit is to indicate that the odd memory is overwritten or not before 'UPDATED' is cleared.
2: This bit is to indicate that the even memory is overwritten or not before 'UPDATED' is cleared.</comment>
      </bits>
      <bits name="rVD_VOR_UPDATED" pos="1:0" access="w1c" rst="0">
        <comment>1: This bit is to indicate that the odd memory is updated or not.
0: This bit is to indicate that the even memory is updated or not.</comment>
      </bits>
    </reg32>
  </module>
</archive>


<archive relative = "page_spy.xml">

<module name="page_spy" category="Debug">

  <var name="NB_BITS_ADDR_PAGE_SPY"     value="32"/>
  <var name="PAGE_SPY_NB_PAGE" value="30"/>

  <reg protect="rw" name="enable">
    <bits access="rs" name="enable_page" pos="PAGE_SPY_NB_PAGE-1:0" rst="0" cut="1" cutprefix="enable_page">
      <comment>Writing '1' enable the page (n), writing '0' leave the page in
      it's current state. Reading returns '1' if the page is active (hit or
      not).</comment>
    </bits>
  </reg>

  <reg protect="rw" name="disable">
    <bits access="rc" name="disable_page" pos="PAGE_SPY_NB_PAGE-1:0" rst="0" cut="1" cutprefix="disable_page">
      <comment>Writing '1' disable the page (n) and clears the hit status if
      any, writing '0' leave the page in it's current state. Reading returns
      '1' if the page is active (hit or not).</comment>
    </bits>
  </reg>

  <reg protect="r" name="status">
    <bits access="r" name="status_page" pos="PAGE_SPY_NB_PAGE-1:0" rst="0" cut="1" cutprefix="status_page">
      <options>
        <option name="NOT_HIT" value="0" />
        <option name="HIT" value="1" />
        <default />
      </options>
      <comment>Status of the page.</comment>
    </bits>
  </reg>

  <hole size="32" />

  <struct count="PAGE_SPY_NB_PAGE" name="page">
    <reg protect="rw" name="start">
      <bits access="rw" name="start_address" pos="NB_BITS_ADDR_PAGE_SPY-1:0" rst="no">
        <comment>Start address of page (n) (included). </comment>
      </bits>
    </reg>

    <reg protect="rw" name="end">
      <bits access="rw" name="end_address" pos="NB_BITS_ADDR_PAGE_SPY-1:0" rst="no">
        <comment>End address of page (n) (excluded).</comment>
      </bits>
    </reg>

    <reg protect="r" name="master">
      <bits access="r" name="master" pos="3:0" rst="0">
        <options>
          <option name="XCPU_SYS" value="0b0001" />
          <option name="BCPU_SYS" value="0b0010" />
          <option name="XCPU_TCM" value="0b0011" />
          <option name="BCPU_TCM" value="0b0100" />
          <option name="RF_IF   " value="0b0101" />
          <option name="SYS_IFC " value="0b0110" />
          <option name="DMA     " value="0b0111" />
          <default />
        </options>
        <comment>The master that wrote in the page (n). </comment>
      </bits>

      <bits access="r" name="hit_read" pos="30" rst="no">
        <comment>If '1' a read has triggered the page.</comment>
      </bits>

      <bits access="r" name="hit_write" pos="31" rst="no">
        <comment>If '1' a write has triggered the page.</comment>
      </bits>
    </reg>

    <reg protect="r" name="addr">
      <bits access="r" name="hit_addr" pos="NB_BITS_ADDR_PAGE_SPY-1:0" rst="no">
        <comment>Address that triggered page (n). </comment>
      </bits>
    </reg>
  </struct>

  <reg protect="rw" name="detect_write_reg">
    <bits access="rw" name="detect_write" pos="PAGE_SPY_NB_PAGE-1:0" rst="no" cut="1" cutprefix="detect_write">
      <comment>If '1' any write within the range will trigger the
      page.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="detect_read_reg">
    <bits access="rw" name="detect_read" pos="PAGE_SPY_NB_PAGE-1:0" rst="no" cut="1" cutprefix="detect_read">
      <comment>If '1' any read within the range will trigger the
      page.</comment>
    </bits>
  </reg>

</module>

</archive>
<archive relative="pmuc.xml">
  <module name="pmuc" category="System">
    <reg protect="rw" name="power_mode_ctrl">
      <bits access="r" name="power_mode_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="power_mode_ctrl_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="r" name="fist_pwon_state" pos="12:8" rst="0">
      </bits>
      <bits access="r" name="power_mode_ctrl_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="r" name="pm_state" pos="6:4" rst="0">
        <comment>
          current  pmuc state
        </comment>
      </bits>
      <bits access="r" name="power_mode_ctrl_reserved_3" pos="3:2" rst="0">
      </bits>
      <bits access="rw" name="pm_mode" pos="1:0" rst="3">
        <comment>
          power mode for pmu
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="pm_mode_status_1">
      <bits access="r" name="pm_mode_status_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="wakeup_exist" pos="15" rst="0">
      </bits>
      <bits access="r" name="pm_mode_status_1_reserved_1" pos="14" rst="0">
      </bits>
      <bits access="r" name="pm03_sw_state" pos="13:8" rst="0">
      </bits>
      <bits access="r" name="pm_mode_status_1_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="r" name="pm01_sw_state" pos="4:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="pm_mode_status_2">
      <bits access="r" name="pm_mode_status_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pm_mode_status_2_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="r" name="lp_mode_b" pos="11" rst="0">
      </bits>
      <bits access="r" name="lp_mode_bg" pos="10" rst="0">
      </bits>
      <bits access="r" name="lp_26mxtal_fsm" pos="9" rst="0">
      </bits>
      <bits access="r" name="lp_clk_en" pos="8" rst="0">
      </bits>
      <bits access="r" name="ldo_vrtc_status" pos="7" rst="0">
      </bits>
      <bits access="r" name="pu_26mxtal" pos="6" rst="0">
      </bits>
      <bits access="r" name="pu_vtcxo" pos="5" rst="0">
      </bits>
      <bits access="r" name="pwrswitch_en" pos="4" rst="0">
      </bits>
      <bits access="r" name="pu_bg_fsm" pos="3" rst="0">
      </bits>
      <bits access="r" name="pu_vsim1" pos="2" rst="0">
      </bits>
      <bits access="r" name="pu_avdd3" pos="1" rst="0">
      </bits>
      <bits access="r" name="pu_vled_ldo_fsm" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="power_status">
      <bits access="r" name="power_status_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pu_vio" pos="15" rst="0">
      </bits>
      <bits access="r" name="pu_vusb" pos="14" rst="0">
      </bits>
      <bits access="r" name="pu_vsdmc" pos="13" rst="0">
      </bits>
      <bits access="r" name="pu_vspimem" pos="12" rst="0">
      </bits>
      <bits access="r" name="pu_vmem" pos="11" rst="0">
      </bits>
      <bits access="r" name="pu_vsim0" pos="10" rst="0">
      </bits>
      <bits access="r" name="pu_buck2_ldo" pos="9" rst="0">
      </bits>
      <bits access="r" name="pu_buck2" pos="8" rst="0">
      </bits>
      <bits access="r" name="pu_buck1_ldo" pos="7" rst="0">
      </bits>
      <bits access="r" name="pu_buck1" pos="6" rst="0">
      </bits>
      <bits access="r" name="pu_va" pos="5" rst="0">
      </bits>
      <bits access="r" name="pu_vrf28" pos="4" rst="0">
      </bits>
      <bits access="r" name="pu_vcam0" pos="3" rst="0">
      </bits>
      <bits access="r" name="pu_vcam1" pos="2" rst="0">
      </bits>
      <bits access="r" name="pu_vlcd" pos="1" rst="0">
      </bits>
      <bits access="r" name="pu_vib" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="clkbuffer_ctrl">
      <bits access="r" name="clkbuffer_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="clkbuf2_ibit" pos="15:12" rst="7">
      </bits>
      <bits access="r" name="clkbuffer_ctrl_reserved_1" pos="11:9" rst="0">
      </bits>
      <bits access="rw" name="clkbuf2_pu" pos="8" rst="1">
      </bits>
      <bits access="rw" name="clkbuf1_ibit" pos="7:4" rst="7">
      </bits>
      <bits access="r" name="clkbuffer_ctrl_reserved_2" pos="3:1" rst="0">
      </bits>
      <bits access="rw" name="clkbuf1_pu" pos="0" rst="1">
      </bits>
    </reg>
    <reg protect="r" name="iso_dbb_status">
      <bits access="r" name="iso_dbb_status_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="iso_dbb_status_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="r" name="resetb_dbb" pos="10" rst="1">
      </bits>
      <bits access="r" name="iso_aon" pos="9" rst="1">
      </bits>
      <bits access="r" name="iso_mmi_top" pos="8" rst="1">
      </bits>
      <bits access="r" name="resetb_mmi_top" pos="7" rst="1">
      </bits>
      <bits access="r" name="pu_mmi_top" pos="6" rst="0">
      </bits>
      <bits access="r" name="iso_gge_top" pos="5" rst="1">
      </bits>
      <bits access="r" name="resetb_gge_top" pos="4" rst="1">
      </bits>
      <bits access="r" name="pu_gge_top" pos="3" rst="0">
      </bits>
      <bits access="r" name="iso_wcn_top" pos="2" rst="1">
      </bits>
      <bits access="r" name="resetb_wcn_top" pos="1" rst="1">
      </bits>
      <bits access="r" name="pu_wcn_top" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="delay_time_ctrl_1">
      <bits access="r" name="delay_time_ctrl_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="sw_rf_clk_time_sel" pos="15:14" rst="0">
      </bits>
      <bits access="r" name="delay_time_ctrl_1_reserved_1" pos="13:12" rst="0">
      </bits>
      <bits access="rw" name="s1_op_time_sel" pos="11:10" rst="1">
        <comment>
          00:1ms,01:3ms:10:7ms,11:8ms
        </comment>
      </bits>
      <bits access="rw" name="dbb_rst_rls_time_sel" pos="9:8" rst="1">
        <comment>
          Wait time after DBB reset release
00:32us, 01:1.5ms, 10:2ms, 11:2.5ms
        </comment>
      </bits>
      <bits access="rw" name="open_xtal_time_sel" pos="7:6" rst="0">
        <comment>
          26m xtal rdy time for wake up from pm1 
00: 0.5ms, 01:1ms, 10:1.5ms, 11:2ms
        </comment>
      </bits>
      <bits access="rw" name="pwon_xtl_wit_time_sel" pos="5:4" rst="1">
        <comment>
          26m xtal rdy time for power on
00: 2ms, 01:2.5ms, 10:3ms, 11:5ms
        </comment>
      </bits>
      <bits access="rw" name="close_ldo_time_sel" pos="3:2" rst="1">
        <comment>
          The interval of shut down powr source
00: 125us, 01:250us, 10:375us, 11:500us
        </comment>
      </bits>
      <bits access="rw" name="op_ldo_time_sel" pos="1:0" rst="1">
        <comment>
          The interval of open powr source
00: 325us, 01:600us, 10:1ms, 11:2ms
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="delay_time_ctrl_2">
      <bits access="r" name="delay_time_ctrl_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="pwrswitch_delay_time_sel" pos="15:14" rst="1">
        <comment>
          pwrswitch_en_delay timer control:
00: 250us
01: 500us
10: 750us
11: 1ms

        </comment>
      </bits>
      <bits access="rw" name="pu_ldo_delay_time_sel" pos="13:12" rst="2">
        <comment>
          pu_ldo and pu_ldo_delay delay time select:  
00:200us 01:250us, 10:300us,11:350us
        </comment>
      </bits>
      <bits access="r" name="delay_time_ctrl_2_reserved_1" pos="11" rst="0">
      </bits>
      <bits access="rw" name="enable_pon_without_rd_efuse" pos="10" rst="1">
        <comment>
          0: Power on enable after auto read efuse done.
1: Power on enable no matter with auto read efuse done.
        </comment>
      </bits>
      <bits access="rw" name="pwrkey_debounce_time_sel" pos="9:8" rst="1">
        <comment>
          powerkey debounce time sel:
00:500ms, 01:1s, 10:1.5s,11:2s
        </comment>
      </bits>
      <bits access="rw" name="sw_32k_time_sel" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="sw_fclk_time_sel" pos="5:4" rst="0">
      </bits>
      <bits access="rw" name="count_pu_mmi_time" pos="3:2" rst="0">
      </bits>
      <bits access="rw" name="count_pd_mmi_time" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="delay_time_ctrl_3">
      <bits access="r" name="delay_time_ctrl_3_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="count_pu_gge_time" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="count_pd_gge_time" pos="13:12" rst="0">
      </bits>
      <bits access="rw" name="count_pd_wcn_time" pos="11:10" rst="0">
      </bits>
      <bits access="rw" name="count_pu_wcn_time" pos="9:8" rst="0">
      </bits>
      <bits access="rw" name="count_wkup_pm1" pos="7:3" rst="0">
      </bits>
      <bits access="rw" name="count_enter_pm1" pos="2:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="delay_time_ctrl_4">
      <bits access="r" name="delay_time_ctrl_4_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="delay_time_ctrl_4_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="count_wit_buck1_rdy" pos="14:12" rst="1">
      </bits>
      <bits access="r" name="delay_time_ctrl_4_reserved_2" pos="11:7" rst="0">
      </bits>
      <bits access="rw" name="xtal_wkup_rdy_time" pos="6:0" rst="1">
      </bits>
    </reg>
    <reg protect="rw" name="pmuc_sys_ctrl">
      <bits access="r" name="pmuc_sys_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pmuc_sys_ctrl_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="lv_detect_reg" pos="9" rst="0">
      </bits>
      <bits access="rw" name="lv_detect_dr" pos="8" rst="0">
      </bits>
      <bits access="r" name="pmuc_sys_ctrl_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="lp_mode_pol" pos="6" rst="0">
        <comment>
          lp_mode polarity
        </comment>
      </bits>
      <bits access="rw" name="lp_mode_mask" pos="5" rst="1">
      </bits>
      <bits access="rw" name="cfg_lp_mode_on" pos="4" rst="0">
        <comment>
          Force the lp_mode_h to be active
        </comment>
      </bits>
      <bits access="rw" name="lp_mode_b_reg" pos="3" rst="1">
      </bits>
      <bits access="rw" name="lp_mode_b_dr" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pwrswitch_en_reg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pwrswitch_en_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="xtal_ctrl_1">
      <bits access="r" name="xtal_ctrl_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="xtal_enter_lp_time_sel" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="xtal_rdac_hlsel_nor" pos="13:12" rst="3">
      </bits>
      <bits access="rw" name="xtal_rdac_hlsel_lp" pos="11:10" rst="3">
      </bits>
      <bits access="r" name="xtal_ctrl_1_reserved_1" pos="9" rst="0">
      </bits>
      <bits access="rw" name="xtal_reg_bit" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="xtal_lp_mode_en_reg" pos="5" rst="0">
      </bits>
      <bits access="rw" name="xtal_lp_mode_en_dr" pos="4" rst="0">
      </bits>
      <bits access="rw" name="pm3_en_xtal" pos="3" rst="1">
        <comment>
          0: PM3 will shut off the xtal.
1: PM3, xtal enter LP mode
        </comment>
      </bits>
      <bits access="rw" name="pm1_en_xtal" pos="2" rst="1">
        <comment>
          0: PM1 will shut off the xtal.
1: PM1, xtal enter LP mode
        </comment>
      </bits>
      <bits access="rw" name="pu_lpo32k" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_32kxtal" pos="0" rst="0">
        <comment>
          32k xtal enable.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="xtal_ctrl_vamp">
      <bits access="r" name="xtal_ctrl_vamp_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="xtal_vamp_ibit_xosc_lp" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="xtal_vamp_ibit_xosc_nor" pos="11:8" rst="4">
      </bits>
      <bits access="rw" name="xtal_lvds2nb_bbpll_en" pos="7" rst="0">
      </bits>
      <bits access="rw" name="xtal_lvds2gsm_bbpll_en" pos="6" rst="0">
      </bits>
      <bits access="rw" name="xtal_clk2gsm_bbpll_en" pos="5" rst="1">
      </bits>
      <bits access="rw" name="xtal_clk2nb_bbpll_en" pos="4" rst="1">
      </bits>
      <bits access="rw" name="xtal_clk2dig_en" pos="3" rst="1">
      </bits>
      <bits access="r" name="xtal_ctrl_vamp_reserved_1" pos="2:1" rst="0">
      </bits>
      <bits access="rw" name="xtal_clk6m5_en_aux" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="xtal_cap_bank">
      <bits access="r" name="xtal_cap_bank_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="xtal_cap_bank_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="xtal_capbank_bit_lp" pos="14:8" rst="64">
      </bits>
      <bits access="r" name="xtal_cap_bank_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="xtal_capbank_bit_nor" pos="6:0" rst="64">
      </bits>
    </reg>
    <reg protect="rw" name="xtal_ctrl_fix_ibit">
      <bits access="r" name="xtal_ctrl_fix_ibit_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="xtal_ctrl_fix_ibit_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="xtal_fix_ibit_xosc_lp" pos="9:5" rst="3">
      </bits>
      <bits access="rw" name="xtal_fix_ibit_xosc_nor" pos="4:0" rst="24">
      </bits>
    </reg>
    <reg protect="rw" name="xtal_ctrl_afc">
      <bits access="r" name="xtal_ctrl_afc_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="xtal_din_dr" pos="15" rst="1">
      </bits>
      <bits access="r" name="xtal_ctrl_afc_reserved_1" pos="14" rst="0">
      </bits>
      <bits access="rw" name="xtal_din_reg" pos="13:0" rst="8192">
      </bits>
    </reg>
    <reg protect="rw" name="xtal_ctrl_6">
      <bits access="r" name="xtal_ctrl_6_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="xdrv_clk_en" pos="15:12" rst="15">
      </bits>
      <bits access="rw" name="enable_clk_6p5m" pos="11" rst="0">
      </bits>
      <bits access="rw" name="xdrv_reg_bit" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="xtal_ctrl_6_reserved_1" pos="7" rst="0">
      </bits>
      <bits access="rw" name="xtal26m_req_bypass" pos="6" rst="1">
      </bits>
      <bits access="rw" name="wcn_osc_req_bypass" pos="5" rst="1">
      </bits>
      <bits access="rw" name="xtal_clk2bt_rfpll_en" pos="4" rst="1">
      </bits>
      <bits access="rw" name="xtal_clk2bt_adpll_en" pos="3" rst="1">
      </bits>
      <bits access="rw" name="xtal_clk2bt_adc_en" pos="2" rst="1">
      </bits>
      <bits access="rw" name="xtal_clk2aupll_en" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_xdrv" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="wake_up_ctrl">
      <bits access="r" name="wake_up_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="sel_pin_wakeup_src" pos="15:14" rst="0">
        <comment>
          0: H level wake up
1: L Level wake up
2: posedge wakeup
3: negedge wakup
        </comment>
      </bits>
      <bits access="rw" name="sel_aon_pin1_wakeup_src" pos="13:12" rst="0">
        <comment>
          0: H level wake up
1: L Level wake up
2: posedge wakeup
3: negedge wakup
        </comment>
      </bits>
      <bits access="r" name="wake_up_ctrl_reserved_1" pos="11:10" rst="0">
      </bits>
      <bits access="rw" name="wcn2sys_wakeup_mask" pos="9" rst="0">
        <comment>
          1. Mask  the wcn2sys_wakeup
        </comment>
      </bits>
      <bits access="rw" name="lps_wakup_mask" pos="8" rst="0">
        <comment>
          1. Mask  the lp_pu_reached wakeup 
        </comment>
      </bits>
      <bits access="rw" name="dbg_hst_wakeup_mask" pos="7" rst="0">
      </bits>
      <bits access="rw" name="rtc_wakeup_mask" pos="6" rst="0">
        <comment>
          1: Mask the rtc wakeup 
        </comment>
      </bits>
      <bits access="rw" name="aon_pin_1_wk_mask" pos="5" rst="0">
        <comment>
          1: Mask the aon pin1 wakeup 
        </comment>
      </bits>
      <bits access="rw" name="pin_wakeup_mask" pos="4" rst="0">
        <comment>
          1: Mask the aon pin0 wakeup 
        </comment>
      </bits>
      <bits access="rw" name="sysirq_wakup_wk_mask" pos="3" rst="0">
        <comment>
          1: Mask the system interrupt wakeup 
        </comment>
      </bits>
      <bits access="rw" name="pin_rst_wakeup_mask" pos="2" rst="0">
        <comment>
          1: Mask after resetb_pin released, power on. 
        </comment>
      </bits>
      <bits access="rw" name="pwrkey_wakeup_mask" pos="1" rst="0">
        <comment>
          1: Mask the pwrkey wakup to wake up
        </comment>
      </bits>
      <bits access="rw" name="low_bat_det_bypass" pos="0" rst="0">
        <comment>
          1:Bypass The Low Power Detection Shut Down Function
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wake_up_status_clr">
      <bits access="r" name="wake_up_status_clr_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="wake_up_status_clr_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rc" name="wcn2sys_wakeup_clr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ac_on_wakeup_clr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="lps_wakeup_clr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="dbg_hst_wakeup_clr" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="rtc_wakeup_clr" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="aon_pin_1_clr" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="pin_wakeup_clr" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="sysirq_wakeup_clr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="pin_rst_wakeup_clr" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="pwrkey_wakeup_clr" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="r" name="wake_up_status">
      <bits access="r" name="wake_up_status_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="wake_up_status_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="r" name="wcn2sys_wakeup_status" pos="9" rst="0">
      </bits>
      <bits access="r" name="ac_on_wakeup_status" pos="8" rst="0">
      </bits>
      <bits access="r" name="lps_wakeup_status" pos="7" rst="0">
      </bits>
      <bits access="r" name="dbg_hst_wakeup_status" pos="6" rst="0">
      </bits>
      <bits access="r" name="rtc_wakeup_status" pos="5" rst="0">
      </bits>
      <bits access="r" name="aon_pin_1_status" pos="4" rst="0">
      </bits>
      <bits access="r" name="pin_wakeup_status" pos="3" rst="0">
      </bits>
      <bits access="r" name="sysirq_wakeup_status" pos="2" rst="0">
      </bits>
      <bits access="r" name="pin_rst_wakeup_status" pos="1" rst="0">
      </bits>
      <bits access="r" name="pwrkey_wakeup_status" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="xtal_divider_ctrl">
      <bits access="r" name="xtal_divider_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="xtal_divider_ctrl_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="r" name="div_lp_mode_h" pos="7" rst="0">
        <comment>
          32k divider work mode. 0: normal mode, 1: low poer mode.
        </comment>
      </bits>
      <bits access="r" name="xtal_divider_ctrl_reserved_2" pos="6" rst="0">
      </bits>
      <bits access="rw" name="sel_32k_src" pos="5:4" rst="0">
        <comment>
          32k clock source select
0: rc 32k
1: xtal32k
2: xtal26 -&gt; 32K
3:  xtal26 -&gt; 32K
        </comment>
      </bits>
      <bits access="r" name="xtal_divider_ctrl_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="div_lp_mode_h_reg" pos="2" rst="0">
        <comment>
          Lp Mode Derect Control
        </comment>
      </bits>
      <bits access="rw" name="div_lp_mode_h_dr" pos="1" rst="0">
        <comment>
          Lp Mode Value
        </comment>
      </bits>
      <bits access="rw" name="step_offset_update" pos="0" rst="0">
        <comment>
          Update the Step Offset Value for 32k divider
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="step_value_for_32kdiv_lp">
      <bits access="r" name="step_value_for_32kdiv_lp_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="step_value_for_32kdiv_lp_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="step_offset_lp" pos="12:0" rst="0">
        <comment>
          32k divider lp mode step
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="step_value_for_32kdiv_nor">
      <bits access="r" name="step_value_for_32kdiv_nor_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="step_value_for_32kdiv_nor_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="step_offset_nor" pos="12:0" rst="0">
        <comment>
          32k divider normal mode step
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="charge_cfg_ctrl">
      <bits access="r" name="charge_cfg_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="chr_highac_9v" pos="15" rst="0">
      </bits>
      <bits access="r" name="chr_highac_6v" pos="14" rst="0">
      </bits>
      <bits access="r" name="lowac_4p6" pos="13" rst="0">
      </bits>
      <bits access="r" name="chr_vreg" pos="12" rst="0">
      </bits>
      <bits access="r" name="chr_creg" pos="11" rst="0">
      </bits>
      <bits access="rw" name="chr_ac_on_time_sel" pos="10:9" rst="1">
        <comment>
          Sel the ac on ready time
        </comment>
      </bits>
      <bits access="rw" name="chg_mask" pos="8" rst="0">
        <comment>
          1: mask the ac_on to power up system
        </comment>
      </bits>
      <bits access="rw" name="bat_off_det_bypass" pos="7" rst="1">
        <comment>
          1: bypass the bat_off to power down.
        </comment>
      </bits>
      <bits access="r" name="chr_cc_mode" pos="6" rst="0">
        <comment>
          constant current charging mode. 
1::constant_current_mode
0::pre_charge_mode
        </comment>
      </bits>
      <bits access="rw" name="chr_cc_mode_reg" pos="5" rst="1">
      </bits>
      <bits access="rw" name="chr_cc_mode_dr" pos="4" rst="0">
      </bits>
      <bits access="r" name="chr_enable" pos="3" rst="0">
        <comment>
          1: charge enable. 0: charge disable
        </comment>
      </bits>
      <bits access="rw" name="chr_enable_reg" pos="2" rst="1">
        <comment>
          charge enable reg
        </comment>
      </bits>
      <bits access="rw" name="chr_enable_dr" pos="1" rst="0">
        <comment>
          charge enable derect
        </comment>
      </bits>
      <bits access="rw" name="pre_chr_check_bypass" pos="0" rst="0">
        <comment>
          1:disable bad bat check. 0: Enable bad bat check.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="charge_cfg_ctrl_2">
      <bits access="r" name="charge_cfg_ctrl_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="charge_cfg_ctrl_2_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="chr_auxadc_sel" pos="13:12" rst="0">
        <comment>
          select the auxout to gpadc.                    00: sel sense voltage of charging current to gpadc;
01: sel TS(Temperature sense) voltage to gpadc; 
10: sel ac_div_in (ac/6) to gpadc;
11:NC
        </comment>
      </bits>
      <bits access="rw" name="chr_cc_i_bit" pos="11:8" rst="4">
        <comment>
          constant current charging tunning bits
        </comment>
      </bits>
      <bits access="rw" name="chr_bypass_chopper" pos="7" rst="0">
      </bits>
      <bits access="rw" name="chr_chopper_sel" pos="6" rst="0">
      </bits>
      <bits access="rw" name="chr_bypass_chopper_isense" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pa_on_bypass" pos="4" rst="0">
        <comment>
          1: disable the pa_on forbid lowbat detect
        </comment>
      </bits>
      <bits access="rw" name="chr_cv_lowgain" pos="3" rst="0">
        <comment>
          constant voltage charging lowgain mode
        </comment>
      </bits>
      <bits access="r" name="chr_ac_on" pos="2" rst="0">
        <comment>
          1: AC connector is on.
        </comment>
      </bits>
      <bits access="r" name="low_bat_det" pos="1" rst="0">
        <comment>
          1: detect low bat
        </comment>
      </bits>
      <bits access="r" name="bat_on" pos="0" rst="0">
        <comment>
          1: detect bat is on.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="charge_cfg_ctrl_3">
      <bits access="r" name="charge_cfg_ctrl_3_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="charge_cfg_ctrl_3_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="charge_pump_ldo_en" pos="12" rst="1">
        <comment>
          enable charge pump for ldo_usb/ldo_vio
        </comment>
      </bits>
      <bits access="rw" name="chr_vfb_sel_reg" pos="11:8" rst="8">
        <comment>
          tunning the floating output voltage of charger.
        </comment>
      </bits>
      <bits access="rw" name="chr_vfb_sel_dr" pos="7" rst="0">
      </bits>
      <bits access="rw" name="chr_uv_sel_reg" pos="6:5" rst="0">
        <comment>
          tunning threshold of under voltage lockout.
00: L-&gt;H(low to high threshold) is 3.21V, H-&gt;L(high to low threshold) is 2.57V;
01:L-&gt;H is 3.21V, H-&gt;L is  2.73V;
10: L-&gt;H is 3.21V; H-&gt;L is 2.88V;
11: L-&gt;H is 3.21V, H-&gt;L is 3.03V.
        </comment>
      </bits>
      <bits access="rw" name="chr_uv_sel_dr" pos="4" rst="0">
      </bits>
      <bits access="rw" name="chr_pre_i_bit_reg" pos="3:1" rst="4">
        <comment>
          pre-charging current tunning bits
        </comment>
      </bits>
      <bits access="rw" name="chr_pre_i_bit_dr" pos="0" rst="0">
        <comment>
          1: disable the pa_on forbid lowbat detect
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out0_15_0">
      <bits access="r" name="charge_efuse_out0_15_0_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out0_15_0" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out0_31_16">
      <bits access="r" name="charge_efuse_out0_31_16_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out0_31_16" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out0_47_32">
      <bits access="r" name="charge_efuse_out0_47_32_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out0_47_32" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out0_63_48">
      <bits access="r" name="charge_efuse_out0_63_48_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out0_63_48" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out1_15_0">
      <bits access="r" name="charge_efuse_out1_15_0_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out1_15_0" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out1_31_16">
      <bits access="r" name="charge_efuse_out1_31_16_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out1_31_16" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out1_47_32">
      <bits access="r" name="charge_efuse_out1_47_32_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out1_47_32" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="charge_efuse_out1_63_48">
      <bits access="r" name="charge_efuse_out1_63_48_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="efuse_out1_63_48" pos="15:0" rst="0">
        <comment>
          read out the charger config from efuse
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="abnormal_pwroff_src">
      <bits access="r" name="abnormal_pwroff_src_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="abnormal_pwroff_src_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="r" name="uvlo_occur" pos="13" rst="0">
      </bits>
      <bits access="r" name="over_temp_occur" pos="12" rst="0">
        <comment>
          shut down for over tempature
        </comment>
      </bits>
      <bits access="r" name="abnormal_pwroff_src_reserved_2" pos="11:9" rst="0">
      </bits>
      <bits access="r" name="bat_off_occur" pos="8" rst="0">
        <comment>
          shut down for bat off detect
        </comment>
      </bits>
      <bits access="r" name="abnormal_pwroff_src_reserved_3" pos="7:5" rst="0">
      </bits>
      <bits access="r" name="low_bat_occur" pos="4" rst="0">
        <comment>
          shut down for low bat detect
        </comment>
      </bits>
      <bits access="r" name="abnormal_pwroff_src_reserved_4" pos="3:1" rst="0">
      </bits>
      <bits access="r" name="rst_ext_occur" pos="0" rst="0">
        <comment>
          shut down by resetb_ext 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="abnormal_pwroff_status_clr">
      <bits access="r" name="abnormal_pwroff_status_clr_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="abnormal_pwroff_status_clr_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rc" name="uvlo_occur_clr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="over_temp_occur_clr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="abnormal_pwroff_status_clr_reserved_2" pos="11:9" rst="0">
      </bits>
      <bits access="rc" name="bat_off_occur_clr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="abnormal_pwroff_status_clr_reserved_3" pos="7:5" rst="0">
      </bits>
      <bits access="rc" name="low_bat_occur_clr" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="abnormal_pwroff_status_clr_reserved_4" pos="3:1" rst="0">
      </bits>
      <bits access="rc" name="rst_occur_clr" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="r" name="pmuc_int_cause">
      <bits access="r" name="pmuc_int_cause_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pmuc_int_cause_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="r" name="ac_on_int_status" pos="8" rst="0">
        <comment>
          AC connect or disconnect interrupt cause
        </comment>
      </bits>
      <bits access="r" name="pmuc_int_cause_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="r" name="pu_ready_int_status" pos="4" rst="0">
        <comment>
          The Power-Up Sequence is in state Ready._x000D_            
        </comment>
      </bits>
      <bits access="r" name="pmuc_int_cause_reserved_3" pos="3:1" rst="0">
      </bits>
      <bits access="r" name="pu_done_int_status" pos="0" rst="0">
        <comment>
          The Power-Up Sequence is done (or idle)._x000D_            
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pmuc_int_mask">
      <bits access="r" name="pmuc_int_mask_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pmuc_int_mask_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rw" name="ac_on_int_mask" pos="8" rst="0">
        <comment>
          AC connect or disconnect interrupt mask
        </comment>
      </bits>
      <bits access="r" name="pmuc_int_mask_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="pu_ready_int_mask" pos="4" rst="0">
        <comment>
          The Power-Up Sequence is in state Ready mask
        </comment>
      </bits>
      <bits access="r" name="pmuc_int_mask_reserved_3" pos="3:1" rst="0">
      </bits>
      <bits access="rw" name="pu_done_int_mask" pos="0" rst="0">
        <comment>
          The Power-Up Sequence is done (or idle) mask 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pmuc_int_clr">
      <bits access="r" name="pmuc_int_clr_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pmuc_int_clr_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rc" name="chr_ac_on_clr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Clear the AC connect or disconnect interrupt
        </comment>
      </bits>
      <bits access="r" name="pmuc_int_clr_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="rc" name="pu_ready_clr" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          clear the  Power-Up Sequence is in state Ready 
        </comment>
      </bits>
      <bits access="r" name="pmuc_int_clr_reserved_3" pos="3:1" rst="0">
      </bits>
      <bits access="rc" name="pu_done_clr" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          clear the Power-Up Sequence is done (or idle) mask 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pmuc_pu_ctrl">
      <bits access="r" name="pmuc_pu_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pmuc_pu_ctrl_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="start_npll_en" pos="13" rst="1">
        <comment>
          1: enalbe to open mpll when pm1 wake up
        </comment>
      </bits>
      <bits access="rw" name="start_gpll_en" pos="12" rst="1">
        <comment>
          1: enalbe to open mpll when pm1 wake up
        </comment>
      </bits>
      <bits access="rw" name="start_mpll_en" pos="11" rst="0">
        <comment>
          1: enalbe to open mpll when pm1 wake up
        </comment>
      </bits>
      <bits access="rw" name="mpll_auto_switch_en" pos="10" rst="0">
        <comment>
          1: Enalbe audo switch sys_clk to pll.
        </comment>
      </bits>
      <bits access="rw" name="reg_tcu_wakeup_en" pos="9" rst="0">
        <comment>
          Enalbe tcu wake up done.
        </comment>
      </bits>
      <bits access="rw" name="reg_pu_done" pos="8" rst="0">
        <comment>
          Write 1 to indicate power up sequence finished, all powers are rdy
auto clear by pu_done
        </comment>
      </bits>
      <bits access="r" name="pmuc_pu_ctrl_reserved_2" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="sw_32k_en" pos="5" rst="1">
        <comment>
          1: auto switch clk_slow to 32k.
        </comment>
      </bits>
      <bits access="r" name="pmuc_pu_ctrl_reserved_3" pos="4" rst="0">
      </bits>
      <bits access="rw" name="sw_rf_en" pos="3" rst="1">
        <comment>
          1: enable to auto swithc the clk_slow to 26M
        </comment>
      </bits>
      <bits access="rw" name="rf_clk_en_pol" pos="2" rst="0">
        <comment>
          This sets the Clock RF control line (CLK_RF_26M_EN) polarity.        
Set to '1' if the line is active low.
        </comment>
      </bits>
      <bits access="rw" name="pu_26mxtal_mask" pos="1" rst="1">
        <comment>
          0: soft can mask the 26m xtal, 1: enable
        </comment>
      </bits>
      <bits access="rw" name="cfg_pu_clk_rf_on" pos="0" rst="0">
        <comment>
          1: soft enable the 26m xtal
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="pu_status">
      <bits access="r" name="pu_status_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pu_status_reserved_1" pos="15:5" rst="0">
      </bits>
      <bits access="r" name="pu_ready" pos="4" rst="0">
        <comment>
          The Power-Up Sequence is in state Ready
        </comment>
      </bits>
      <bits access="r" name="pu_status_reserved_2" pos="3:1" rst="0">
      </bits>
      <bits access="r" name="pu_done" pos="0" rst="0">
        <comment>
          The Power-Up Sequence is done
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wcn_pwr_enable">
      <bits access="r" name="wcn_pwr_enable_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="wcn_pwr_enable_reserved_1" pos="15:1" rst="0">
      </bits>
      <bits access="rw" name="pu_wcn_power" pos="0" rst="1">
        <comment>
          when 1, enable the bt block to powr up
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gge_pwr_enable">
      <bits access="r" name="gge_pwr_enable_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="gge_pwr_enable_reserved_1" pos="15:1" rst="0">
      </bits>
      <bits access="rw" name="pu_gge_power" pos="0" rst="1">
        <comment>
          when 1, enable the bt block to powr up
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mmi_pwr_enable">
      <bits access="r" name="mmi_pwr_enable_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="mmi_pwr_enable_reserved_1" pos="15:1" rst="0">
      </bits>
      <bits access="rw" name="pu_mmi_power" pos="0" rst="1">
        <comment>
          when 1, enable the bt block to powr up
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wcn_pwr_ctrl">
      <bits access="r" name="wcn_pwr_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="wcn_pwr_ctrl_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="r" name="wcn_state" pos="8:6" rst="0">
      </bits>
      <bits access="rw" name="pu_wcn_reg" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pu_wcn_dr" pos="4" rst="0">
      </bits>
      <bits access="rw" name="resetb_wcn_reg" pos="3" rst="1">
      </bits>
      <bits access="rw" name="resetb_wcn_dr" pos="2" rst="0">
      </bits>
      <bits access="rw" name="iso_wcn_reg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="iso_wcn_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="gge_pwr_ctrl">
      <bits access="r" name="gge_pwr_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="gge_pwr_ctrl_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="r" name="gge_state" pos="8:6" rst="0">
      </bits>
      <bits access="rw" name="pu_gge_reg" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pu_gge_dr" pos="4" rst="0">
      </bits>
      <bits access="rw" name="resetb_gge_reg" pos="3" rst="1">
      </bits>
      <bits access="rw" name="resetb_gge_dr" pos="2" rst="0">
      </bits>
      <bits access="rw" name="iso_gge_reg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="iso_gge_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="mmi_pwr_ctrl">
      <bits access="r" name="mmi_pwr_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="mmi_pwr_ctrl_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="r" name="mmi_state" pos="8:6" rst="0">
      </bits>
      <bits access="rw" name="pu_mmi_reg" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pu_mmi_dr" pos="4" rst="0">
      </bits>
      <bits access="rw" name="resetb_mmi_reg" pos="3" rst="1">
      </bits>
      <bits access="rw" name="resetb_mmi_dr" pos="2" rst="0">
      </bits>
      <bits access="rw" name="iso_mmi_reg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="iso_mmi_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bg_cfg_1">
      <bits access="r" name="bg_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="bg_ref_sel_reg" pos="15" rst="0">
        <comment>
          select output reference between bandgap out and vref_pre_reg. ref_sel should follow below sequence:
 when power up, rel_sel should first be 1(the output v1200m=vref_pre_reg), after about 50us when chopping is working, change ref_sel to 0(the output v1200m=vref_bg with chopping)
        </comment>
      </bits>
      <bits access="rw" name="bg_ref_sel_dr" pos="14" rst="0">
      </bits>
      <bits access="rw" name="pm1_lp_bg_en" pos="13" rst="1">
        <comment>
          1: enable the band gap enter lp mode when enter pm1
        </comment>
      </bits>
      <bits access="rw" name="bg_chopper_enb_reg" pos="12" rst="0">
        <comment>
          disable chopping function.
1::disable
0::enable
        </comment>
      </bits>
      <bits access="rw" name="bg_ts_i_ctrl" pos="11:8" rst="8">
        <comment>
          tunning the current for TS. 
        </comment>
      </bits>
      <bits access="rw" name="bg_freq_bit" pos="7:6" rst="2">
        <comment>
          tunning chopping frequency. 
2'b00::400kHz;
2'b01::750kHz; 
2'b10::1.1MHz; 
2'b11::1.5MHz
        </comment>
      </bits>
      <bits access="rw" name="pu_bg_ts" pos="5" rst="0">
        <comment>
          disable temperature sense of battery. 
1::enable temperature sense
0::disable temperature sense
        </comment>
      </bits>
      <bits access="rw" name="bg_chopper_enb_dr" pos="4" rst="0">
      </bits>
      <bits access="rw" name="lp_mode_bg_reg" pos="3" rst="0">
      </bits>
      <bits access="rw" name="lp_mode_bg_dr" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_bg_reg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_bg_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bg_cfg_2">
      <bits access="r" name="bg_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="bg_cfg_2_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="count_bg_rdy" pos="12:8" rst="1">
        <comment>
          wait bg ready time
        </comment>
      </bits>
      <bits access="r" name="bg_cfg_2_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="bg_res_tc_bit" pos="4:0" rst="23">
        <comment>
          tunning the temperatrue coefficient bandgap voltage.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck1_cfg_1">
      <bits access="r" name="ldo_buck1_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_buck1_cfg_1_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="vout_sel_buck1" pos="9" rst="0">
      </bits>
      <bits access="r" name="ldo_buck1_cfg_1_reserved_2" pos="8" rst="0">
      </bits>
      <bits access="rw" name="pu_buck1_reg" pos="7" rst="0">
      </bits>
      <bits access="rw" name="pu_buck1_dr" pos="6" rst="0">
      </bits>
      <bits access="r" name="ldo_buck1_cfg_1_reserved_3" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pu_buck1_ldo_pm1" pos="4" rst="1">
      </bits>
      <bits access="rw" name="pu_buck1_ldo_pm0" pos="3" rst="1">
      </bits>
      <bits access="rw" name="pu_buck1_ldo_pm3" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_buck1_ldo_reg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_buck1_ldo_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck1_cfg_2">
      <bits access="r" name="ldo_buck1_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="slopex2_buck1" pos="15" rst="0">
        <comment>
          200% of slope compensation 
        </comment>
      </bits>
      <bits access="rw" name="en_irdelay_buck1" pos="14" rst="0">
        <comment>
          delay 2ns of ir detection
        </comment>
      </bits>
      <bits access="rw" name="ir_cmp_lr_buck1" pos="13" rst="1">
        <comment>
          reduce or increase Vref of ircmp 
        </comment>
      </bits>
      <bits access="r" name="ldo_buck1_cfg_2_reserved_1" pos="12" rst="0">
      </bits>
      <bits access="rw" name="ir_cmp_bit_buck1" pos="11:9" rst="0">
        <comment>
          adjustment of ircmp
        </comment>
      </bits>
      <bits access="rw" name="heavy_load_buck1" pos="8" rst="0">
        <comment>
          increase peak detect current to increase load current
        </comment>
      </bits>
      <bits access="rw" name="heavy_load2_buck1" pos="7" rst="0">
        <comment>
          increase peak detect current to increase load current
        </comment>
      </bits>
      <bits access="rw" name="dis_antiring_sleep_buck1" pos="6" rst="1">
        <comment>
          disable antiring sleep when antiring_disable_buck1=1
        </comment>
      </bits>
      <bits access="rw" name="antiring_disable_buck1" pos="5" rst="1">
        <comment>
          disable antiring active
        </comment>
      </bits>
      <bits access="rw" name="pfm_clk_disable_buck1" pos="4" rst="1">
        <comment>
          disable pfm_clk
        </comment>
      </bits>
      <bits access="rw" name="pu_ldo_ready_buck1_reg" pos="3" rst="0">
        <comment>
          enable control of ldo
        </comment>
      </bits>
      <bits access="rw" name="pu_dcdc_ready_buck1_reg" pos="2" rst="0">
        <comment>
          enable control of dcdc
        </comment>
      </bits>
      <bits access="rw" name="pu_ldo_ready_buck1_dr" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_dcdc_ready_buck1_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck1_cfg_3">
      <bits access="r" name="ldo_buck1_cfg_3_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="nonov_delay_buck1" pos="15:14" rst="0">
        <comment>
          dcdc nonovlap clk dead time adjust
        </comment>
      </bits>
      <bits access="rw" name="osc_freq_buck1" pos="13:11" rst="2">
        <comment>
          internal clock frequency control
        </comment>
      </bits>
      <bits access="rw" name="pfm_threshold_buck1" pos="10:9" rst="2">
        <comment>
          pfm mode current threshold
        </comment>
      </bits>
      <bits access="rw" name="gdrv_n_en_100ma_buck1" pos="8" rst="1">
        <comment>
          more nldmos for 100ma load
        </comment>
      </bits>
      <bits access="rw" name="gdrv_p_en_100ma_buck1" pos="7" rst="1">
        <comment>
          more pldmos for 100ma load
        </comment>
      </bits>
      <bits access="rw" name="soft_en_buck1" pos="6" rst="1">
        <comment>
          dcdc soft_start
        </comment>
      </bits>
      <bits access="rw" name="ldo_cc_disable_buck1" pos="5" rst="0">
        <comment>
          reduce bandwidth of ldo
        </comment>
      </bits>
      <bits access="rw" name="counter_disable_buck1" pos="4" rst="0">
        <comment>
          disable internal counter
        </comment>
      </bits>
      <bits access="rw" name="discharge_enb_buck1" pos="3" rst="1">
        <comment>
          discharge the output of buck when power down
        </comment>
      </bits>
      <bits access="rw" name="low_sense_bit_buck1" pos="2:1" rst="1">
        <comment>
          increase peak detect current to increase load current
        </comment>
      </bits>
      <bits access="rw" name="slopex0p75_buck1" pos="0" rst="1">
        <comment>
          75% of slope compensation 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck1_cfg_4">
      <bits access="r" name="ldo_buck1_cfg_4_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="buck1_dcdc_mode_en" pos="15" rst="0">
        <comment>
          0: LDO mode
1: BUCK mode
        </comment>
      </bits>
      <bits access="r" name="ldo_buck1_cfg_4_reserved_1" pos="14:4" rst="0">
      </bits>
      <bits access="r" name="ref_ready_buck1" pos="3" rst="0">
        <comment>
          complete soft_start
        </comment>
      </bits>
      <bits access="rw" name="ldo_vref_sel_buck1" pos="2" rst="1">
        <comment>
          ldo vref source
        </comment>
      </bits>
      <bits access="rw" name="pfm_mode_sel_buck1" pos="1" rst="0">
        <comment>
          pfm mode select_x000D_
1:pfm mode and pwm mode auto switch_x000D_
0:force pwm mode
        </comment>
      </bits>
      <bits access="rw" name="dis_lowbat_buck1" pos="0" rst="0">
        <comment>
          disable detection of lowvbat
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck1_cfg_5">
      <bits access="r" name="ldo_buck1_cfg_5_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_buck1_cfg_5_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="vbuck1_ldo_bit_pm1" pos="11:8" rst="9">
      </bits>
      <bits access="rw" name="vbuck1_ldo_bit_pm0" pos="7:4" rst="9">
      </bits>
      <bits access="rw" name="vbuck1_ldo_bit_pm3" pos="3:0" rst="9">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck1_cfg_6">
      <bits access="r" name="ldo_buck1_cfg_6_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_buck1_cfg_6_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="vbuck1_bit_pm1" pos="14:10" rst="16">
      </bits>
      <bits access="rw" name="vbuck1_bit_pm0" pos="9:5" rst="16">
      </bits>
      <bits access="rw" name="vbuck1_bit_pm3" pos="4:0" rst="16">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck2_cfg_1">
      <bits access="r" name="ldo_buck2_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_buck2_cfg_1_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="vout_sel_buck2" pos="9" rst="0">
      </bits>
      <bits access="r" name="ldo_buck2_cfg_1_reserved_2" pos="8" rst="0">
      </bits>
      <bits access="rw" name="pu_buck2_reg" pos="7" rst="0">
      </bits>
      <bits access="rw" name="pu_buck2_dr" pos="6" rst="0">
      </bits>
      <bits access="r" name="ldo_buck2_cfg_1_reserved_3" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pu_buck2_ldo_pm1" pos="4" rst="0">
      </bits>
      <bits access="rw" name="pu_buck2_ldo_pm0" pos="3" rst="1">
      </bits>
      <bits access="rw" name="pu_buck2_ldo_pm3" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_buck2_ldo_reg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_buck2_ldo_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck2_cfg_2">
      <bits access="r" name="ldo_buck2_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="slopex2_buck2" pos="15" rst="0">
        <comment>
          200% of slope compensation 
        </comment>
      </bits>
      <bits access="rw" name="en_irdelay_buck2" pos="14" rst="0">
        <comment>
          delay 2ns of ir detection
        </comment>
      </bits>
      <bits access="rw" name="ir_cmp_lr_buck2" pos="13" rst="1">
        <comment>
          reduce or increase Vref of ircmp 
        </comment>
      </bits>
      <bits access="r" name="ldo_buck2_cfg_2_reserved_1" pos="12" rst="0">
      </bits>
      <bits access="rw" name="ir_cmp_bit_buck2" pos="11:9" rst="0">
        <comment>
          adjustment of ircmp
        </comment>
      </bits>
      <bits access="rw" name="heavy_load_buck2" pos="8" rst="0">
        <comment>
          increase peak detect current to increase load current
        </comment>
      </bits>
      <bits access="rw" name="heavy_load2_buck2" pos="7" rst="0">
        <comment>
          increase peak detect current to increase load current
        </comment>
      </bits>
      <bits access="rw" name="dis_antiring_sleep_buck2" pos="6" rst="1">
        <comment>
          disable antiring sleep when antiring_disable_buck2=1
        </comment>
      </bits>
      <bits access="rw" name="antiring_disable_buck2" pos="5" rst="1">
        <comment>
          disable antiring active
        </comment>
      </bits>
      <bits access="rw" name="pfm_clk_disable_buck2" pos="4" rst="1">
        <comment>
          disable pfm_clk
        </comment>
      </bits>
      <bits access="rw" name="pu_ldo_ready_buck2_reg" pos="3" rst="0">
        <comment>
          enable control of ldo
        </comment>
      </bits>
      <bits access="rw" name="pu_dcdc_ready_buck2_reg" pos="2" rst="0">
        <comment>
          enable control of dcdc
        </comment>
      </bits>
      <bits access="rw" name="pu_ldo_ready_buck2_dr" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_dcdc_ready_buck2_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck2_cfg_3">
      <bits access="r" name="ldo_buck2_cfg_3_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="nonov_delay_buck2" pos="15:14" rst="0">
        <comment>
          dcdc nonovlap clk dead time adjust
        </comment>
      </bits>
      <bits access="rw" name="osc_freq_buck2" pos="13:11" rst="2">
        <comment>
          internal clock frequency control
        </comment>
      </bits>
      <bits access="rw" name="pfm_threshold_buck2" pos="10:9" rst="2">
        <comment>
          pfm mode current threshold
        </comment>
      </bits>
      <bits access="rw" name="gdrv_n_en_70ma_buck2" pos="8" rst="1">
        <comment>
          more nldmos for 100ma load
        </comment>
      </bits>
      <bits access="rw" name="gdrv_p_en_70ma_buck2" pos="7" rst="1">
        <comment>
          more pldmos for 100ma load
        </comment>
      </bits>
      <bits access="rw" name="soft_en_buck2" pos="6" rst="1">
        <comment>
          dcdc soft_start
        </comment>
      </bits>
      <bits access="rw" name="ldo_cc_disable_buck2" pos="5" rst="0">
        <comment>
          reduce bandwidth of ldo
        </comment>
      </bits>
      <bits access="rw" name="counter_disable_buck2" pos="4" rst="0">
        <comment>
          disable internal counter
        </comment>
      </bits>
      <bits access="rw" name="discharge_enb_buck2" pos="3" rst="1">
        <comment>
          discharge the output of buck when power down
        </comment>
      </bits>
      <bits access="rw" name="low_sense_bit_buck2" pos="2:1" rst="1">
        <comment>
          increase peak detect current to increase load current
        </comment>
      </bits>
      <bits access="rw" name="slopex0p75_buck2" pos="0" rst="1">
        <comment>
          75% of slope compensation 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck2_cfg_4">
      <bits access="r" name="ldo_buck2_cfg_4_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="buck2_dcdc_mode_en" pos="15" rst="0">
        <comment>
          0: LDO mode
1: BUCK mode
        </comment>
      </bits>
      <bits access="r" name="ldo_buck2_cfg_4_reserved_1" pos="14:4" rst="0">
      </bits>
      <bits access="r" name="ref_ready_buck2" pos="3" rst="0">
        <comment>
          complete soft_start
        </comment>
      </bits>
      <bits access="rw" name="ldo_vref_sel_buck2" pos="2" rst="1">
        <comment>
          ldo vref source
        </comment>
      </bits>
      <bits access="rw" name="pfm_mode_sel_buck2" pos="1" rst="0">
        <comment>
          pfm mode select_x000D_
1:pfm mode and pwm mode auto switch_x000D_
0:force pwm mode
        </comment>
      </bits>
      <bits access="rw" name="dis_lowbat_buck2" pos="0" rst="0">
        <comment>
          disable detection of lowvbat
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck2_cfg_5">
      <bits access="r" name="ldo_buck2_cfg_5_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_buck2_cfg_5_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="vbuck2_ldo_bit_pm1" pos="11:8" rst="4">
      </bits>
      <bits access="rw" name="vbuck2_ldo_bit_pm0" pos="7:4" rst="4">
      </bits>
      <bits access="rw" name="vbuck2_ldo_bit_pm3" pos="3:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_buck2_cfg_6">
      <bits access="r" name="ldo_buck2_cfg_6_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_buck2_cfg_6_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="vbuck2_bit_pm1" pos="14:10" rst="16">
      </bits>
      <bits access="rw" name="vbuck2_bit_pm0" pos="9:5" rst="16">
      </bits>
      <bits access="rw" name="vbuck2_bit_pm3" pos="4:0" rst="16">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_avdd3_cfg_1">
      <bits access="r" name="ldo_avdd3_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_avdd3_cfg_1_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="avdd3_vbit_pm1" pos="14:12" rst="4">
      </bits>
      <bits access="r" name="ldo_avdd3_cfg_1_reserved_2" pos="11" rst="0">
      </bits>
      <bits access="rw" name="avdd3_vbit_pm0" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_avdd3_cfg_1_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="avdd3_vbit_pm3" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_avdd3_cfg_1_reserved_4" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_avdd3_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_avdd3_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_avdd3_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_va_cfg_1">
      <bits access="r" name="ldo_va_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_va_cfg_1_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="rw" name="pu_lp_va" pos="7" rst="0">
      </bits>
      <bits access="rw" name="va_vsel_pm1" pos="6" rst="0">
        <comment>
          1: 2.4v  0:2.8v
        </comment>
      </bits>
      <bits access="rw" name="va_vsel_pm0" pos="5" rst="0">
        <comment>
          1: 2.4v  0:2.8v
        </comment>
      </bits>
      <bits access="rw" name="va_vsel_pm3" pos="4" rst="0">
        <comment>
          1: 2.4v  0:2.8v
        </comment>
      </bits>
      <bits access="rw" name="va_cc_disable" pos="3" rst="0">
        <comment>
          current sensing disalbe_x000D_
1: disable_x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="pu_va_pm1" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_va_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_va_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_va_cfg_2">
      <bits access="r" name="ldo_va_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_va_cfg_2_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="va_vbit_pm1" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_va_cfg_2_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="va_vbit_pm0" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_va_cfg_2_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="va_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vrf28_cfg_1">
      <bits access="r" name="ldo_vrf28_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vrf28_cfg_1_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="vrf28_vbit_pm1" pos="14:12" rst="4">
      </bits>
      <bits access="r" name="ldo_vrf28_cfg_1_reserved_2" pos="11" rst="0">
      </bits>
      <bits access="rw" name="vrf28_vbit_pm0" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_vrf28_cfg_1_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="vrf28_vbit_pm3" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_vrf28_cfg_1_reserved_4" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vrf28_pm1" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_vrf28_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vrf28_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vmem_cfg_1">
      <bits access="r" name="ldo_vmem_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vmem_cfg_1_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="rw" name="vmem_vsel_pm1" pos="7" rst="1">
        <comment>
          1:1.8v, 0:2.8v
        </comment>
      </bits>
      <bits access="rw" name="vmem_vsel_pm0" pos="6" rst="1">
        <comment>
          1:1.8v, 0:2.8v
        </comment>
      </bits>
      <bits access="rw" name="vmem_vsel_pm3" pos="5" rst="1">
        <comment>
          1:1.8v, 0:2.8v
        </comment>
      </bits>
      <bits access="rw" name="vmem_cur_limit_enb" pos="4" rst="0">
      </bits>
      <bits access="rw" name="vmem_cc_disable" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vmem_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vmem_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vmem_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vmem_cfg_2">
      <bits access="r" name="ldo_vmem_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="vspimem_vbit_pm1" pos="15:12" rst="8">
      </bits>
      <bits access="r" name="ldo_vmem_cfg_2_reserved_1" pos="11:9" rst="0">
      </bits>
      <bits access="rw" name="vmem_vbit_pm1" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="vmem_vbit_pm0" pos="5:3" rst="4">
      </bits>
      <bits access="rw" name="vmem_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vspimem_cfg_1">
      <bits access="r" name="ldo_vspimem_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="vspimem_vbit_pm0" pos="15:12" rst="8">
      </bits>
      <bits access="rw" name="vspimem_vbit_pm3" pos="11:8" rst="8">
      </bits>
      <bits access="r" name="ldo_vspimem_cfg_1_reserved_1" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="vspimem_cc_disable" pos="4" rst="0">
        <comment>
          current sensing disalbe_x000D_
1: disable_x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="vspimem_cur_limit_enb" pos="3" rst="0">
        <comment>
          currnt limiting_x000D_
1: disable _x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="pu_vspimem_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vspimem_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vspimem_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vsdmc_cfg_1">
      <bits access="r" name="ldo_vsdmc_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vsdmc_cfg_1_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="vsdmc_vsel_pm1" pos="13:12" rst="0">
        <comment>
          00:3.3v, 01:2.8v, 11:1.8v
        </comment>
      </bits>
      <bits access="rw" name="vsdmc_vsel_pm0" pos="11:10" rst="0">
        <comment>
          00:3.3v, 01:2.8v, 11:1.8v
        </comment>
      </bits>
      <bits access="rw" name="vsdmc_vsel_pm3" pos="9:8" rst="0">
        <comment>
          00:3.3v, 01:2.8v, 11:1.8v
        </comment>
      </bits>
      <bits access="r" name="ldo_vsdmc_cfg_1_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="vmmc_cc_disable" pos="4" rst="0">
        <comment>
          current sensing disalbe_x000D_
1: disable_x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="vmmc_cur_limit_enb" pos="3" rst="0">
        <comment>
          currnt limiting_x000D_
1: disable _x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="pu_vsdmc_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vsdmc_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vsdmc_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vsdmc_cfg_2">
      <bits access="r" name="ldo_vsdmc_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vsdmc_cfg_2_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rw" name="vsdmc_vbit_pm1" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="vsdmc_vbit_pm0" pos="5:3" rst="4">
      </bits>
      <bits access="rw" name="vsdmc_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vio_cfg_1">
      <bits access="r" name="ldo_vio_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vio_cfg_1_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="vio_vsel_pm1" pos="13:12" rst="3">
        <comment>
          00:3.3v, 01:2.8v, 11:1.8v
        </comment>
      </bits>
      <bits access="rw" name="vio_vsel_pm0" pos="11:10" rst="3">
        <comment>
          00:3.3v, 01:2.8v, 11:1.8v
        </comment>
      </bits>
      <bits access="rw" name="vio_vsel_pm3" pos="9:8" rst="3">
        <comment>
          00:3.3v, 01:2.8v, 11:1.8v
        </comment>
      </bits>
      <bits access="r" name="ldo_vio_cfg_1_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="vio_cc_disable" pos="4" rst="0">
        <comment>
          current sensing disalbe_x000D_
1: disable_x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="vio_cur_limit_enb" pos="3" rst="0">
        <comment>
          currnt limiting_x000D_
1: disable _x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="pu_vio_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vio_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vio_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vio_cfg_2">
      <bits access="r" name="ldo_vio_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vio_cfg_2_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="vio_vbit_pm1" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_vio_cfg_2_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="vio_vbit_pm0" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_vio_cfg_2_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="vio_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vusb_cfg_1">
      <bits access="r" name="ldo_vusb_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vusb_cfg_1_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="rw" name="vusb_vsel_pm1" pos="7" rst="0">
        <comment>
          1: 2.8v,  0: 3.3v
        </comment>
      </bits>
      <bits access="rw" name="vusb_vsel_pm0" pos="6" rst="0">
        <comment>
          1: 2.8v,  0: 3.3v
        </comment>
      </bits>
      <bits access="rw" name="vusb_vsel_pm3" pos="5" rst="0">
        <comment>
          1: 2.8v,  0: 3.3v
        </comment>
      </bits>
      <bits access="rw" name="vusb_cc_disable" pos="4" rst="0">
        <comment>
          current sensing disalbe_x000D_
1: disable_x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="vusb_cur_limit_enb" pos="3" rst="0">
        <comment>
          currnt limiting_x000D_
1: disable _x000D_
0: enable
        </comment>
      </bits>
      <bits access="rw" name="pu_vusb_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vusb_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vusb_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vusb_cfg_2">
      <bits access="r" name="ldo_vusb_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vusb_cfg_2_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="vusb_vbit_pm1" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_vusb_cfg_2_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="vusb_vbit_pm0" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_vusb_cfg_2_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="vusb_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vsim0_cfg_1">
      <bits access="r" name="ldo_vsim0_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vsim0_cfg_1_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="vsim0_vsel_pm1" pos="9:8" rst="3">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="rw" name="vsim0_vsel_pm0" pos="7:6" rst="3">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="rw" name="vsim0_vsel_pm3" pos="5:4" rst="3">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="r" name="ldo_vsim0_cfg_1_reserved_2" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vsim0_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vsim0_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vsim0_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vsim0_cfg_2">
      <bits access="r" name="ldo_vsim0_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vsim0_cfg_2_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rw" name="vsim0_vbit_pm1" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="vsim0_vbit_pm0" pos="5:3" rst="4">
      </bits>
      <bits access="rw" name="vsim0_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vsim1_cfg_1">
      <bits access="r" name="ldo_vsim1_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vsim1_cfg_1_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="vsim1_vsel_pm1" pos="9:8" rst="3">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="rw" name="vsim1_vsel_pm0" pos="7:6" rst="3">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="rw" name="vsim1_vsel_pm3" pos="5:4" rst="3">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="r" name="ldo_vsim1_cfg_1_reserved_2" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vsim1_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vsim1_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vsim1_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vsim1_cfg_2">
      <bits access="r" name="ldo_vsim1_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vsim1_cfg_2_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rw" name="vsim1_vbit_pm1" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="vsim1_vbit_pm0" pos="5:3" rst="4">
      </bits>
      <bits access="rw" name="vsim1_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vcam0_cfg_1">
      <bits access="r" name="ldo_vcam0_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vcam0_cfg_1_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="vcam0_vsel_pm1" pos="9:8" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.3v
        </comment>
      </bits>
      <bits access="rw" name="vcam0_vsel_pm0" pos="7:6" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.3v
        </comment>
      </bits>
      <bits access="rw" name="vcam0_vsel_pm3" pos="5:4" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.3v
        </comment>
      </bits>
      <bits access="r" name="ldo_vcam0_cfg_1_reserved_2" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vcam0_pm1" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_vcam0_pm0" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_vcam0_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vcam0_cfg_2">
      <bits access="r" name="ldo_vcam0_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vcam0_cfg_2_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="vcam0_vbit_pm1" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_vcam0_cfg_2_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="vcam0_vbit_pm0" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_vcam0_cfg_2_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="vcam0_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vcam1_cfg_1">
      <bits access="r" name="ldo_vcam1_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vcam1_cfg_1_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="vcam1_vsel_pm1" pos="9:8" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.3v
        </comment>
      </bits>
      <bits access="rw" name="vcam1_vsel_pm0" pos="7:6" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.3v
        </comment>
      </bits>
      <bits access="rw" name="vcam1_vsel_pm3" pos="5:4" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.3v
        </comment>
      </bits>
      <bits access="r" name="ldo_vcam1_cfg_1_reserved_2" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vcam1_pm1" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_vcam1_pm0" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_vcam1_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vcam1_cfg_2">
      <bits access="r" name="ldo_vcam1_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vcam1_cfg_2_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="vcam1_vbit_pm1" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_vcam1_cfg_2_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="vcam1_vbit_pm0" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_vcam1_cfg_2_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="vcam1_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vlcd_cfg_1">
      <bits access="r" name="ldo_vlcd_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vlcd_cfg_1_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="vlcd_vsel_pm1" pos="9:8" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="rw" name="vlcd_vsel_pm0" pos="7:6" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="rw" name="vlcd_vsel_pm3" pos="5:4" rst="2">
        <comment>
          00:1.8v, 01:2.0v,10: 2.8v, 11: 3.0v
        </comment>
      </bits>
      <bits access="r" name="ldo_vlcd_cfg_1_reserved_2" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vlcd_pm1" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_vlcd_pm0" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_vlcd_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vlcd_cfg_2">
      <bits access="r" name="ldo_vlcd_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_vlcd_cfg_2_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="vlcd_vbit_pm1" pos="10:8" rst="4">
      </bits>
      <bits access="r" name="ldo_vlcd_cfg_2_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="vlcd_vbit_pm0" pos="6:4" rst="4">
      </bits>
      <bits access="r" name="ldo_vlcd_cfg_2_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="vlcd_vbit_pm3" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_vib_cfg_1">
      <bits access="r" name="ldo_vib_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="vib_vbit_pm1" pos="15:13" rst="4">
      </bits>
      <bits access="rw" name="vib_vbit_pm0" pos="12:10" rst="4">
      </bits>
      <bits access="rw" name="vib_vbit_pm3" pos="9:7" rst="4">
      </bits>
      <bits access="rw" name="vib_vsel_pm1" pos="6" rst="0">
        <comment>
          1: 2.8v  0:3.2v
        </comment>
      </bits>
      <bits access="rw" name="vib_vsel_pm0" pos="5" rst="0">
        <comment>
          1: 2.8v  0:3.2v
        </comment>
      </bits>
      <bits access="rw" name="vib_vsel_pm3" pos="4" rst="0">
        <comment>
          1: 2.8v  0:3.2v
        </comment>
      </bits>
      <bits access="rw" name="vibr_cc_disable" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vib_pm1" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_vib_pm0" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_vib_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_tcxo_cfg_1">
      <bits access="r" name="ldo_tcxo_cfg_1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_tcxo_cfg_1_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="vtcxo_vbit_pm1" pos="14:12" rst="4">
      </bits>
      <bits access="rw" name="vtcxo_vbit_pm0" pos="11:9" rst="4">
      </bits>
      <bits access="rw" name="vtcxo_vbit_pm3" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="vtcxo_vsel_pm1" pos="5" rst="0">
        <comment>
          1: 2.8v  0:3.2v
        </comment>
      </bits>
      <bits access="rw" name="vtcxo_vsel_pm0" pos="4" rst="0">
        <comment>
          1: 2.8v  0:3.2v
        </comment>
      </bits>
      <bits access="rw" name="vtcxo_vsel_pm3" pos="3" rst="0">
        <comment>
          1: 2.8v  0:3.2v
        </comment>
      </bits>
      <bits access="rw" name="pu_vtcxo_pm1" pos="2" rst="1">
      </bits>
      <bits access="rw" name="pu_vtcxo_pm0" pos="1" rst="1">
      </bits>
      <bits access="rw" name="pu_vtcxo_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ldo_rgb_cfg">
      <bits access="r" name="ldo_rgb_cfg_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="ldo_rgb_cfg_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="pu_bl_pm1" pos="14" rst="0">
      </bits>
      <bits access="rw" name="pu_bl_pm0" pos="13" rst="0">
      </bits>
      <bits access="rw" name="pu_bl_pm3" pos="12" rst="0">
      </bits>
      <bits access="r" name="ldo_rgb_cfg_reserved_2" pos="11" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_b_pm1" pos="10" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_b_pm0" pos="9" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_b_pm3" pos="8" rst="0">
      </bits>
      <bits access="r" name="ldo_rgb_cfg_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_g_pm1" pos="6" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_g_pm0" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_g_pm3" pos="4" rst="0">
      </bits>
      <bits access="r" name="ldo_rgb_cfg_reserved_4" pos="3" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_r_pm1" pos="2" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_r_pm0" pos="1" rst="0">
      </bits>
      <bits access="rw" name="pu_vled_r_pm3" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="vrtc_ulp_cfg">
      <bits access="r" name="vrtc_ulp_cfg_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="vrtc_ulp_cfg_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="ldo_ulp_vrtc_vbit_pm1" pos="11:8" rst="8">
      </bits>
      <bits access="rw" name="ldo_ulp_vrtc_vbit_pm0" pos="7:4" rst="8">
      </bits>
      <bits access="rw" name="ldo_ulp_vrtc_vbit_pm3" pos="3:0" rst="8">
      </bits>
    </reg>
    <reg protect="rw" name="vpad_ulp_cfg">
      <bits access="r" name="vpad_ulp_cfg_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="vpad_ulp_cfg_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="vbat_bakup_vbit" pos="14" rst="1">
        <comment>
          Not used
        </comment>
      </bits>
      <bits access="rw" name="memio_retention_enable" pos="13" rst="0">
        <comment>
          1: retention the PSRAM IO PAD
        </comment>
      </bits>
      <bits access="rw" name="rtc_calib_en" pos="12" rst="0">
        <comment>
          software enalbe rtl calib
        </comment>
      </bits>
      <bits access="rw" name="ldo_ulp_vio_vbit_pm1" pos="11:8" rst="8">
        <comment>
          usded for vbat_bakup_vbit
        </comment>
      </bits>
      <bits access="rw" name="ldo_ulp_vio_vbit_pm0" pos="7:4" rst="8">
        <comment>
          usded for vbat_bakup_vbit
        </comment>
      </bits>
      <bits access="rw" name="ldo_ulp_vio_vbit_pm3" pos="3:0" rst="8">
        <comment>
          usded for vbat_bakup_vbit
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temprature_ctrl">
      <bits access="r" name="temprature_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="temprature_ctrl_reserved_1" pos="15:4" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="thermal_check_bypass" pos="3" rst="1">
        <comment>
          0: Enable the thermal check
1: Disable the thermal check
        </comment>
      </bits>
      <bits access="rw" name="thermal_sel" pos="2:1" rst="0">
        <comment>
          over temp threshold sel_x000D_
00: 142 _x000D_
01: 130_x000D_
10: 120_x000D_
11: 108
        </comment>
      </bits>
      <bits access="rw" name="pu_thermal_protect" pos="0" rst="0">
        <comment>
          enable thermal protect function_x000D_
0:disable_x000D_
1:enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="nand_and_uvlo">
      <bits access="r" name="nand_and_uvlo_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="disable_pullup_res" pos="15" rst="0">
        <comment>
          1: Disable the pull up resistory on the pwrkey PAD.
        </comment>
      </bits>
      <bits access="r" name="nand_and_uvlo_reserved_1" pos="14:12" rst="0">
      </bits>
      <bits access="rw" name="uvlo_vth_bit" pos="11:8" rst="2">
        <comment>
          0000:2.2v
0001:2.4v
0010:2.6v
0100:2.8v
1000:3.0v
        </comment>
      </bits>
      <bits access="r" name="nand_and_uvlo_reserved_2" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="en_uvlo" pos="5" rst="0">
        <comment>
          1:Enable the uvlo detect
        </comment>
      </bits>
      <bits access="rw" name="uvlo_detect_bypass" pos="4" rst="1">
        <comment>
          1:bypass the uvlo detect fucntion
        </comment>
      </bits>
      <bits access="r" name="nand_and_uvlo_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="nand_wp_vsel" pos="2:1" rst="0">
        <comment>
          write protection threshold sel,given VRTC_MUX_OUT=1.2V_x000D_
00:_x000D_
01:_x000D_
10:_x000D_
11:_x000D_

        </comment>
      </bits>
      <bits access="rw" name="nand_wp_en" pos="0" rst="0">
        <comment>
          nand write protection enable_x000D_
0: disable_x000D_
1: enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbb_ctrl">
      <bits access="r" name="dbb_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="dbb_ctrl_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="mem_retention_reg" pos="11" rst="0">
      </bits>
      <bits access="rw" name="mem_retention_dr" pos="10" rst="0">
      </bits>
      <bits access="rw" name="lp_clk_en_reg" pos="9" rst="1">
      </bits>
      <bits access="rw" name="lp_clk_en_dr" pos="8" rst="0">
      </bits>
      <bits access="rw" name="pu_done_reg" pos="7" rst="0">
      </bits>
      <bits access="rw" name="pu_done_dr" pos="6" rst="0">
      </bits>
      <bits access="rw" name="pu_ready_reg" pos="5" rst="0">
      </bits>
      <bits access="rw" name="pu_ready_dr" pos="4" rst="0">
      </bits>
      <bits access="r" name="dbb_ctrl_reserved_2" pos="3" rst="0">
      </bits>
      <bits access="r" name="dbb_ctrl_reserved_3" pos="2" rst="0">
      </bits>
      <bits access="rw" name="resetb_dbb_reg" pos="1" rst="1">
      </bits>
      <bits access="rw" name="resetb_dbb_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="spk_ctrl">
      <bits access="r" name="spk_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="spk_ctrl_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="rw" name="spk_vio_ulp_bit" pos="7:4" rst="8">
      </bits>
      <bits access="r" name="spk_ctrl_reserved_2" pos="3:1" rst="0">
      </bits>
      <bits access="rw" name="spk_pu_clg" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="aon_mem_pwr_ctrl">
      <bits access="r" name="aon_mem_pwr_ctrl_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="aon_mem_pwr_ctrl_reserved_1" pos="15:5" rst="0">
      </bits>
      <bits access="rw" name="iso_aon_mem" pos="4" rst="1">
      </bits>
      <bits access="r" name="aon_mem_pwr_ctrl_reserved_2" pos="3:1" rst="0">
      </bits>
      <bits access="rw" name="pd_aon_mem" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="pmu1_rsv_cfg">
      <bits access="r" name="pmu1_rsv_cfg_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="pmu1_rsv_vrtc_in" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="pmu1_rsv_cfg_2">
      <bits access="r" name="pmu1_rsv_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pmu1_rsv_cfg_2_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="r" name="pmu1_rsv_vrtc_out" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="pmu2_rsv_cfg">
      <bits access="r" name="pmu2_rsv_cfg_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="pmu2_rsv_vrtc_in" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="pmu2_rsv_cfg_2">
      <bits access="r" name="pmu2_rsv_cfg_2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="pmu2_rsv_cfg_2_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="r" name="pmu2_rsv_vrtc_out" pos="7:0" rst="0">
      </bits>
    </reg>
  </module>
</archive>

<archive relative = "psram8_ctrl.xml">

<module name="psram8_ctrl" category="System">

  <reg name="ctrl_time" protect="rw">
    <bits access="rw" name="rl_type" pos="31:31" rst="0x0">
    </bits>
    <bits access="rw" name="rl" pos="29:24" rst="0x3">
    </bits>
    <bits access="rw" name="wl" pos="21:16" rst="0x0">
    </bits>
    <bits access="rw" name="w_tcph" pos="13:8" rst="0x7">
    </bits>
    <bits access="rw" name="r_tcph" pos="5:0" rst="0x3">
    </bits>
  </reg>

  <reg name="read_ctrl" protect="rw">
    <bits access="rw" name="fifo_rst_time" pos="17:12" rst="0x1">
    </bits>
    <bits access="rw" name="rd_start_mode" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw" name="opt_length" pos="7:4" rst="0x3">
    </bits>
    <bits access="rw" name="rd_start_num" pos="3:0" rst="0x7">
    </bits>
  </reg>

  <hole size="32"/>

  <reg name="dqs_ctrl" protect="rw">
    <bits access="rw" name="o_dqs_u_delay" pos="31:24" rst="0x0">
    </bits>
    <bits access="rw" name="o_dqs_l_delay" pos="23:16" rst="0x0">
    </bits>
    <bits access="rw" name="i_dqs_u_delay" pos="15:8" rst="0x0">
    </bits>
    <bits access="rw" name="i_dqs_l_delay" pos="7:0" rst="0x0">
    </bits>
  </reg>

  <reg name="clk_ctrl" protect="rw">
    <bits access="rw" name="o_clk_delay" pos="7:0" rst="0x0">
    </bits>
  </reg>

  <reg name="power_up" protect="rw">
    <bits access="rw" name="wake_up_trig" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw" name="wake_up_time" pos="19:12" rst="0xf">
    </bits>
      <bits access="r" name="init_done_state" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw" name="hw_power_pulse" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="sw_init_done" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw" name="sw_power_level" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="power_time" protect="rw">
    <bits access="rw" name="rst_wait_time" pos="25:16" rst="0x3ff">
    </bits>
    <bits access="rw" name="rst_tcph_time" pos="13:8" rst="0x7">
    </bits>
    <bits access="rw" name="rst_acc_time" pos="5:0" rst="0x5">
    </bits>
  </reg>

  <reg name="reg_time" protect="rw">
    <bits access="rw" name="nop_time" pos="21:16" rst="0xf">
    </bits>
    <bits access="rw" name="send_reg_time" pos="13:8" rst="0x3">
    </bits>
    <bits access="rw" name="read_reg_time" pos="5:0" rst="0xf">
    </bits>
  </reg>

  <reg name="irsr" protect="r">
    <bits access="r" name="wrong_delay" pos="7:7" rst="0x0">
    </bits>
    <bits access="r" name="delay_updt" pos="6:6" rst="0x0">
    </bits>
    <bits access="r" name="rd_timeout" pos="5:5" rst="0x0">
    </bits>
    <bits access="r" name="init_done"  pos="4:4" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_d" pos="3:3" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_c" pos="2:2" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_b" pos="1:1" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_a" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="imr" protect="rw">
    <bits access="rw" name="wrong_delay" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw" name="delay_updt" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw" name="rd_timeout" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw" name="init_done"  pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_d" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_c" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_b" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_a" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="isr" protect="r">
    <bits access="r" name="wrong_delay" pos="7:7" rst="0x0">
    </bits>
    <bits access="r" name="delay_updt" pos="6:6" rst="0x0">
    </bits>
    <bits access="r" name="rd_timeout" pos="5:5" rst="0x0">
    </bits>
    <bits access="r" name="init_done"  pos="4:4" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_d" pos="3:3" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_c" pos="2:2" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_b" pos="1:1" rst="0x0">
    </bits>
    <bits access="r" name="cross_1k_a" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="icr" protect="rw">
    <bits access="rw" name="wrong_delay" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw" name="delay_updt" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw" name="rd_timeout" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw" name="init_done"  pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_d" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_c" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_b" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw" name="cross_1k_a" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="debug_sel" protect="rw">
    <bits access="rw" name="debug_sel" pos="7:0" rst="0x0">
    </bits>
  </reg>

  <reg name="timeout_val" protect="rw">
    <bits access="rw" name="timeout_value" pos="19:0" rst="0x7ff">
    </bits>
  </reg>

  <reg name="psram_free" protect="rw">
    <bits access="r" name="psram_free" pos="31:31" rst="0x1">
    </bits>
    <bits access="r" name="phy_state" pos="4:0" rst="0x0">
    </bits>
  </reg>

  <reg name="psram_version" protect="rw">
    <bits access="rw" name="APMEM32M0" pos="31" rst="0x0">
    </bits>
    <bits access="r" name="psram_version" pos="3:0" rst="0x1">
    </bits>
  </reg>
  
  <reg name="delay_train" protect="rw">
    <bits access="rw" name="auto_cfg" pos="31:31" rst="0x0">
    </bits>
    <bits access="rw" name="delay_final_add" pos="30:28" rst="0x1">
    </bits>
    <bits access="rw" name="delay_threshold" pos="27:24" rst="0x4">
    </bits>
    <bits access="rw" name="wait_dll_value" pos="19:16" rst="0xf">
    </bits>
    <bits access="rw" name="init_trim" pos="14:12" rst="0x7">
    </bits>
    <bits access="rw" name="init_delay" pos="11:4" rst="0x0">
    </bits>
    <bits access="rw" name="delay_step" pos="3:2" rst="0x1">
    </bits>
    <bits access="rw" name="training_en" pos="1" rst="0x0">
    </bits>
  </reg>

  <reg name="dll_state" protect="rw">
    <bits access="rw" name="dll_locked" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw" name="real_path_delay" pos="15:8" rst="0x0">
    </bits>
    <bits access="rw" name="train_delay" pos="7:0" rst="0x0">
    </bits>
  </reg>

  <reg name="delay_maxmin" protect="rw">
    <bits access="rw" name="train_delay_max" pos="15:8" rst="0x0">
    </bits>
    <bits access="rw" name="train_delay_min" pos="7:0" rst="0x0">
    </bits>
  </reg>

  <reg name="arbi_ctrl" protect="rw">
    <bits access="rw" name="arbi_alg" pos="31:31" rst="0x1">
    </bits>
    <bits access="rw" name="cur_ahb" pos="9:8" rst="0x0">
    </bits>
    <bits access="rw" name="cmd_priority" pos="7:0" rst="0x1b">
    </bits>
  </reg>

  <reg name="cnt_trans_a" protect="r">
    <bits access="r" name="cnt_trans_a" pos="31:0" rst="0x0">
    </bits>
  </reg>
  
  <reg name="cnt_trans_b" protect="r">
    <bits access="r" name="cnt_trans_b" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="cnt_trans_c" protect="r">
    <bits access="r" name="cnt_trans_c" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="cnt_trans_d" protect="r">
    <bits access="r" name="cnt_trans_d" pos="31:0" rst="0x0">
    </bits>
  </reg>
  
  <reg name="cnt_wait_a" protect="r">
    <bits access="r" name="cnt_wait_a" pos="31:0" rst="0x0">
    </bits>
  </reg>
  
  <reg name="cnt_wait_b" protect="r">
    <bits access="r" name="cnt_wait_b" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="cnt_wait_c" protect="r">
    <bits access="r" name="cnt_wait_c" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="cnt_wait_d" protect="r">
    <bits access="r" name="cnt_wait_d" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="cnt_ctrl" protect="rw">
    <bits access="rw" name="cnt_stop_d" pos="7" rst="0x0">
    </bits>
    <bits access="rw" name="cnt_start_d" pos="6" rst="0x0">
    </bits>
    <bits access="rw" name="cnt_stop_c" pos="5" rst="0x0">
    </bits>
    <bits access="rw" name="cnt_start_c" pos="4" rst="0x0">
    </bits>
    <bits access="rw" name="cnt_stop_b" pos="3" rst="0x0">
    </bits>
    <bits access="rw" name="cnt_start_b" pos="2" rst="0x0">
    </bits>
    <bits access="rw" name="cnt_stop_a" pos="1" rst="0x0">
    </bits>
    <bits access="rw" name="cnt_start_a" pos="0" rst="0x0">
    </bits>
  </reg>
  
  <hole size="96"/>

  <reg name="mr0" protect="rw">
    <bits access="rw" name="mr0" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="mr1" protect="r">
    <bits access="r" name="mr1" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="mr2" protect="r">
    <bits access="r" name="mr2" pos="31:0" rst="0x0">
    </bits>
  </reg>
  
  <reg name="mr3" protect="rw">
    <bits access="rw" name="mr3" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <reg name="mr4" protect="rw">
    <bits access="rw" name="mr4" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <hole size="32"/>

  <reg name="mr6" protect="rw">
    <bits access="rw" name="mr6" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <hole size="32"/>

  <reg name="mr8" protect="rw">
    <bits access="rw" name="mr8" pos="31:0" rst="0x0">
    </bits>
  </reg>

  <hole size="704"/>

  <reg name="cre" protect="rw">
    <bits access="rw" name="cre" pos="0:0" rst="0x0">
    </bits>
  </reg>

</module>
</archive>

<archive relative = "pulp_dbg.xml">
	<module name="pulp_dbg" category="pulp_dbg">
  </module>
</archive>

<archive relative = "pulp_irq.xml">
	<module name="pulp_irq" category="pulp_irqctl">
		<reg name="reg_enable" protect="rw">
			<bits name="enable" pos="31:0" access="rw" rst="0x0" >
                <comment>irq enable ctrl, 1: enable ; 0: disable
                </comment>
			</bits>
		</reg>
		<reg name="reg_pending">
			<bits name="pending_int" pos="31:0" access="rw" rst="0x0" >
                <comment>pending interrupt, can be set(1), clr(0), and read status 
                </comment>
			</bits>
		</reg>
        <reg name="set_pending">
			<bits name="set_pending_int" pos="31:0" access="wo" rst="0x0" >
                <comment>pending interrupt, can be set(1)
                </comment>
			</bits>
        </reg>
        <reg name="clr_pending_int">
			<bits name="clr_pending" pos="31:0" access="wo" rst="0x0" >
                <comment>pending interrupt, can be clr(1)
                </comment>
			</bits>
		</reg>
  </module>
</archive>

<archive relative = "pulp_sc.xml">
	<module name="pulp_sc" category="pulp_slpctl">
		<reg name="SCR">
			<bits name="enable" pos="0" access="rw" rst="0x0" >
				<comment>1: Sleep Enabled.
        Put the core to sleep. The core will be woken up again when there is an interrupt   </comment>
			</bits>
		</reg>
		<reg name="SSR">
			<bits name="sleep_st" pos="0" access="ro" rst="0x0" >
				<comment>Sleep Status.
        if the core is currently asleep and has its clock gated. </comment>
			</bits>

		</reg>
  </module>
</archive>
<archive relative = "pwm.xml">
<module name="pwm" category="Periph">
    <reg name="PWT0_Config" protect="rw">
        <bits name="PWT0_Enable" pos="0" access="rw" rst="0">
            <comment>Enables the Pulse Width Tone output
                <br/>1 = Enable PWT output
                <br/>0 = Disable PWT output
            </comment>            
        </bits>
        <bits name="PWT0_Duty" pos="13:4" access="rw" rst="all1">
            <comment>The PWT_Duty value can be used to set the approximate volume of the tone.
                <br/> The PWT_Duty value must be less than or equal to half the PWT_Period value and must be at least a value of 8, otherwise no tone will be generated.
            </comment>
        </bits>
        <bits name="PWT0_Period" pos="26:16" access="rw" rst="all1">
            <comment>PWT_Period is the divider value to produce a tone of a given frequency.
                <br/> To calculate the PWT_Period value, Use the following formula:
                <br/>  PWT_Period = FBASE/FNOTE
                <br/> where FBASE is the frequency of the PWM module clock (it is based on the system frequency, 26, 39, 52, 78 or 104 MHz divided by 5).  FNOTE is the frequency of the desired tone.
            </comment>
        </bits>        
    </reg>
    <reg name="PWT1_Config" protect="rw">
        <bits name="PWT1_Enable" pos="0" access="rw" rst="0">
            <comment>Enables the Pulse Width Tone output
                <br/>1 = Enable PWT output
                <br/>0 = Disable PWT output
            </comment>            
        </bits>
        <bits name="PWT1_Duty" pos="13:4" access="rw" rst="all1">
            <comment>The PWT_Duty value can be used to set the approximate volume of the tone.
                <br/> The PWT_Duty value must be less than or equal to half the PWT_Period value and must be at least a value of 8, otherwise no tone will be generated.
            </comment>
        </bits>
        <bits name="PWT1_Period" pos="26:16" access="rw" rst="all1">
            <comment>PWT_Period is the divider value to produce a tone of a given frequency.
                <br/> To calculate the PWT_Period value, Use the following formula:
                <br/>  PWT_Period = FBASE/FNOTE
                <br/> where FBASE is the frequency of the PWM module clock (it is based on the system frequency, 26, 39, 52, 78 or 104 MHz divided by 5).  FNOTE is the frequency of the desired tone.
            </comment>
        </bits>        
    </reg>
    <reg name="LPG_Config" protect="rw">
        <bits name="LPG_Reset_L"    pos="0"     access="rw" rst="0">
            <comment>Setting this bit to '0' will reset the Light Pulse Generator internal counters.
            </comment>
          </bits>
        <bits name="l_LPG_Test"    pos="1"     access="rw" rst="0">
            <comment>Setting this bit to '0' will reset the Light Pulse Generator internal counters.
            </comment>
        </bits>          
        <bits name="LPG_OnTime" pos="7:4"   access="rw" rst="0xf">
            <comment>Configures the duty cycle for the Light Pulse Generator by setting the ontime for the LPG output. The actual on-time is calculated as: Tick Period * LPG_OnTime * 256 where the Tick Period is nominally 1/16kHz.
            </comment>
            <options>
                <option name="undefined" value="0"/>
                <option name="15_6mS" value="1"/>
                <option name="31_2mS" value="2"/>
                <option name="46_8mS" value="3"/>
                <option name="62mS" value="4"/>
                <option name="78mS" value="5"/>
                <option name="94mS" value="6"/>
                <option name="110mS" value="7"/>
                <option name="125mS" value="8"/>
                <option name="140mS" value="9"/>
                <option name="156mS" value="10"/>
                <option name="172mS" value="11"/>
                <option name="188mS" value="12"/>
                <option name="200mS" value="13"/>
                <option name="218mS" value="14"/>
                <option name="234mS" value="15"/>
                <default/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="LPG_Period"     pos="18:16" access="rw" rst="0">
            <comment>Configures the main period of the light pulse generator. The period is calculated based on the following configurations:
            <br/>with the Tick Period ~ 1/16kHz<br/>
            </comment>
            <options>
                <option name="0_125s" value="0"><comment>Tick Period * 2048</comment></option>
                <option name="0_25s"  value="1"><comment>Tick Period * 4096</comment></option>
                <option name="0_5s"   value="2"><comment>Tick Period * 8192</comment></option>
                <option name="0_75s"  value="3"><comment>Tick Period * 12288</comment></option>
                <option name="1s"     value="4"><comment>Tick Period * 16384</comment></option>
                <option name="1_25s"  value="5"><comment>Tick Period * 20480</comment></option>
                <option name="1_5s"   value="6"><comment>Tick Period * 24576</comment></option>
                <option name="1_75s"  value="7"><comment>Tick Period * 28672</comment></option>
                <default/>
                <mask/>
                <shift/>
            </options>
        </bits>
    </reg>
    <reg name="PWL0_Config" protect="rw">
        <bits name="PWL_Min" pos="7:0" access="rw" rst="all1">
            <comment>Sets the lower boundary for PWL pulse.  When pulse mode is not used, this is the threshold value for the PWL0.  Reading this value will return the current value used for the threshold.
            </comment>
        </bits>
        <bits name="PWL_Max" pos="15:8" access="rw" rst="all1">
            <comment>Sets the upper boundary for PWL pulse.  When pulse mode is not used, this value is ignored.  Reading this value will return the LFSR value used for generating the PWL outputs.
            </comment>
        </bits>
        <bits name="PWL0_En_H" pos="16" access="rs" rst="0">
            <comment>When this bit is written with '1', the PWL 0 is enabled and the output is a PRBS whose average on-time is proportional to PWL_Min.  This bit is cleared when either of the Force bits are written.  Reading this bit will return the current state of the PWL0 enable.
            </comment>
        </bits>
        <bits name="PWL0_Force_L" pos="17" access="rc" rst="0">
            <comment>Writing a '1' to this bit will force the PWL0 to output a low value.  If the PWL0 was previously enabled, this will clear the bit.
            </comment>
        </bits>
        <bits name="PWL0_Force_H" pos="18" access="r" rst="no">
            <comment>Writing a '1' to this bit will force the PWL0 to output a high value.  If the PWL0 was previously enabled, this will clear the bit.
            </comment>
        </bits>
        <bits name="PWL_Pulse_En" pos="19" access="rw" rst="0">
            <comment>This will enable the PWL pulse mode.  The threshold will dynamically sweep between PWL_Min and PWL_Max at a rate depending on PWL_Pulse_Per.
            </comment>
        </bits>
        <bits name="PWL0_Set_OE" pos="20" access="rs" rst="0">
            <comment>Writing '1' to this bit will set the output enable.  Reading this bit will return the current status.
            </comment>
        </bits>
        <bits name="PWL0_Clr_OE" pos="21" access="c" rst="no">
            <comment>Writing '1' to this bit will clear the output enable.
            </comment>
        </bits>
        <bits name="PWL_Set_Mux" pos="22" access="rs" rst="0">
            <comment>Writing a '1' to this bit will swap the PWL0 and PWL1 outputs.  Reading this bit will return the current status.
            </comment>
        </bits>
        <bits name="PWL_Clr_Mux" pos="23" access="c" rst="no">
            <comment>Writing a '1' to this bit will unswap the PWL0/PWL1 outputs.
            </comment>
        </bits>
        <bits name="PWL_Pulse_Per" pos="31:24" access="w" rst="all1">
            <comment>This value will adjust the pulse period when pulsing is enabled.
            </comment>
        </bits>
    </reg>
    <reg name="PWL1_Config" protect="rw">
        <bits name="PWL1_Threshold"         pos="7:0"   access="rw" rst="all1">
            <comment>Average duty cycle for the Pulse Width Light 1 output. The average duty cycle is calculated as PWL1_Threshold/256.
            </comment>
        </bits>
        <bits name="LFSR_Reg"               pos="15:8"  access="r" rst="0xa1">
            <comment>LFSR value for PWL.
            </comment>
        </bits>
        <bits name="PWL1_En_H" pos="16" access="rs" rst="0">
            <comment>When this bit is written with '1', the PWL 1 is enabled and the output is a PRBS whose average on-time is proportional to PWL1_Threshold.  This bit is cleared when either of the Force bits are written.  Reading this bit will return the current state of the PWL1 enable.
            </comment>
        </bits>
        <bits name="PWL1_Force_L" pos="17" access="rc" rst="0">
            <comment>Writing a '1' to this bit will force the PWL1 to output a low value.  If the PWL1 was previously enabled, this will clear the bit.
            </comment>
        </bits>
        <bits name="PWL1_Force_H" pos="18" access="r" rst="no">
            <comment>Writing a '1' to this bit will force the PWL1 to output a high value.  If the PWL1 was previously enabled, this will clear the bit.
            </comment>
        </bits>
        <bits name="PWL1_Set_OE" pos="20" access="rs" rst="0">
            <comment>Writing '1' to this bit will set the output enable.  Reading this bit will return the current status.
            </comment>
        </bits>
        <bits name="PWL1_Clr_OE" pos="21" access="c" rst="no">
            <comment>Writing '1' to this bit will clear the output enable.
            </comment>
        </bits>
    </reg>
    <reg name="TSC_DATA" protect="r">
        <bits name="TSC_X_Value_bit" pos="9:0" access="r" rst="0">
            <comment>TSC X Value. </comment>
        </bits>
        <bits name="TSC_X_Value_valid" pos="10" access="r" rst="0">
            <comment>TSC X Value valid. </comment>
        </bits>
        <bits name="TSC_Y_Value_bit" pos="20:11" access="r" rst="0">
            <comment>TSC Y Value. </comment>
        </bits>
        <bits name="TSC_Y_Value_valid" pos="21" access="r" rst="0">
            <comment>TSC Y Value valid. </comment>
        </bits>
    </reg>
    <reg name="GPADC_DATA" protect="r">
        <bits name="GPADC_Value_bit" pos="9:0" access="r" rst="0">
            <comment>GPADC Value. </comment>
        </bits>
        <bits name="GPADC_Value_valid" pos="10" access="r" rst="0">
            <comment>GPADC Value valid. </comment>
        </bits>
    </reg>
</module>
</archive>
<archive relative="ble_link.xml">
  <module name="ble_link" category="WCN">
    <reg protect="rw" name="RWBLECNTL">
      <bits access="w" name="master_soft_rst" pos="31" rst="0">
        <comment>
          Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 
In case of Dual Mode implementation, reset also common blocks. 
        </comment>
      </bits>
      <bits access="w" name="master_tgsoft_rst" pos="30" rst="0">
        <comment>
          Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="w" name="reg_soft_rst" pos="29" rst="0">
        <comment>
          Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="w" name="swint_req" pos="28" rst="0">
        <comment>
          Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="r" name="RWBLECNTL_reserved_0" pos="27" rst="0">
      </bits>
      <bits access="w" name="rftest_abort" pos="26" rst="0">
        <comment>
          Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 
Note that when RFTEST_ABORT is requested 
  1/ In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC.  
  2/ In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. 
        </comment>
      </bits>
      <bits access="w" name="advert_abort" pos="25" rst="0">
        <comment>
          Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. 
No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="w" name="scan_abort" pos="24" rst="0">
        <comment>
          Abort the current scan window when written with a  1. Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="r" name="RWBLECNTL_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="md_dsb" pos="22" rst="0">
        <comment>
          0: Normal operation of MD bits management 
1: Allow a single Tx/Rx exchange whatever the MD bits are.  
-      value forced by SW from Tx Descriptor 
-      value just saved in Rx Descriptor during reception 
        </comment>
      </bits>
      <bits access="rw" name="sn_dsb" pos="21" rst="0">
        <comment>
          0: Normal operation of Sequence number  
1: Sequence Number Management disabled: 
-      value forced by SW from Tx Descriptor 
-      value ignored in Rx -&gt; No SN error reported. 
        </comment>
      </bits>
      <bits access="rw" name="nesn_dsb" pos="20" rst="0">
        <comment>
          0: Normal operation of Acknowledge   
1: Acknowledge scheme disabled: 
-      value forced by SW from Tx Descriptor 
-      value ignored in Rx -&gt; No NESN error reported. 
        </comment>
      </bits>
      <bits access="rw" name="crypt_dsb" pos="19" rst="0">
        <comment>
          0: Normal operation. Encryption / Decryption enabled.  
1: Encryption / Decryption disabled. 
Note  that  if  CS-CRYPT_EN  is  set,  then  MIC  is  generated,  and  only  data  encryption  is  disabled, meaning data sent are plain data. 
        </comment>
      </bits>
      <bits access="rw" name="whit_dsb" pos="18" rst="0">
        <comment>
          0: Normal operation. Whitening enabled. 
1: Whitening disabled. 
        </comment>
      </bits>
      <bits access="rw" name="crc_dsb" pos="17" rst="0">
        <comment>
          0: Normal operation. CRC removed from data stream. 
1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx. 
        </comment>
      </bits>
      <bits access="rw" name="hop_remap_dsb" pos="16" rst="0">
        <comment>
          0: Normal operation. Frequency Hopping Remapping algorithm enabled. 
1: Frequency Hopping Remapping algorithm disabled 
        </comment>
      </bits>
      <bits access="r" name="RWBLECNTL_reserved_2" pos="15:10" rst="0">
      </bits>
      <bits access="rw" name="advertfilt_en" pos="9" rst="0">
        <comment>
          Advertising Channels Error Filtering Enable control 
0: RW-BLE Core reports all errors to RW-BLE Software 
1: RW-BLE Core reports only correctly received packet, without error to RW-BLE Software 
        </comment>
      </bits>
      <bits access="rw" name="rwble_en" pos="8" rst="0">
        <comment>
          0: Disable RW-BLE Core Exchange Table pre-fetch mechanism. 
1: Enable RW-BLE Core Exchange table pre-fetch mechanism.
        </comment>
      </bits>
      <bits access="rw" name="rxwinszdef" pos="7:4" rst="15">
        <comment>
          Default Rx Window size in us. Used when device 
-      is master connected 
-      performs its second receipt. 
'0' is not a valid value. Recommended value is 10 (in decimal). 
        </comment>
      </bits>
      <bits access="r" name="RWBLECNTL_reserved_3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="syncerr" pos="2:0" rst="0">
        <comment>
          Indicates the maximum number of errors allowed to recognize the synchronization word. 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="VERSION">
      <bits access="r" name="typ" pos="31:24" rst="8">
        <comment>
          RW-BLE Core Type - 0x8 means BLE v4.2 (i.e. correspond LL version assigned number). Correspond to FS v8.0.10) 
        </comment>
      </bits>
      <bits access="r" name="rel" pos="23:16" rst="0">
        <comment>
          RW-BLE Core version - Major release number. Correspond to FS v8.0.10
        </comment>
      </bits>
      <bits access="r" name="upg" pos="15:8" rst="10">
        <comment>
          RW-BLE Core upgrade - Upgrade number. Correspond to FS v8.0.10
        </comment>
      </bits>
      <bits access="r" name="build_num" pos="7:0" rst="0">
        <comment>
          RW-BLE Core Build - Build number 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="RWBLECONF">
      <bits access="r" name="dmmode" pos="31" rst="1">
        <comment>
          0: RW-BLE Core is used as a standalone BLE device 
1: RW-BLE Core is used in a Dual Mode device 
        </comment>
      </bits>
      <bits access="r" name="RWBLECONF_reserved_0" pos="30:26" rst="0">
      </bits>
      <bits access="r" name="isoportnb" pos="25:24" rst="0">
        <comment>
          Number of supported Isochronous Channel (0 to 3) 
00: No ISO/Audio Channel available 
01: One ISO/Audio Channel available 
10: Two ISO/Audio Channels available 
11: Three ISO/Audio Channels available 
        </comment>
      </bits>
      <bits access="r" name="decipher" pos="23" rst="1">
        <comment>
          0: AES deciphering not present 
1: AES deciphering present 
        </comment>
      </bits>
      <bits access="r" name="RWBLECONF_reserved_1" pos="22" rst="0">
      </bits>
      <bits access="r" name="wlancoex" pos="21" rst="0">
        <comment>
          0: WLAN Coexistence mechanism not present 
1: WLAN Coexistence mechanism present (Default Value) 
        </comment>
      </bits>
      <bits access="r" name="rfif" pos="20:16" rst="1">
        <comment>
          RFIF[k]= 0: Control logic supporting radio k not present 
RFIF[k]= 1: Control logic supporting radio k present 
Index k values are: 
 00001: Ripple RF. 
 00010: External Radio Controller Support 
 00100: IcyTRx Radio 
xxx000: Reserved 
Default value is 0000001 
        </comment>
      </bits>
      <bits access="r" name="usedbg" pos="15" rst="1">
        <comment>
          0: Diagnostic port not instantiated 
1: Diagnostic port instantiated (Default Value) 
        </comment>
      </bits>
      <bits access="r" name="usecrypt" pos="14" rst="1">
        <comment>
          0: AES-CCM Encryption block not present 
1: AES-CCM Encryption block present (Default Value) 
        </comment>
      </bits>
      <bits access="r" name="clk_sel" pos="13:8" rst="13">
        <comment>
          Operating Frequency (in MHz) 
Default value is 13MHz 
        </comment>
      </bits>
      <bits access="r" name="intmode" pos="7" rst="1">
        <comment>
          0: Interrupts are edge level generated, i.e. pulse.  
1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement (Default Value) 
        </comment>
      </bits>
      <bits access="r" name="bus_type" pos="6" rst="0">
        <comment>
          Processor Bus Type 
0: AHB Bus 
1: X-Bar Bus 
        </comment>
      </bits>
      <bits access="r" name="data_width" pos="5" rst="1">
        <comment>
          Processor bus width: 
0: 16 bits (Default Value) 
1: 32 bits  
        </comment>
      </bits>
      <bits access="r" name="addr_width" pos="4:0" rst="16">
        <comment>
          Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary. 
Default value is 13 (in decimal) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="INTCNTL">
      <bits access="r" name="INTCNTL_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="cscntdevmsk" pos="15" rst="1">
        <comment>
          CSCNT  interrupt  mask  during  event.  This  bit  allows  to  enable  CSCNT  interrupt  generation  during events (i.e. advertising, scanning, initiating, and connection) 
0: CSCNT Interrupt not generated during events. 
1: CSCNT Interrupt generated during events. 
        </comment>
      </bits>
      <bits access="r" name="INTCNTL_reserved_1" pos="14:13" rst="0">
      </bits>
      <bits access="rw" name="audioint2msk" pos="12" rst="0">
        <comment>
          Audio channel 2 interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="audioint1msk" pos="11" rst="0">
        <comment>
          Audio channel 1 interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="audioint0msk" pos="10" rst="0">
        <comment>
          Audio channel 0 interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="swintmsk" pos="9" rst="0">
        <comment>
          SW triggered interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="eventapfaintmsk" pos="8" rst="1">
        <comment>
          End of event / anticipated pre-fetch abort interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="finetgtimintmsk" pos="7" rst="0">
        <comment>
          Fine Target Timer Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="grosstgtimintmsk" pos="6" rst="0">
        <comment>
          Gross Target Timer Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="errorintmsk" pos="5" rst="0">
        <comment>
          Error Interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="cryptintmsk" pos="4" rst="1">
        <comment>
          Encryption engine Interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="eventintmsk" pos="3" rst="1">
        <comment>
          End of event Interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="slpintmsk" pos="2" rst="1">
        <comment>
          Sleep Mode Interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="rxintmsk" pos="1" rst="1">
        <comment>
          Rx Interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="cscntintmsk" pos="0" rst="1">
        <comment>
          625 us Base Time Interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="INTSTAT">
      <bits access="r" name="INTSTAT_reserved_0" pos="31:13" rst="0">
      </bits>
      <bits access="r" name="audioint2stat" pos="12" rst="0">
        <comment>
          Audio channel 2 interrupt status 
0: No Audio interrupt. 
1: An Audio interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint1stat" pos="11" rst="0">
        <comment>
          Audio channel 1 interrupt status 
0: No Audio interrupt. 
1: An Audio interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint0stat" pos="10" rst="0">
        <comment>
          Audio channel 0 interrupt status 
0: No Audio interrupt. 
1: An Audio interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="swintstat" pos="9" rst="0">
        <comment>
          SW triggered interrupt status 
0: No SW triggered interrupt. 
1: A SW triggered interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="eventapfaintstat" pos="8" rst="0">
        <comment>
          End of event / Anticipated Pre-Fetch Abort interrupt status 
0: No End of Event interrupt. 
1: An End of Event interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="finetgtimintstat" pos="7" rst="0">
        <comment>
          Masked Fine Target Timer Error interrupt status 
0: No Fine Target Timer interrupt. 
1: A Fine Target Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="grosstgtimintstat" pos="6" rst="0">
        <comment>
          Masked Gross Target Timer interrupt status 
0: No Gross Target Timer interrupt. 
1: A Gross Target Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="errorintstat" pos="5" rst="0">
        <comment>
          Masked Error interrupt status 
0: No Error interrupt. 
1: An Error interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="cryptintstat" pos="4" rst="0">
        <comment>
          Masked Encryption engine interrupt status 
0: No Encryption / Decryption interrupt. 
1: An Encryption / Decryption interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="eventintstat" pos="3" rst="0">
        <comment>
          Masked End of Event interrupt status 
0: No End of Advertising / Scanning / Connection interrupt. 
1: An End of Advertising / Scanning / Connection interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="slpintstat" pos="2" rst="0">
        <comment>
          Masked Sleep interrupt status 
0: No End of Sleep Mode interrupt. 
1: An End of Sleep Mode interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="rxintstat" pos="1" rst="0">
        <comment>
          Masked Packet Reception interrupt status 
0: No Rx interrupt. 
1: An Rx interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="cscntintstat" pos="0" rst="0">
        <comment>
          Masked 625 us base time reference interrupt status 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="INTRAWSTAT">
      <bits access="r" name="INTRAWSTAT_reserved_0" pos="31:13" rst="0">
      </bits>
      <bits access="r" name="audioint2rawstat" pos="12" rst="0">
        <comment>
          Audio channel 2 interrupt raw status 
0: No Audio interrupt. 
1: An Audio interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint1rawstat" pos="11" rst="0">
        <comment>
          Audio channel 1 interrupt raw status 
0: No Audio interrupt. 
1: An Audio interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint0rawstat" pos="10" rst="0">
        <comment>
          Audio channel 0 interrupt raw status 
0: No Audio interrupt. 
1: An Audio interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="swintrawstat" pos="9" rst="0">
        <comment>
          SW triggered interrupt raw status 
0: No SW triggered interrupt. 
1: A SW triggered interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="eventapfaintrawstat" pos="8" rst="0">
        <comment>
          End of event / Anticipated Pre-Fetch Abort interrupt raw status 
0: No End of Event interrupt. 
1: An End of Event interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="finetgtimintrawstat" pos="7" rst="0">
        <comment>
          Fine Target Timer Error interrupt raw status 
0: No Fine Target Timer interrupt. 
1: A Fine Target Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="grosstgtimintrawstat" pos="6" rst="0">
        <comment>
          Gross Target Timer interrupt raw status 
0: No Gross Target Timer interrupt. 
1: A Gross Target Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="errorintrawstat" pos="5" rst="0">
        <comment>
          Error interrupt raw status 
0: No Error interrupt. 
1: An Error interrupt is pending.
        </comment>
      </bits>
      <bits access="r" name="cryptintrawstat" pos="4" rst="0">
        <comment>
          Encryption engine interrupt raw status 
0: No Encryption / Decryption interrupt. 
1: An Encryption / Decryption interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="eventintrawstat" pos="3" rst="0">
        <comment>
          End of Event interrupt raw status 
0: No End of Advertising / Scanning / Connection interrupt. 
1: An End of Advertising / Scanning / Connection interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="slpintrawstat" pos="2" rst="0">
        <comment>
          Sleep interrupt raw status 
0: No End of Sleep Mode interrupt. 
1: An End of Sleep Mode interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="rxintrawstat" pos="1" rst="0">
        <comment>
          Packet Reception interrupt raw status 
0: No Rx interrupt. 
1: An Rx interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="cscntintrawstat" pos="0" rst="0">
        <comment>
          625us base time reference interrupt raw status 
0: No 625us Base Time interrupt. 
1: A 625us Base Time interrupt is pending. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="INTACK">
      <bits access="r" name="INTACK_reserved_0" pos="31:13" rst="0">
      </bits>
      <bits access="s" name="audioint2ack" pos="12" rst="0">
        <comment>
        bit type is changed from wos to s.

          Audio channel 2 interrupt acknowledgement bit 
Software  writing  1  acknowledges  the  Audio  channel  2  interrupt.  This  bit  resets  AUDIOINT2STAT  and AUDIOINT2RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="audioint1ack" pos="11" rst="0">
        <comment>
        bit type is changed from wos to s.

          Audio channel 1 interrupt acknowledgement bit 
Software  writing  1  acknowledges  the  Audio  channel  1  interrupt.  This  bit  resets  AUDIOINT1STAT  and AUDIOINT1RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="audioint0ack" pos="10" rst="0">
        <comment>
        bit type is changed from wos to s.

          Audio channel 0 interrupt acknowledgement bit 
Software  writing  1  acknowledges  the  Audio  channel  0  interrupt.  This  bit  resets  AUDIOINT0STAT  and AUDIOINT0RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="swintack" pos="9" rst="0">
        <comment>
        bit type is changed from wos to s.

          SW triggered interrupt acknowledgement bit 
Software   writing   1   acknowledges   the   SW   triggered   interrupt.   This   bit   resets   SWINTSTAT   and SWINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="eventapfaintack" pos="8" rst="0">
        <comment>
        bit type is changed from wos to s.

          End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit 
Software  writing  1  acknowledges  the  End  of  event  /  Anticipated  Pre-Fetch  Abort  interrupt.  This  bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="finetgtimintack" pos="7" rst="0">
        <comment>
        bit type is changed from wos to s.

          Fine Target Timer interrupt acknowledgement bit 
Software  writing  1  acknowledges  the  Fine  Timer  interrupt.  This  bit  resets  FINETGTIMINTSTAT  and FINETGTIMINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="grosstgtimintack" pos="6" rst="0">
        <comment>
        bit type is changed from wos to s.

          Gross Target Timer interrupt acknowledgement bit 
Software writing  1 acknowledges the Gross Timer interrupt. This bit resets  GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="errorintack" pos="5" rst="0">
        <comment>
        bit type is changed from wos to s.

          Error interrupt acknowledgement bit 
Software   writing   1   acknowledges   the   Error   interrupt.   This   bit   resets   ERRORINTSTAT   and ERRORINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="cryptintack" pos="4" rst="0">
        <comment>
        bit type is changed from wos to s.

          Encryption  engine  interrupt  acknowledgement  bit  Software  writing  1  acknowledges  the  Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="eventintack" pos="3" rst="0">
        <comment>
        bit type is changed from wos to s.

          End of Event interrupt acknowledgment bit 
Software  writing  1  acknowledges  the  End  of  Advertising  /  Scanning  /  Connection  interrupt.  This  bit resets SLPINTSTAT and SLPINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="slpintack" pos="2" rst="0">
        <comment>
        bit type is changed from wos to s.

          End of Deep Sleep interrupt acknowledgment bit 
Software  writing  1  acknowledges  the  End  of  Sleep  Mode  interrupt.  This  bit  resets  SLPINTSTAT  and SLPINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="rxintack" pos="1" rst="0">
        <comment>
        bit type is changed from wos to s.

          Packet Reception interrupt acknowledgment bit 
Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="cscntintack" pos="0" rst="0">
        <comment>
        bit type is changed from wos to s.

          625us base time reference interrupt acknowledgment bit 
Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="BASETIMECNT">
      <bits access="w" name="samp" pos="31" rst="0">
        <comment>
          Writing  a  1  samples  the  Base  Time  Counter  value  in  BASETIMECNT  register  field.  Resets  at  0  when action is performed 
        </comment>
      </bits>
      <bits access="r" name="BASETIMECNT_reserved_0" pos="30:27" rst="0">
      </bits>
      <bits access="r" name="basetimecnt" pos="26:0" rst="0">
        <comment>
          Value of the 625us base time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="FINETIMECNT">
      <bits access="r" name="FINETIMECNT_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="r" name="finecnt" pos="9:0" rst="0">
        <comment>
          Value of the current us fine time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="BDADDRL">
      <bits access="rw" name="bdaddrl" pos="31:0" rst="0">
        <comment>
          Bluetooth Low Energy Device Address. LSB part. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="BDADDRU">
      <bits access="r" name="BDADDRU_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="rw" name="priv_npub" pos="16" rst="0">
        <comment>
          Bluetooth Low Energy Device Address privacy indicator 
0: Public Bluetooth Device Address 
1: Private Bluetooth Device Address 
        </comment>
      </bits>
      <bits access="rw" name="bdaddru" pos="15:0" rst="0">
        <comment>
          Bluetooth Low Energy Device Address. MSB part. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ET_CURRENTRXDESCPTR">
      <bits access="rw" name="etptr" pos="31:16" rst="0">
        <comment>
          Exchange Table Pointer that determines the starting point of the Exchange Table 
        </comment>
      </bits>
      <bits access="r" name="ET_CURRENTRXDESCPTR_reserved_0" pos="15" rst="0">
      </bits>
      <bits access="rw" name="currentrxdescptr" pos="14:0" rst="0">
        <comment>
          Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List 
        </comment>
      </bits>
    </reg>
    <hole size="256"/>
    <reg protect="rw" name="DIAGCNTL">
      <bits access="rw" name="diag3_en" pos="31" rst="0">
        <comment>
          0: Disable diagnostic port 3 output. All outputs are set to 0x0. 
1: Enable diagnostic port 3 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_0" pos="30" rst="0">
      </bits>
      <bits access="rw" name="diag3" pos="29:24" rst="0">
        <comment>
          Only relevant when DIAGEN3 = 1. 
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  3.  See  section  2.16  for  a  detailed description. 
        </comment>
      </bits>
      <bits access="rw" name="diag2_en" pos="23" rst="0">
        <comment>
          0: Disable diagnostic port 2 output. All outputs are set to 0x0. 
1: Enable diagnostic port 2 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_1" pos="22" rst="0">
      </bits>
      <bits access="rw" name="diag2" pos="21:16" rst="0">
        <comment>
          Only relevant when DIAGEN2 = 1. 
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  2.  See  section  2.16  for  a  detailed description. 
        </comment>
      </bits>
      <bits access="rw" name="diag1_en" pos="15" rst="0">
        <comment>
          0: Disable diagnostic port 1 output. All outputs are set to 0x0. 
1: Enable diagnostic port 1 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_2" pos="14" rst="0">
      </bits>
      <bits access="rw" name="diag1" pos="13:8" rst="0">
        <comment>
          Only relevant when DIAGEN1 = 1. 
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  1.  See  section  2.16  for  a  detailed description. 
        </comment>
      </bits>
      <bits access="rw" name="diag0_en" pos="7" rst="0">
        <comment>
          0: Disable diagnostic port 0 output. All outputs are set to 0x0. 
1: Enable diagnostic port 0 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_3" pos="6" rst="0">
      </bits>
      <bits access="rw" name="diag0" pos="5:0" rst="0">
        <comment>
          Only relevant when DIAGEN0 = 1. 
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  0.  See  section  2.16  for  a  detailed description. 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="DIAGSTAT">
      <bits access="r" name="diag3stat" pos="31:24" rst="0">
        <comment>
          Directly connected to ble_dbg3[7:0] output. Debug use only. 
        </comment>
      </bits>
      <bits access="r" name="diag2stat" pos="23:16" rst="0">
        <comment>
          Directly connected to ble_dbg2[7:0] output. Debug use only. 
        </comment>
      </bits>
      <bits access="r" name="diag1stat" pos="15:8" rst="0">
        <comment>
          Directly connected to ble_dbg1[7:0] output. Debug use only. 
        </comment>
      </bits>
      <bits access="r" name="diag0stat" pos="7:0" rst="0">
        <comment>
          Directly connected to ble_dbg0[7:0] output. Debug use only. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DEBUGADDMAX">
      <bits access="rw" name="reg_addmax" pos="31:16" rst="0">
        <comment>
          Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.16) 
        </comment>
      </bits>
      <bits access="rw" name="em_addmax" pos="15:0" rst="0">
        <comment>
          Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DEBUGADDMIN">
      <bits access="rw" name="reg_addmin" pos="31:16" rst="0">
        <comment>
          Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.16) 
        </comment>
      </bits>
      <bits access="rw" name="em_addmin" pos="15:0" rst="0">
        <comment>
          Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16) 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="ERRORTYPESTAT">
      <bits access="r" name="ERRORTYPESTAT_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="r" name="ral_underrun" pos="19" rst="0">
        <comment>
          Indicates  Resolving  Address  List  engine  Under  run  issue,  happens  when  RAL  List  parsing  not finished on time 
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="ral_error" pos="18" rst="0">
        <comment>
          Indicates Resolving Address List engine faced a bad setting (e.g CS-RAL_EN = 1 and null RALPTR, or RALPTR &gt; CS-PEER_RALPTR).  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="concevtirq_error" pos="17" rst="0">
        <comment>
          Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the RW-BLE Software.  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="rxdata_ptr_error" pos="16" rst="0">
        <comment>
          Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure.  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="txdata_ptr_error" pos="15" rst="0">
        <comment>
          Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning /  Initiating  events,  or  during  Master  /  Slave  connections  with  non-null  packet  length:  this  is  a major programming failure.  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="rxdesc_empty_error" pos="14" rst="0">
        <comment>
          Indicates  whether  Rx  Descriptor  pointer  value  programmed  in  register  is  null:  this  is  a  major programming failure.  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="txdesc_empty_error" pos="13" rst="0">
        <comment>
          Indicates  whether  Tx  Descriptor  pointer  value  programmed  in  Control  Structure  is  null  during Advertising / Scanning / Initiating events: this is a major programming failure.  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="csformat_error" pos="12" rst="0">
        <comment>
          Indicates  whether  CS-FORMAT  has  been  programmed  with  an  invalid  value:  this  is  a  major software programming failure.  
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="llchmap_error" pos="11" rst="0">
        <comment>
          Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="adv_underrun" pos="10" rst="0">
        <comment>
          Indicates  Advertising  Interval  Under  run,  occurs  if  time  between  two  consecutive  Advertising packet (in Advertising mode) is lower than described in Table 3-11.  
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="ifs_underrun" pos="9" rst="0">
        <comment>
          Indicates  Inter  Frame  Space  Under  run,  occurs  if  IFS  time  is  not  enough  to  update  and  read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="whitelist_error" pos="8" rst="0">
        <comment>
          Indicates White List Timeout error, occurs if White List parsing is not finished on time 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="evt_cntl_apfm_error" pos="7" rst="0">
        <comment>
          Indicates  Anticipated  Pre-Fetch  Mechanism  error:  happens  when  2  consecutive  events  are programmed, and when the first event is not completely finished while second pre-fetch instant is reached.  
0: No error 
1: Error occured 
        </comment>
      </bits>
      <bits access="r" name="evt_schdl_apfm_error" pos="6" rst="0">
        <comment>
          Indicates  Anticipated  Pre-Fetch  Mechanism  error:  happens  when  2  consecutive  events  are programmed, and when the first event is not completely finished while second pre-fetch instant is reached.  
0: No error 
1: Error occured 
        </comment>
      </bits>
      <bits access="r" name="evt_schdl_entry_error" pos="5" rst="0">
        <comment>
          Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624us offset and second one with no offset) 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="evt_schdl_emacc_error" pos="4" rst="0">
        <comment>
          Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="radio_emacc_error" pos="3" rst="0">
        <comment>
          Indicates  Radio  Controller  Exchange  Memory  access  error,  happens  when  Exchange  Memory accesses are not served in time and data are corrupted.  
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="pktcntl_emacc_error" pos="2" rst="0">
        <comment>
          Indicates  Packet  Controller  Exchange  Memory  access  error,  happens  when  Exchange  Memory accesses are not served in time and Tx/Rx data are corrupted 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="rxcrypt_error" pos="1" rst="0">
        <comment>
          Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to  Packet  Controller  requests.  A  16-bytes  block  has  to  be  decrypted  prior  the  next  block  is received by the Packet Controller 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="txcrypt_error" pos="0" rst="0">
        <comment>
          Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to  Packet  Controller  requests.  A  16-bytes  block  has  to  be  encrypted  and  prepared  on  Packet Controller request, and needs to be ready before the Packet Controller has to send ti 
0: No error 
1: Error occurred 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="SWPROFILING">
      <bits access="rw" name="swprof" pos="31:0" rst="0">
        <comment>
          Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port (Please refer to section 2.16 for details) 
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="RADIOCNTL0">
      <bits access="r" name="RADIOCNTL0_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="sync_pulse_mode" pos="23" rst="0">
        <comment>
          Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet.
0: Access Code detection indicator provided as pulse
1: Access Code detection indicator provided as level
        </comment>
      </bits>
      <bits access="rw" name="dpcorr_en" pos="22" rst="0">
        <comment>
          Enables the use of the delayed DC offset compensated data path in Radio Correlator block.
1: Enable
0: Disable
        </comment>
      </bits>
      <bits access="rw" name="forceagc_en" pos="21" rst="0">
        <comment>
          Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value
1: Enable
0: Disable
        </comment>
      </bits>
      <bits access="rw" name="forcebleiq" pos="20" rst="0">
        <comment>
          Control Ripple modulation mode in between FM and I&amp;Q
1: I&amp;Q modulation mode
0: FM modulation mode
        </comment>
      </bits>
      <bits access="rw" name="jef_select" pos="19" rst="0">
        <comment>
          Selects Jitter Elimination FIFO
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL0_reserved_1" pos="18:7" rst="0">
      </bits>
      <bits access="rw" name="spifreq" pos="6:5" rst="0">
        <comment>
          Frequency of the SPI clock
00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz)
01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz)
10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz)
11: Do not use
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL0_reserved_2" pos="4:2" rst="0">
      </bits>
      <bits access="r" name="spicomp" pos="1" rst="1">
        <comment>
          This bit is READ ONLY.
0: Indicates that the SPI transfer is in progress.
1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer.
        </comment>
      </bits>
      <bits access="w" name="spigo" pos="0" rst="0">
        <comment>
          Software writing 1 triggers the SPI access. This bit is always read as 0.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOCNTL1">
      <bits access="r" name="RADIOCNTL1_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="subversion" pos="27:24" rst="0">
        <comment>
          Has no effect on Radio Controller
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL1_reserved_1" pos="23:21" rst="0">
      </bits>
      <bits access="rw" name="xrfsel" pos="20:16" rst="0">
        <comment>
          Extended radio selection field
5'b00000: No radio selected
5'b00001: RivieraWaves Ripple RF (BT4.0)
5'b00010: External Radio controller support
5'b00011-5'b11111: reserved
        </comment>
      </bits>
      <bits access="rw" name="spiptr" pos="15:0" rst="0">
        <comment>
          Pointer to the buffer containing data to be transferred to or received from the SPI port.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOCNTL2">
      <bits access="rw" name="rfrxtmda" pos="31:28" rst="0">
        <comment>
          RF Rx Test Mode Delay Adjustment
        </comment>
      </bits>
      <bits access="rw" name="tx_delay" pos="27:24" rst="0">
        <comment>
          Used to compensate Modem &amp; RF Tx delay. When used, rtrip_delay should be set as Rx delay
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL2_reserved_0" pos="23" rst="0">
      </bits>
      <bits access="rw" name="sync_position" pos="22:16" rst="0">
        <comment>
          Defines sync_p instant when provided to the Modem.
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL2_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="forceagc_length" pos="11:0" rst="0">
        <comment>
          Defines Rx window time threshold that forces Ripple AGC to max gain
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOCNTL3">
      <bits access="r" name="RADIOCNTL3_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="freqtable_ptr" pos="15:0" rst="64">
        <comment>
          BR/EDR Frequency Table pointer
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOPWRUPDN">
      <bits access="r" name="RADIOPWRUPDN_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="rtrip_delay" pos="30:24" rst="0">
        <comment>
          Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in us 
        </comment>
      </bits>
      <bits access="rw" name="rxpwrup" pos="23:16" rst="210">
        <comment>
          This register holds the  length in us of the RX power  up  phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. 
        </comment>
      </bits>
      <bits access="r" name="RADIOPWRUPDN_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="txpwrdn" pos="12:8" rst="3">
        <comment>
          This  register  extends  the  length  in us  of  the  TX  power  down  phase  for  the  current  radio  device. Default value is 3us (reset value). Operating range depends on the selected radio. 
        </comment>
      </bits>
      <bits access="rw" name="txpwrup" pos="7:0" rst="210">
        <comment>
          This  register  holds  the  length  in us  of  the  TX  power  up  phase  for  the  current  radio  device.  Default value is 210us (reset value). Operating range depends on the selected radio. 
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="rw" name="ADVCHMAP">
      <bits access="r" name="ADVCHMAP_reserved_0" pos="31:3" rst="0">
      </bits>
      <bits access="rw" name="advchmap" pos="2:0" rst="7">
        <comment>
          Advertising  Channel  Map,  defined  as  per  the  advertising  connection  settings.  Contains  advertising channels index 37 to 39. If ADVCHMAP[i] equals: 
0: Do not use data channel i+37. 
1: Use data channel i+37. 
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="rw" name="ADVTIM">
      <bits access="r" name="ADVTIM_reserved_0" pos="31:14" rst="0">
      </bits>
      <bits access="rw" name="advint" pos="13:0" rst="0">
        <comment>
          Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. 
Value is in us. 
Value  to  program  depends  on  the  used  Advertising  Packet  type  and  the  device  filtering  policy. 
Please refer to Table 3-11 for details about ADVINT programming range.  
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="ACTSCANSTAT">
      <bits access="r" name="ACTSCANSTAT_reserved_0" pos="31:25" rst="0">
      </bits>
      <bits access="r" name="backoff" pos="24:16" rst="1">
        <comment>
          Active scan mode back-off counter initialization value.  
        </comment>
      </bits>
      <bits access="r" name="ACTSCANSTAT_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="r" name="upperlimit" pos="8:0" rst="1">
        <comment>
          Active scan mode upper limit counter value. 
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="WLPUBADDPTR">
      <bits access="r" name="WLPUBADDPTR_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="wlpubaddptr" pos="15:0" rst="0">
        <comment>
          Start address pointer of the public devices white list.  
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="WLPRIVADDPTR">
      <bits access="r" name="WLPRIVADDPTR_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="wlprivaddptr" pos="15:0" rst="0">
        <comment>
          Start address pointer of the private devices white list.  
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="WLNBDEV">
      <bits access="r" name="WLNBDEV_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="nbprivdev" pos="15:8" rst="0">
        <comment>
          Number of private devices in the white list.  
        </comment>
      </bits>
      <bits access="rw" name="nbpubdev" pos="7:0" rst="0">
        <comment>
          Number of public devices in the white list. 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="AESCNTL">
      <bits access="r" name="AESCNTL_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="rw" name="aes_mode" pos="1" rst="0">
        <comment>
          0: Cipher mode 
1: Decipher mode 
        </comment>
      </bits>
      <bits access="w" name="aes_start" pos="0" rst="0">
        <comment>
          Writing a 1 starts AES-128 ciphering/deciphering process. 
This bit is reset once the process is finished (i.e. ble_crypt_irq interrupt occurs, even masked) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="AESKEY31_0">
      <bits access="rw" name="aeskey31_0" pos="31:0" rst="0">
        <comment>
          AES encryption 128-bit key. Bit 31 down to 0 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="AESKEY63_32">
      <bits access="rw" name="aeskey63_32" pos="31:0" rst="0">
        <comment>
          AES encryption 128-bit key. Bit 63 down to 32 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="AESKEY95_64">
      <bits access="rw" name="aeskey95_64" pos="31:0" rst="0">
        <comment>
          AES encryption 128-bit key. Bit 95 down to 64 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="AESKEY127_96">
      <bits access="rw" name="aeskey127_96" pos="31:0" rst="0">
        <comment>
          AES encryption 128-bit key. Bit 127 down to 96 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="AESPTR">
      <bits access="r" name="AESPTR_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="aesptr" pos="15:0" rst="0">
        <comment>
          Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="TXMICVAL">
      <bits access="r" name="txmicval" pos="31:0" rst="0">
        <comment>
          AES-CCM plain MIC value. Valid on when MIC has been calculated (in Tx) 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="RXMICVAL">
      <bits access="r" name="rxmicval" pos="31:0" rst="0">
        <comment>
          AES-CCM plain MIC value. Valid on once MIC has been extracted from Rx packet. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RFTESTCNTL">
      <bits access="rw" name="infiniterx" pos="31" rst="0">
        <comment>
          Applicable to all event type 
0: Normal mode of operation 
1: Infinite Rx window 
        </comment>
      </bits>
      <bits access="r" name="RFTESTCNTL_reserved_0" pos="30:28" rst="0">
      </bits>
      <bits access="rw" name="rxpktcnten" pos="27" rst="0">
        <comment>
          Applicable in RF Direct Rx Test mode only 
0: Rx packet count disabled 
1:  Rx  packet  count  enabled,  and  reported  in  CS-RXCCMPKTCNT  and  RFTESTRXSTAT-RXPKTCNT  on RF abort command 
        </comment>
      </bits>
      <bits access="r" name="RFTESTCNTL_reserved_1" pos="26:16" rst="0">
      </bits>
      <bits access="rw" name="infinitetx" pos="15" rst="0">
        <comment>
          Applicable to all event type 
0: Normal mode of operation. 
1: Infinite Tx packet / Normal start of a packet but endless payload 
        </comment>
      </bits>
      <bits access="rw" name="txlengthsrc" pos="14" rst="0">
        <comment>
          Applicable to all event type 
0: Normal mode of operation: TxDESC-&lt;TXADVLEN/TXLEN&gt; controls the Tx packet payload size 
1: Uses RFTESTCNTL-TXLENGTH packet length (can support up to 512 bytes transmit) 
        </comment>
      </bits>
      <bits access="rw" name="prbstype" pos="13" rst="0">
        <comment>
          Defines the PRBS in use 
0: Tx Packet Payload are PRBS9 type 
1: Tx Packet Payload are PRBS15 type 
        </comment>
      </bits>
      <bits access="rw" name="txpldsrc" pos="12" rst="0">
        <comment>
          Applicable to all event type 
0: Tx Packet Payload source is the Control Structure 
1: Tx Packet Payload are PRBS generator 
        </comment>
      </bits>
      <bits access="rw" name="txpktcnten" pos="11" rst="0">
        <comment>
          Applicable in RF Direct Tx Test mode only 
0: Tx packet count disabled 
1: Tx packet count enabled, and reported in CS-TXCCMPKTCNT and RFTESTTXSTAT-TXPKTCNT on RF abort command 
        </comment>
      </bits>
      <bits access="r" name="RFTESTCNTL_reserved_2" pos="10:9" rst="0">
      </bits>
      <bits access="rw" name="txlength" pos="8:0" rst="0">
        <comment>
          Applicable to all event type, valid when RFTESTCNTL-TXLENGTHSRC = 1 
Tx packet length in number of byte 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="RFTESTTXSTAT">
      <bits access="r" name="txpktcnt" pos="31:0" rst="0">
        <comment>
          Reports number of transmitted packet during Test Modes. 
Value is valid if RFTESTCNTL-TXPKTCNTEN is set 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="RFTESTRXSTAT">
      <bits access="r" name="rxpktcnt" pos="31:0" rst="0">
        <comment>
          Reports number of correctly received packet during Test Modes (no sync error, no CRC error). 
Value is valid if RFTESTCNTL-RXPKTCNTEN is set 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="TIMGENCNTL">
      <bits access="rw" name="apfm_en" pos="31" rst="1">
        <comment>
          Controls the Anticipated pre-Fetch Abort mechanism 
0: Disabled 
1: Enabled 
        </comment>
      </bits>
      <bits access="r" name="TIMGENCNTL_reserved_0" pos="30:26" rst="0">
      </bits>
      <bits access="rw" name="prefetchabort_time" pos="25:16" rst="510">
        <comment>
           Defines the instant in us at which immediate abort is required after anticipated pre-fetch abort 
        </comment>
      </bits>
      <bits access="r" name="TIMGENCNTL_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rw" name="prefetch_time" pos="8:0" rst="150">
        <comment>
          Defines Exchange Table pre-fetch instant in us 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GROSSTIMTGT">
      <bits access="r" name="GROSSTIMTGT_reserved_0" pos="31:23" rst="0">
      </bits>
      <bits access="rw" name="grosstarget" pos="22:0" rst="0">
        <comment>
          Gross  Timer  Target  value  on  which  a  ble_grosstgtim_irq  must  be  generated.  This  timer  has  a precision  of  10ms:  interrupt  is  generated  only  when  GROSSTARGET[22:0]  =  BASETIMECNT[26:4] and BASETIMECNT[3:0] = 0. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="FINETIMTGT">
      <bits access="r" name="FINETIMTGT_reserved_0" pos="31:27" rst="0">
      </bits>
      <bits access="rw" name="finetarget" pos="26:0" rst="0">
        <comment>
          Fine Timer Target value on which a ble_finetgtim_irq must be generated. This timer has a precision of 625us: interrupt is generated only when FINETARGET = BASETIMECNT 
        </comment>
      </bits>
    </reg>
    <hole size="288"/>
    <reg protect="rw" name="RALPTR">
      <bits access="r" name="RALPTR_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="ralptr" pos="15:0" rst="0">
        <comment>
          Start address pointer of the RAL structure 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RALNBDEV">
      <bits access="r" name="RALNBDEV_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="rw" name="nbraldev" pos="7:0" rst="0">
        <comment>
          Number of devices in RAL Structure 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RAL_LOCAL_RND">
      <bits access="w" name="lrnd_init" pos="31" rst="0">
        <comment>
          Writing a 1 initializes of Local RPA random number generation LFSR 
This bit is reset once the LFSR is loaded 
        </comment>
      </bits>
      <bits access="r" name="RAL_LOCAL_RND_reserved_0" pos="30:22" rst="0">
      </bits>
      <bits access="rw" name="lrnd_val" pos="21:0" rst="4132623">
        <comment>
          Initialization value for  Local RPA random generation when LRDN_INIT is set to 1, else reports the current Local RPA random number LFSR value 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RAL_PEER_RND">
      <bits access="w" name="prnd_init" pos="31" rst="0">
        <comment>
          Writing a 1 initializes of Peer RPA random number generation LFSR 
This bit is reset once the LFSR is loaded 
        </comment>
      </bits>
      <bits access="r" name="RAL_PEER_RND_reserved_0" pos="30:22" rst="0">
      </bits>
      <bits access="rw" name="prnd_val" pos="21:0" rst="3207408">
        <comment>
          Initialization  value  for  Peer  RPA  random  generation  when  PRDN_INIT  is  set  to  1,  else  reports the current Peer RPA random number LFSR value 
        </comment>
      </bits>
    </reg>
    <hole size="768"/>
    <reg protect="rw" name="BLEPRIOSCHARB">
      <bits access="r" name="BLEPRIOSCHARB_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="blepriomode" pos="15" rst="0">
        <comment>
          Determine BLE Priority Scheduling Arbitration Mode 
0: BLE Decision instant not used 
1: BLE Decision instant used 
        </comment>
      </bits>
      <bits access="r" name="BLEPRIOSCHARB_reserved_1" pos="14:8" rst="0">
      </bits>
      <bits access="rw" name="blemargin" pos="7:0" rst="0">
        <comment>
          Determine the decision instant margin for Priority Scheduling Arbitration. 
Decision instant is defined as per formula of section 3.6 
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_aud_ifc.xml">
  <module name="bt_aud_ifc" category="WCN">
    <hole size="512"/>
    <reg protect="w" name="ch__control">
      <bits access="w" name="control_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="w" name="auto_disable" pos="4" rst="0">
        <comment>
          Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.
        </comment>
      </bits>
      <bits access="w" name="control_reserved_1" pos="3:2" rst="0">
      </bits>
      <bits access="w" name="disable" pos="1" rst="0">
        <comment>
          Channel Disable, write one in this bit disable the channel. 
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled.
        </comment>
      </bits>
      <bits access="w" name="enable" pos="0" rst="0">
        <comment>
          Channel Enable, write one in this bit enable the channel. 
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="ch__status">
      <bits access="r" name="status_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="r" name="i3_4f" pos="19" rst="0">
        <comment>
          Three Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="i4f" pos="18" rst="0">
        <comment>
          Quarter of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ihf" pos="17" rst="0">
        <comment>
          Half of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="ief" pos="16" rst="0">
        <comment>
          End of FIFO interrupt status bit.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="r" name="cause_i3_4f" pos="11" rst="0">
        <comment>
          Cause interrupt Three Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_i4f" pos="10" rst="0">
        <comment>
          Cause interrupt Quarter of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ihf" pos="9" rst="0">
        <comment>
          Cause interrupt Half of FIFO.
        </comment>
      </bits>
      <bits access="r" name="cause_ief" pos="8" rst="0">
        <comment>
          Cause interrupt End of FIFO.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>
          When 1 the fifo is empty
        </comment>
      </bits>
      <bits access="r" name="status_reserved_3" pos="3:2" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="1" rst="0">
      </bits>
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>
          When 1 the channel is enabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ch__start_addr">
      <bits access="rw" name="start_addr" pos="31:2" rst="1073741823">
        <comment>
          AHB Start Address. This field represent the start address of the FIFO located in RAM.
        </comment>
      </bits>
      <bits access="r" name="start_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch__fifo_size">
      <bits access="r" name="fifo_size_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rw" name="fifo_size" pos="14:4" rst="2047">
        <comment>
          Fifo size in bytes, max 32kBytes. 
The size of the fifo must be a multiple of 16 (The four LSB are always zero).
        </comment>
      </bits>
      <bits access="r" name="fifo_size_reserved_1" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch__reserved">
      <bits access="r" name="reserved_reserved_0" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch__int_mask">
      <bits access="r" name="int_mask_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
          THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="quarter_fifo" pos="10" rst="0">
        <comment>
          QUARTER FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="half_fifo" pos="9" rst="0">
        <comment>
          HALF FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="rw" name="end_fifo" pos="8" rst="0">
        <comment>
          END FIFO Mask interrupt. When one this interrupt is enabled.
        </comment>
      </bits>
      <bits access="r" name="int_mask_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="ch__int_clear">
      <bits access="r" name="int_clear_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rc" name="three_quarter_fifo" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Three Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="quarter_fifo" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear Quarter fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="half_fifo" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear half of fifo interrupt.
        </comment>
      </bits>
      <bits access="rc" name="end_fifo" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          Write one to clear end of fifo interrupt.
        </comment>
      </bits>
      <bits access="r" name="int_clear_reserved_1" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="ch__cur_ahb_addr">
      <bits access="r" name="cur_ahb_addr" pos="31:2" rst="1073741823">
        <comment>
          Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.
        </comment>
      </bits>
      <bits access="r" name="cur_ahb_addr_reserved_0" pos="1:0" rst="0">
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_comregs.xml">
  <module name="bt_comregs" category="WCN">
    <reg protect="r" name="snapshot">
      <bits access="r" name="snapshot_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="snapshot" pos="1:0" rst="0">
        <comment>
          Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="snapshot_cfg">
      <bits access="r" name="snapshot_cfg_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="snapshot_cfg_rd" pos="1" rst="1">
      </bits>
      <bits access="rw" name="snapshot_cfg" pos="0" rst="0">
        <comment>
          number of snapshot
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="cause">
      <bits access="r" name="cause_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="irq1_cause" pos="15:8" rst="0">
        <comment>
          When read from the Xcpu, this return the cause of interruption, basically the set/clear register X_Irq1 part masked with X_Irq1_Mask
When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask
        </comment>
      </bits>
      <bits access="r" name="irq0_cause" pos="7:0" rst="0">
        <comment>
          When read from the Xcpu, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask
When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mask_set">
      <bits access="r" name="mask_set_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rs" name="irq1_mask_set" pos="15:8" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          When read: returns the value of the Irq1_Mask register.
                When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0
        </comment>
      </bits>
      <bits access="rs" name="irq0_mask_set" pos="7:0" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          When read: returns the value of the Irq0_Mask register.
                When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mask_clr">
      <bits access="r" name="mask_clr_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="irq1_mask_clr" pos="15:8" rst="0">
        <comment>
        bit type is changed from rc to r.

          When read: returns the value of the Irq1_Mask register.
                When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 1
        </comment>
      </bits>
      <bits access="r" name="irq0_mask_clr" pos="7:0" rst="0">
        <comment>
        bit type is changed from rc to r.

          When read: returns the value of the Irq0_Mask register.
                When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="itreg_set">
      <bits access="r" name="itreg_set_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rc" name="irq1_set" pos="15:8" rst="0">
        <comment>
        bit type is changed from w0c to rc.

          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled
        </comment>
      </bits>
      <bits access="rc" name="irq0_set" pos="7:0" rst="0">
        <comment>
        bit type is changed from w0c to rc.

          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="itreg_clr">
      <bits access="r" name="itreg_clr_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="irq1_clr" pos="15:8" rst="0">
        <comment>
        bit type is changed from rc to r.

          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled.
        </comment>
      </bits>
      <bits access="r" name="irq0_clr" pos="7:0" rst="0">
        <comment>
        bit type is changed from rc to r.

          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_core.xml">
  <module name="bt_core" category="WCN">
    <reg protect="rw" name="common_ctrl">
      <bits access="r" name="typ" pos="31:28" rst="2">
        <comment>
          Version type of bt_core. 1 for BTDM old version. 2 for BTDM new version. 3 for BLE only.
        </comment>
      </bits>
      <bits access="r" name="rel" pos="27:24" rst="0">
        <comment>
          Major release number of bt_core
        </comment>
      </bits>
      <bits access="r" name="upg" pos="23:20" rst="0">
        <comment>
          Upgrade number of bt_core
        </comment>
      </bits>
      <bits access="r" name="common_ctrl_reserved_0" pos="19:3" rst="0">
      </bits>
      <bits access="rw" name="infinite_entry" pos="2" rst="0">
        <comment>
          Set to 1 to force status of exchange table entry to be ready
        </comment>
      </bits>
      <bits access="rw" name="rf_ext_slave" pos="1" rst="0">
        <comment>
          Set to 1 when working as a plug-in RF&amp;modem board. Set to 0 in all other modes
        </comment>
      </bits>
      <bits access="rw" name="rf_ext_master" pos="0" rst="0">
        <comment>
          Set to 1 when using plug-in RF&amp;modem board. Set to 0 in all other modes
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tport_ctrl">
      <bits access="r" name="tport_ctrl_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="tport_clk_sel" pos="27:24" rst="0">
        <comment>
          select tport clock
        </comment>
      </bits>
      <bits access="r" name="tport_ctrl_reserved_1" pos="23:20" rst="0">
      </bits>
      <bits access="rw" name="tport_trig_sel" pos="19:16" rst="0">
        <comment>
          select tport trigger
        </comment>
      </bits>
      <bits access="r" name="tport_ctrl_reserved_2" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="tport_data1_sel" pos="11:8" rst="0">
        <comment>
          select tport data1
        </comment>
      </bits>
      <bits access="r" name="tport_ctrl_reserved_3" pos="7:4" rst="0">
      </bits>
      <bits access="rw" name="tport_data0_sel" pos="3:0" rst="0">
        <comment>
          select tport data0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rf_pllfreq_sel_0">
      <bits access="rw" name="pllfreq_sel_31_0" pos="31:0" rst="0">
        <comment>
          select pll frequency for rf/modem for channel 0~31
1 for 214.5MHz and 0 for 208MHz
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rf_pllfreq_sel_1">
      <bits access="rw" name="pllfreq_sel_63_32" pos="31:0" rst="0">
        <comment>
          select pll frequency for rf/modem for channel 32~63
1 for 214.5MHz and 0 for 208MHz
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rf_pllfreq_sel_2">
      <bits access="r" name="rf_pllfreq_sel_2_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rw" name="pllfreq_sel_78_64" pos="14:0" rst="0">
        <comment>
          select pll frequency for rf/modem for channel 64~78
1 for 214.5MHz and 0 for 208MHz
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="trx_on_force">
      <bits access="r" name="trx_on_force_reserved_0" pos="31:6" rst="0">
      </bits>
      <bits access="rw" name="tx_cal_en" pos="5" rst="0">
        <comment>
          tx calibration enable
        </comment>
      </bits>
      <bits access="rw" name="rx_cal_en" pos="4" rst="0">
        <comment>
          rx calibration enable
        </comment>
      </bits>
      <bits access="rw" name="txon_force" pos="3" rst="0">
        <comment>
          force txon for rf to txon_value when txon_force is 1
        </comment>
      </bits>
      <bits access="rw" name="txon_value" pos="2" rst="0">
      </bits>
      <bits access="rw" name="rxon_force" pos="1" rst="0">
        <comment>
          force rxon for rf to rxon_value when rxon_force is 1
        </comment>
      </bits>
      <bits access="rw" name="rxon_value" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="trx_on_timing">
      <bits access="rw" name="modem_txon_delay" pos="31:24" rst="48">
        <comment>
          delay time in us to enable modem tx after link layer txon enable
        </comment>
      </bits>
      <bits access="rw" name="modem_rf_txoff_delay" pos="23:16" rst="16">
        <comment>
          delay time in us to disable modem&amp;rf tx after link layer txon disable
        </comment>
      </bits>
      <bits access="rw" name="modem_rxon_delay" pos="15:8" rst="48">
        <comment>
          delay time in us to enable modem rx after link layer rxon enable
        </comment>
      </bits>
      <bits access="rw" name="modem_rf_rxoff_delay" pos="7:0" rst="0">
        <comment>
          delay time in us to disable modem&amp;rf rx after link layer rxon disable
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_dbm.xml">
  <module name="bt_dbm" category="WCN">
    <reg protect="rw" name="sel">
      <bits access="r" name="sel_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="rw" name="src_sel" pos="1" rst="0">
        <comment>
          source selection
0 : modem
1 : other
        </comment>
      </bits>
      <bits access="rw" name="dbm_en" pos="0" rst="0">
        <comment>
          debug bus master enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="trans">
      <bits access="rw" name="word_len" pos="31:12" rst="0">
        <comment>
          transfer word length
        </comment>
      </bits>
      <bits access="rw" name="data_sel" pos="11:8" rst="0">
        <comment>
          data selection
        </comment>
      </bits>
      <bits access="rw" name="dump_trig_sel" pos="7" rst="0">
        <comment>
          dump trigger selection
select trigger from soft or hardware
        </comment>
      </bits>
      <bits access="rw" name="wrap_en" pos="6" rst="0">
        <comment>
          wrap the whole fifo, when EOF, keep on write by the start addr
        </comment>
      </bits>
      <bits access="rw" name="burst_type" pos="5:4" rst="0">
        <comment>
          burst type
2'h00:: single
2'h01:: incr4
2'b10:: incr8
2'b11:: incrx
        </comment>
      </bits>
      <bits access="rw" name="burst_len" pos="3:0" rst="0">
        <comment>
          length of burst when incrx
max incr16
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="start_addr">
      <bits access="rw" name="start_addr" pos="31:0" rst="0">
        <comment>
          start address of transfer
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mask">
      <bits access="r" name="mask_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="rw" name="mask_trans_err" pos="3" rst="0">
        <comment>
          mask for transfer error
        </comment>
      </bits>
      <bits access="rw" name="mask_ovfl" pos="2" rst="0">
        <comment>
          mask for ovfl 
        </comment>
      </bits>
      <bits access="rw" name="mask_comp_half" pos="1" rst="0">
        <comment>
          mask for comp half
        </comment>
      </bits>
      <bits access="rw" name="mask_comp_end" pos="0" rst="0">
        <comment>
          mask for comp end
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="status">
      <bits access="r" name="status_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="rc" name="int_trans_err_status" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          interrupt for ahb transfer error
        </comment>
      </bits>
      <bits access="rc" name="int_ovfl_status" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          interrupt from fifo overfolw
        </comment>
      </bits>
      <bits access="rc" name="int_comp_half_status" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          half interrupt from transfer complete
        </comment>
      </bits>
      <bits access="rc" name="int_comp_end_status" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          end interrupt from transfer complete
        </comment>
      </bits>
      <bits access="rc" name="srst_done_status" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          data_packer soft reset done
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="soft_reset">
      <bits access="r" name="soft_reset_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="s" name="s_reset" pos="0" rst="0">
        <comment>
        bit type is changed from wos to s.

          soft reset
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="soft_trig">
      <bits access="r" name="soft_trig_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="s" name="s_dp_trig" pos="0" rst="0">
        <comment>
        bit type is changed from wos to s.

          dump trigger from soft
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_link.xml">
  <module name="bt_link" category="WCN">
    <reg protect="rw" name="RWBTCNT">
      <bits access="w" name="master_soft_rst" pos="31" rst="0">
        <comment>
          Reset the complete RW-BT Core except timing generator and register blocks, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. In case of Dual Mode implementation, reset also common blocks. 
        </comment>
      </bits>
      <bits access="w" name="master_tgsoft_rst" pos="30" rst="0">
        <comment>
          Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.  
        </comment>
      </bits>
      <bits access="w" name="reg_soft_rst" pos="29" rst="0">
        <comment>
          Reset the complete register block, when written with a 1. 
Resets at 0 when action is performed. No action happens if it is written with 0.
        </comment>
      </bits>
      <bits access="w" name="swint_req" pos="28" rst="0">
        <comment>
          Forces  the  generation  of  bt_sw_irq  when  written  with  a  1,  and  proper  masking  is  set.  Resets  at  0 when action is performed. No action happens if it is written with 0.  
        </comment>
      </bits>
      <bits access="w" name="scan_abort" pos="27" rst="0">
        <comment>
          Abort the current Inquiry / Page / Broadcast scan window when written with a 1. 
Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="w" name="rftest_abort" pos="26" rst="0">
        <comment>
          Abort the current RF Testing when written with a 1. 
Resets at 0 when action is performed. No action happens if it is written with 0.  
Note that when RFTEST_ABORT is requested  
1/ In case of infinite Tx, the Packet Controller FSM stops at the  end of the  current byte in process, and processes accordingly the packet CRC.  
2/  In  case  of  Infinite  Rx,  the  Packet  Controller  FSM  either  stops  as  the  end  of  the  current  Packet reception (if Access address has been detected), or simply stop the processing switching off the RF.  
        </comment>
      </bits>
      <bits access="w" name="pageinq_abort" pos="25" rst="0">
        <comment>
          Abort the current Inquiry Mode or Page Mode when written with a 1. 
Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="w" name="sniff_abort" pos="24" rst="0">
        <comment>
          Abort the current Sniff Mode when written with a 1. 
Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="rw" name="flowdsb" pos="23" rst="0">
        <comment>
          0: FLOW verification on Rx packets is activated.  
1: Packets are accepted regardless of FLOW value (test mode). 
        </comment>
      </bits>
      <bits access="r" name="RWBTCNT_reserved_0" pos="22" rst="0">
      </bits>
      <bits access="rw" name="lmpflowdsb" pos="21" rst="0">
        <comment>
          0: When FLOW = 0, LMP messages can be sent.  
1: When FLOW = 0, LMP messages are not sent. 
        </comment>
      </bits>
      <bits access="rw" name="cryptdsb" pos="20" rst="0">
        <comment>
          0: Normal operation. Encryption enabled when required. 
1: Encryption disabled. 
Note this works for both E0 and AES-CCM encryption mechanism 
        </comment>
      </bits>
      <bits access="rw" name="whitdsb" pos="19" rst="0">
        <comment>
          0: Normal operation. Whitening enabled. 
1: Whitening disabled. 
        </comment>
      </bits>
      <bits access="rw" name="arqndsb" pos="18" rst="0">
        <comment>
          0: ARQN verification on Rx packets is activated.  
1: Packets are accepted regardless of ARQN value (test mode). 
        </comment>
      </bits>
      <bits access="rw" name="crcdsb" pos="17" rst="0">
        <comment>
          0: Normal operation. CRC removed from incoming data stream. 
1: CRC stripping disabled on Rx packets. 
        </comment>
      </bits>
      <bits access="rw" name="hopdsb" pos="16" rst="0">
        <comment>
          0: Normal operation. Hopping enabled. 
1: Hopping disabled, the frequency is set either by CS-FREQ or by RFTESTFREQ register fields. 
        </comment>
      </bits>
      <bits access="rw" name="seqndsb" pos="15" rst="0">
        <comment>
          0: SEQN verification on Rx packets is activated.  
1: Packets are accepted regardless of SEQN value (test mode). 
        </comment>
      </bits>
      <bits access="rw" name="cx_txbsyena" pos="14" rst="1">
        <comment>
          This    field    updates    the    CS-TXBSY_EN    field    in    the    control    structure    when    ends    a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. 
        </comment>
      </bits>
      <bits access="rw" name="cx_rxbsyena" pos="13" rst="1">
        <comment>
          This    field    updates    the    CS-RXBSY_EN    field    in    the    control    structure    when    ends    a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. 
        </comment>
      </bits>
      <bits access="rw" name="cx_dnabort" pos="12" rst="1">
        <comment>
          This    field    updates    the    CS-DNABORT    field    in    the    control    structure    when    ends    a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. 
        </comment>
      </bits>
      <bits access="r" name="RWBTCNT_reserved_1" pos="11:9" rst="0">
      </bits>
      <bits access="rw" name="rwbten" pos="8" rst="0">
        <comment>
          0: Disable RW-BT Core. 
1: Enable RW-BT Core. 
        </comment>
      </bits>
      <bits access="r" name="RWBTCNT_reserved_2" pos="7:4" rst="0">
      </bits>
      <bits access="rw" name="syncerr" pos="3:0" rst="0">
        <comment>
          Indicate the maximum number of errors allowed to recognize the Access Code. 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="VERSION">
      <bits access="r" name="typ" pos="31:24" rst="8">
        <comment>
          RW-BT Core Type - 0x8 means BT v4.2 (i.e. correspond LM version assigned  number). Correspond to FS v8.0.11
        </comment>
      </bits>
      <bits access="r" name="rel" pos="23:16" rst="0">
        <comment>
          Version of the RW-BT Core - Major release number. Correspond to FS v8.0.11.
        </comment>
      </bits>
      <bits access="r" name="upg" pos="15:8" rst="11">
        <comment>
          Version of the RW-BT Core - Upgrade number. Correspond to FS v8.0.11
        </comment>
      </bits>
      <bits access="r" name="build_num" pos="7:0" rst="0">
        <comment>
          RW-BT Core Build number 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="RWBTCONF">
      <bits access="r" name="dmmode" pos="31" rst="1">
        <comment>
          0: RW-BT Core is used as a standalone BR/EDR device  
1: RW-BT Core is used in a Dual Mode device  
        </comment>
      </bits>
      <bits access="r" name="RWBTCONF_reserved_0" pos="30:28" rst="0">
      </bits>
      <bits access="r" name="mwswci2" pos="27" rst="0">
        <comment>
          0: MWS Coexistence 2-Wire Interface not supported 
1: MWS Coexistence 2-Wire Interface supported 
        </comment>
      </bits>
      <bits access="r" name="mwswci1" pos="26" rst="0">
        <comment>
          0: MWS Coexistence 1-Wire Interface not supported 
1: MWS Coexistence 1-Wire Interface supported 
        </comment>
      </bits>
      <bits access="r" name="vxportnb" pos="25:24" rst="3">
        <comment>
          Number of supported Audio Channel (0 to 3) 
00: No Audio Channel / No PCM. 
01: One Audio Channel 
10: Two Audio Channels 
11: Three Audio Channels. 
        </comment>
      </bits>
      <bits access="r" name="pcm" pos="23" rst="1">
        <comment>
          0: PCM Not Instantiated 
1: PCM Instantiated 
        </comment>
      </bits>
      <bits access="r" name="mwscoex" pos="22" rst="0">
        <comment>
          0: MWS Coexistence mechanism not present 
1: MWS Coexistence mechanism present  
        </comment>
      </bits>
      <bits access="r" name="wlancoex" pos="21" rst="0">
        <comment>
          0: WLAN Coexistence mechanism not present 
1: WLAN Coexistence mechanism present  
        </comment>
      </bits>
      <bits access="r" name="rfif" pos="20:16" rst="1">
        <comment>
          RFIF[k]= 0: Control logic supporting radio k not present 
RFIF[k]= 1: Control logic supporting radio k present 
Index k values are: 
00001: RW-BT Ripple RF. 
00010: External Radio Controller Support 
xxxx00: Reserved 
        </comment>
      </bits>
      <bits access="r" name="usedbg" pos="15" rst="1">
        <comment>
          0: Diagnostics port not present 
1: Diagnostics port present 
        </comment>
      </bits>
      <bits access="r" name="usecrypt" pos="14" rst="1">
        <comment>
          0: AES-CCM Encryption block not present 
1: AES-CCM Encryption block present  
        </comment>
      </bits>
      <bits access="r" name="clk_sel" pos="13:8" rst="13">
        <comment>
          Operating Frequency (in MHz) 
Default is 13 MHz 
        </comment>
      </bits>
      <bits access="r" name="intmode" pos="7" rst="1">
        <comment>
          0: Interrupts are edge level generated, i.e. pulse. 
1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement  
        </comment>
      </bits>
      <bits access="r" name="bus_type" pos="6" rst="0">
        <comment>
          Processor Bus Type 
0: AHB Bus 
1: X-Bar Bus 
        </comment>
      </bits>
      <bits access="r" name="data_width" pos="5" rst="1">
        <comment>
          Processor Data bus width: 
0 16 bits 
1: 32 bits 
        </comment>
      </bits>
      <bits access="r" name="addr_width" pos="4:0" rst="16">
        <comment>
           Value of the RW_BT_ADDRESS_WIDTH parameter converted into binary. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="INTCNTL">
      <bits access="r" name="INTCNTL_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="sketintmsk" pos="17" rst="0">
        <comment>
          Skipped Exchange Table entry Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="swintmsk" pos="16" rst="0">
        <comment>
          SW triggered Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="frameapfaintmsk" pos="15" rst="0">
        <comment>
          End of Frame Interrupt / Anticipated Pre-Fetch Abort mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="frameintmsk" pos="14" rst="0">
        <comment>
          End of Frame Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="mwswcirxintmsk" pos="13" rst="0">
        <comment>
          MWS Serial Interface Rx Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="mwswcitxintmsk" pos="12" rst="0">
        <comment>
          MWS Serial Interface Tx Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="errorintmsk" pos="11" rst="0">
        <comment>
          Error Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="grosstgtintmsk" pos="10" rst="0">
        <comment>
          Gross Target Timer Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="finetgtintmsk" pos="9" rst="0">
        <comment>
          Fine Target Timer Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="mtoffint1msk" pos="8" rst="0">
        <comment>
          Momentary Offset 1 event Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="mtoffint0msk" pos="7" rst="0">
        <comment>
          Momentary Offset 0 event Interrupt mask  
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="frsyncintmsk" pos="6" rst="0">
        <comment>
          Frame Synchronization Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="audioint2msk" pos="5" rst="0">
        <comment>
          Audio Channel 2 Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="audioint1msk" pos="4" rst="0">
        <comment>
          Audio Channel 1 Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="audioint0msk" pos="3" rst="0">
        <comment>
          Audio Channel 0 Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="slpintmsk" pos="2" rst="1">
        <comment>
          End of Sleep Interrupt Mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="rxintmsk" pos="1" rst="1">
        <comment>
          Packet Receipt Interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
      <bits access="rw" name="clknintmsk" pos="0" rst="1">
        <comment>
          CLKN / Slot interrupt mask 
0: Interrupt not generated 
1: Interrupt generated 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="INTSTAT">
      <bits access="r" name="INTSTAT_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="r" name="sketintstat" pos="17" rst="0">
        <comment>
          Skipped Exchange Table entry Interrupt status 
0: No Skipped Exchange Table entry Interrupt 
1: Skipped Exchange Table entry Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="swintstat" pos="16" rst="0">
        <comment>
          SW Triggered Interrupt status 
0: No SW triggered Interrupt 
1: SW Triggered Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="frameapfaintstat" pos="15" rst="0">
        <comment>
          End of Frame / Anticipated Pre-Fetch Abort Interrupt status 
0: No End of Frame Interrupt 
1: End of Frame Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="frameintstat" pos="14" rst="0">
        <comment>
          End of Frame Interrupt status 
0: No End of Frame Interrupt 
1: End of Frame Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="mwswcirxintstat" pos="13" rst="0">
        <comment>
          MWS Serial Interface Rx Interrupt status 
0: No MWS WCI Interrupt 
1: MWS WCI Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="mwswcitxintstat" pos="12" rst="0">
        <comment>
          MWS Serial Interface Tx Interrupt status 
0: No MWS WCI Interrupt 
1: MWS WCI Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="errorintstat" pos="11" rst="0">
        <comment>
          Error Interrupt status. 
0: No Error interrupt. 
1: Error interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="grosstgtintstat" pos="10" rst="0">
        <comment>
          Gross Timer Interrupt status. 
0: No Gross Timer interrupt. 
1: Gross Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="finetgtintstat" pos="9" rst="0">
        <comment>
          Fine Timer Interrupt status. 
0: No Fine Timer interrupt. 
1: Fine Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="mtoffint1stat" pos="8" rst="0">
        <comment>
          Momentary Offset 1 Interrupt status. 
0: No Momentary Offset interrupt. 
1: Momentary offset interrupt is pending and the newly calculated momentary offset is lower than the correction step 
        </comment>
      </bits>
      <bits access="r" name="mtoffint0stat" pos="7" rst="0">
        <comment>
          Momentary Offset 0 Interrupt status. 
0: No Momentary Offset interrupt. 
1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step 
        </comment>
      </bits>
      <bits access="r" name="frsyncintstat" pos="6" rst="0">
        <comment>
          MWS Frame Synchronization Interrupt status. 
0: No frame_sync interrupt. 
1: A frame_sync interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint2stat" pos="5" rst="0">
        <comment>
          Audio Channel 2 Interrupt status. 
0: No eSCO SW Transport interrupt. 
1: An eSCO SW Transport interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint1stat" pos="4" rst="0">
        <comment>
          Audio Channel 1 Interrupt status. 
0: No eSCO SW Transport interrupt. 
1: An eSCO SW Transport interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint0stat" pos="3" rst="0">
        <comment>
          Audio Channel 0 Interrupt status. 
0: No eSCO SW Transport interrupt. 
1: An eSCO SW Transport interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="slpintstat" pos="2" rst="0">
        <comment>
          end of Sleep Interrupt Status. 
0: No End of Sleep Mode interrupt. 
1: An End of Sleep Mode interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="rxintstat" pos="1" rst="0">
        <comment>
          Packet Reception Interrupt status. 
0: No Rx interrupt. 
1: An Rx interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="clknintstat" pos="0" rst="0">
        <comment>
          Slot Interrupt status. 
0: No CLKN interrupt. 
1: A CLKN interrupt is pending. 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="INTRAWSTAT">
      <bits access="r" name="INTRAWSTAT_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="r" name="sketintrawstat" pos="17" rst="0">
        <comment>
          Skipped Exchange Table entry Interrupt raw status 
0: No Skipped Exchange Table entry Interrupt 
1: Skipped Exchange Table entry Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="swintrawstat" pos="16" rst="0">
        <comment>
          SW Triggered Interrupt raw status 
0: No SW Triggered Interrupt 
1: SW Triggered Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="frameapfaintrawstat" pos="15" rst="0">
        <comment>
          End of Frame / Anticipated Pre-Fetch Abort Interrupt raw status 
0: No End of Frame Interrupt 
1: End of Frame Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="frameintrawstat" pos="14" rst="0">
        <comment>
          End of Frame Interrupt raw status 
0: No End of Frame Interrupt 
1: End of Frame Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="mwswcirxintrawstat" pos="13" rst="0">
        <comment>
          MWS Serial Interface Rx Interrupt raw status 
0: No MWS WCI Interrupt 
1: MWS WCI Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="mwswcitxintrawstat" pos="12" rst="0">
        <comment>
          MWS Serial Interface Tx Interrupt raw status 
0: No MWS WCI Interrupt 
1: MWS WCI Interrupt is pending 
        </comment>
      </bits>
      <bits access="r" name="errorintrawstat" pos="11" rst="0">
        <comment>
          Error Interrupt raw status. 
0: No Error interrupt. 
1: Error interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="grosstgtintrawstat" pos="10" rst="0">
        <comment>
          Gross Timer Interrupt raw status. 
0: No Gross Timer interrupt. 
1: Gross Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="finetgtintrawstat" pos="9" rst="0">
        <comment>
          Fine Timer Interrupt raw status. 
0: No Fine Timer interrupt. 
1: Fine Timer interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="mtoffint1rawstat" pos="8" rst="0">
        <comment>
          Momentary Offset 1 Interrupt raw status. 
0: No Momentary Offset interrupt. 
1:  Momentary  offset  interrupt  is  pending  and  the  newly  calculated  momentary  offset  is  lower than the correction step 
        </comment>
      </bits>
      <bits access="r" name="mtoffint0rawstat" pos="7" rst="0">
        <comment>
          Momentary Offset 0 Interrupt raw status. 
0: No Momentary Offset interrupt. 
1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step 
        </comment>
      </bits>
      <bits access="r" name="frsyncintrawstat" pos="6" rst="0">
        <comment>
          MWS Frame Synchronization Interrupt raw status. 
0: No frame_sync interrupt. 
1: A frame_sync interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint2rawstat" pos="5" rst="0">
        <comment>
          Audio Channel 2 Interrupt raw status. 
0: No eSCO SW Transport interrupt. 
1: An eSCO SW Transport interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint1rawstat" pos="4" rst="0">
        <comment>
          Audio Channel 1 Interrupt raw status. 
0: No eSCO SW Transport interrupt. 
1: An eSCO SW Transport interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="audioint0rawstat" pos="3" rst="0">
        <comment>
          Audio Channel 0 Interrupt raw status. 
0: No eSCO SW Transport interrupt. 
1: An eSCO SW Transport interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="slpintrawstat" pos="2" rst="0">
        <comment>
          End of Sleep Interrupt raw Status. 
0: No End of Sleep Mode interrupt. 
1: An End of Sleep Mode interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="rxintrawstat" pos="1" rst="0">
        <comment>
          Packet Reception Interrupt raw status. 
0: No Rx interrupt. 
1: An Rx interrupt is pending. 
        </comment>
      </bits>
      <bits access="r" name="clknintrawstat" pos="0" rst="0">
        <comment>
          Slot Interrupt raw status. 
0: No CLKN interrupt. 
1: A CLKN interrupt is pending. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="INTACK">
      <bits access="r" name="INTACK_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="s" name="sketintack" pos="17" rst="0">
        <comment>
        bit type is changed from wos to s.

          Skipped Exchange Table entry Interrupt acknowledgment. 
Software  writing  1  acknowledges  the   Skipped  Exchange  Table  entry   interrupt.  This  bit  resets SKETINTSTAT and SKETINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="swintack" pos="16" rst="0">
        <comment>
        bit type is changed from wos to s.

          SW triggered Interrupt acknowledgment. 
Software   writing   1   acknowledges   the   SW   triggered   interrupt.   This   bit   resets   SWINTSTAT   and SWINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="frameapfaintack" pos="15" rst="0">
        <comment>
        bit type is changed from wos to s.

          End of Frame / Anticipated Pre-Fetch Abort Interrupt acknowledgment. 
Software writing 1 acknowledges the End of Frame interrupt. This bit resets FRAMEAPFAINTSTAT and FRAMEAPFAINTRWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="frameintack" pos="14" rst="0">
        <comment>
        bit type is changed from wos to s.

          End of Frame Interrupt acknowledgment. 
Software  writing  1  acknowledges  the  End  of  Frame  interrupt.  This  bit  resets  FRAMEINTSTAT  and FRAMEINTRWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="mwswcirxintack" pos="13" rst="0">
        <comment>
        bit type is changed from wos to s.

          MWS Serial Interface Rx Interrupt acknowledgment. 
Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="mwswcitxintack" pos="12" rst="0">
        <comment>
        bit type is changed from wos to s.

          MWS Serial Interface Tx Interrupt acknowledgment. 
Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="errorintack" pos="11" rst="0">
        <comment>
        bit type is changed from wos to s.

          Error Interrupt acknowledgment. 
Software   writing   1   acknowledges   the   Error   interrupt.   This   bit   resets   ERRORINTSTAT   and ERRORINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="grosstgtintack" pos="10" rst="0">
        <comment>
        bit type is changed from wos to s.

          Gross Timer Interrupt acknowledgment. 
Software  writing  1  acknowledges  the  Gross  Timer  interrupt.  This  bit  resets  GROSSTGTINTSTAT  and GROSSTGTINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="finetgtintack" pos="9" rst="0">
        <comment>
        bit type is changed from wos to s.

          Fine Timer Interrupt acknowledgment. 
Software  writing  1  acknowledges  the  Fine  Timer  interrupt.  This  bit  resets  FINETGTINTSTAT  and FINETGTINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="mtoffint1ack" pos="8" rst="0">
        <comment>
        bit type is changed from wos to s.

          Momentary Offset 1 Interrupt acknowledgment. 
Software    writing    1    acknowledges    the    Momentary    offset    event    interrupt.    This    bit    resets MTOFFINT1STAT and MTOFFINT1RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="mtoffint0ack" pos="7" rst="0">
        <comment>
        bit type is changed from wos to s.

          Momentary Offset 0 Interrupt acknowledgment. 
Software    writing    1    acknowledges    the    Momentary    offset    event    interrupt.    This    bit    resets MTOFFINT0STAT and MTOFFINT0RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="frsyncintack" pos="6" rst="0">
        <comment>
        bit type is changed from wos to s.

          MWS Frame Synchronization Interrupt acknowledgement. 
Software writing 1 acknowledges the  frame_sync event interrupt. This bit resets FRSYNCINTSTAT and FRSYNCINTRAWSTAT flag. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="audioint2ack" pos="5" rst="0">
        <comment>
        bit type is changed from wos to s.

          Audio Channel 2 Interrupt acknowledgement. 
Software  writing  1  acknowledges  the  Audio  Channel  2  interrupt.  This  bit  resets  AUDIOINT2STAT  and AUDIOINT2RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="audioint1ack" pos="4" rst="0">
        <comment>
        bit type is changed from wos to s.

          Audio Channel 1 Interrupt acknowledgement. 
Software  writing  1  acknowledges  the  Audio  Channel  1  interrupt.  This  bit  resets  AUDIOINT1STAT  and AUDIOINT1RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="audioint0ack" pos="3" rst="0">
        <comment>
        bit type is changed from wos to s.

          Audio Channel 0 Interrupt acknowledgement. 
Software  writing  1  acknowledges  the  Audio  Channel  0  interrupt.  This  bit  resets  AUDIOINT0STAT  and AUDIOINT0RAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="slpintack" pos="2" rst="0">
        <comment>
        bit type is changed from wos to s.

          End of Sleep Interrupt acknowledgement. 
Software  writing  1  acknowledges  the  End  of  Sleep  Mode  interrupt.  This  bit  resets  SLPINTSTAT  and SLPINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="rxintack" pos="1" rst="0">
        <comment>
        bit type is changed from wos to s.

          Packet Reception Interrupt acknowledgement. 
Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
      <bits access="s" name="clknintack" pos="0" rst="0">
        <comment>
        bit type is changed from wos to s.

          Slot Interrupt acknowledgement. 
Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. 
Resets at 0 when action is performed 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="SLOTCLK">
      <bits access="w" name="samp" pos="31" rst="0">
        <comment>
          Writing a 1 samples the CLKN[27:0] value in SLOTCLK-SCLK register field.  
Resets at 0 when action is performed. No action happens if it is written with 0 
        </comment>
      </bits>
      <bits access="w" name="clkn_upd" pos="30" rst="0">
        <comment>
          Update the Native Bluetooth counter CLKN[27:1] (CLKN[0] is not considered), when written with a 1. 
Resets at 0 when action is performed. No action happens if it is written with 0.  
        </comment>
      </bits>
      <bits access="r" name="SLOTCLK_reserved_0" pos="29:28" rst="0">
      </bits>
      <bits access="rw" name="sclk" pos="27:0" rst="0">
        <comment>
          Native Bluetooth counter CLKN sampled at the time the processor has written the SAMP bit (precsision of 312.5us).  This  value  does  not  change  until  the  next  writing  of  SAMP  bit,  and  can  therefore  be  safely accessed with 8-, 16- or 32-bits accesses. 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="FINETIMECNT">
      <bits access="r" name="FINETIMECNT_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="r" name="finecnt" pos="9:0" rst="0">
        <comment>
          Value of the current us fine time reference counter sampled at the time the processor has written the SAMP bit. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ABTRAINCNT">
      <bits access="rw" name="abtpageen" pos="31" rst="0">
        <comment>
          Enable automatic A-train/B-train switch during Page procedure. 
0: Page procedure A-train/B-train counter disabled
1: Page procedure A-train/B-train counter enabled
        </comment>
      </bits>
      <bits access="rw" name="abtpagestartvalue" pos="30" rst="0">
        <comment>
          Starting train value of Page procedure
0:Start with A-train
1:Start with B-train
        </comment>
      </bits>
      <bits access="r" name="ABTRAINCNT_reserved_0" pos="29" rst="0">
      </bits>
      <bits access="w" name="abtpageload" pos="28" rst="0">
        <comment>
          Load A-train/B-train Page procedure conter, when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.
        </comment>
      </bits>
      <bits access="r" name="ABTRAINCNT_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="abtpagetime" pos="26:16" rst="256">
        <comment>
          Defines A-train/B-train duration time during Page procedure, counted by 16-slots.
Loaded when ABTPAGELOAD is set. Start when Page procedure starts and ABTPAGEEN is set. Stops when  ABTPAGEEN is reset. Switch of train when wrapping.
        </comment>
      </bits>
      <bits access="rw" name="abtinqen" pos="15" rst="0">
        <comment>
          Enable automatic A-train/B-train switch during Inquiry procedure. 
0: Inquiry procedure A-train/B-train counter disabled
1: Inquiry procedure A-train/B-train counter enabled
        </comment>
      </bits>
      <bits access="rw" name="abtinqstartvalue" pos="14" rst="0">
        <comment>
          Starting train value of Inquiry procedure
0:Start with A-train
1:Start with B-train
        </comment>
      </bits>
      <bits access="r" name="ABTRAINCNT_reserved_2" pos="13" rst="0">
      </bits>
      <bits access="w" name="abtinqload" pos="12" rst="0">
        <comment>
          Load A-train/B-train Inquiry procedure conter, when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.
        </comment>
      </bits>
      <bits access="r" name="ABTRAINCNT_reserved_3" pos="11" rst="0">
      </bits>
      <bits access="rw" name="abtinqtime" pos="10:0" rst="256">
        <comment>
          Defines A-train/B-train duration time during Inquiry procedure, counted by 16-slots.
Loaded when ABTINQLOAD is set. Start when Inquiry procedure starts and ABTINQEN is set. Stops when  ABTINQEN is reset. Switch of train when wrapping.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="EDRCNTL_NWINSIZE">
      <bits access="r" name="EDRCNTL_NWINSIZE_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="nwinsize" pos="29:24" rst="26">
        <comment>
          Default value equals d'26 
Applies when ET-SNIFF = 1 on first access code detection, in order to process the new bit offset (See section 3.5.5) 
        </comment>
      </bits>
      <bits access="r" name="EDRCNTL_NWINSIZE_reserved_1" pos="23:17" rst="0">
      </bits>
      <bits access="rw" name="edrbcast" pos="16" rst="0">
        <comment>
          0: Broadcast @ 1Mbps / normal mode 
1: Broadcast operation in EDR Mode (@ 2/3 Mbps) / special features 
The EDRCNTL-EDRBCAST bit is used in reception (slave side) as following: 
if RXLTADDR= 0 (i.e. broadcast packet is received) 
    if  EDRCNTL-EDRBCAST=0  ,  we consider  the  currently  received packet  is  not  an  EDR-packet. The 1Mbps modulation is used. 
    if EDRCNTL-EDRBCAST=1, then apply EDR modulation or not depending on the control structure bit " ACLEDR" set in MISCNTL field.  
        </comment>
      </bits>
      <bits access="rw" name="rxguarddsb" pos="15" rst="0">
        <comment>
          0: normal operation, EDR Rx guard window detection activated 
1: EDR Rx guard window detection disabled. 
        </comment>
      </bits>
      <bits access="rw" name="tx_swap" pos="14" rst="0">
        <comment>
          0: Direct order EDR Payload data transmit 
1: Reverse order EDR Payload data transmit 
        </comment>
      </bits>
      <bits access="rw" name="rx_swap" pos="13" rst="0">
        <comment>
          0: Direct order EDR Payload data receive 
1: Reverse order EDR Payload data receive 
        </comment>
      </bits>
      <bits access="r" name="EDRCNTL_NWINSIZE_reserved_2" pos="12:9" rst="0">
      </bits>
      <bits access="rw" name="rxgrd_timeout" pos="8:0" rst="212">
        <comment>
          Time out value before EDR packet reception that allow ending the Rx transaction if an EDR packet is not correctly detected. 
Default value is set to 212 clock cycles @ 13MHz &lt;-&gt; 16.3us. Timing between Packet Header and EDR packet is defined as 5us+-0.25us + 11 synchronization symbol = 16.25us in the worst case 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ET_CURRENTRXDESCPTR">
      <bits access="rw" name="etptr" pos="31:16" rst="0">
        <comment>
          Exchange Table pointer value 
        </comment>
      </bits>
      <bits access="r" name="ET_CURRENTRXDESCPTR_reserved_0" pos="15" rst="0">
      </bits>
      <bits access="rw" name="currentrxdescptr" pos="14:0" rst="0">
        <comment>
          Rx Descriptor current pointer value 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DEEPSLCNTL">
      <bits access="rw" name="extwkupdsb" pos="31" rst="0">
        <comment>
          External Wake-Up disable  
0: RW-BT Core can be woken by external wake-up  
1: RW-BT Core cannot be woken up by external wake-up 
        </comment>
      </bits>
      <bits access="r" name="DEEPSLCNTL_reserved_0" pos="30:16" rst="0">
      </bits>
      <bits access="r" name="deep_sleep_stat" pos="15" rst="0">
        <comment>
          Indicator of current Deep Sleep clock mux status: 
0: RW-BT Core is not yet in Deep Sleep Mode 
1: RW-BT Core is in Deep Sleep Mode (only low_power_clk is running) 
        </comment>
      </bits>
      <bits access="r" name="DEEPSLCNTL_reserved_1" pos="14:5" rst="0">
      </bits>
      <bits access="w" name="soft_wakeup_req" pos="4" rst="0">
        <comment>
          Wake Up Request from RW-BT Software. Applies when system is in Deep Sleep Mode. It wakes up the RW-BT Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="w" name="deep_sleep_corr_en" pos="3" rst="0">
        <comment>
          CLKN  integer  and  fractional  part  correction  (i.e.  CLKN  Counter  and  Fine  Counter).  Applies  when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="w" name="deep_sleep_on" pos="2" rst="0">
        <comment>
          RW-BT Core sleep mode request control 
0: RW-BT Core in normal active mode 
1: Request RW-BT Core to switch in deep sleep mode. 
This bit is reset on DEEP_SLEEP_STAT falling edge. 
        </comment>
      </bits>
      <bits access="rw" name="radio_sleep_en" pos="1" rst="0">
        <comment>
          Controls the Radio module 
0: Radio stands in normal active mode 
1: Allow to disable Radio 
        </comment>
      </bits>
      <bits access="rw" name="osc_sleep_en" pos="0" rst="0">
        <comment>
          Controls the RF High frequency crystal oscillator 
0: High frequency crystal oscillator stands in normal active mode 
1: Allow to disable High frequency crystal oscillator 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DEEPSLWKUP">
      <bits access="rw" name="deepsltime" pos="31:0" rst="0">
        <comment>
          Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="DEEPSLSTAT">
      <bits access="r" name="deepsldur" pos="31:0" rst="0">
        <comment>
          Actual duration of the last deep sleep phase measured in low power oscillator cycles. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low power clock tick until the end of the deep sleep phase. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ENBPRESET">
      <bits access="rw" name="twext" pos="31:21" rst="160">
        <comment>
          Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator following an external wake-up request (signal wakeup_req) [0...64ms for 32kHz) 
        </comment>
      </bits>
      <bits access="rw" name="twosc" pos="20:10" rst="160">
        <comment>
          Time  in  low  power  oscillator  cycles  allowed  for  stabilization  of  the  high  frequency  oscillator  when  the deep-sleep mode has been left due to sleep-timer expiry (DEEPSLWKUP) [0...64ms for 32kHz) 
        </comment>
      </bits>
      <bits access="rw" name="twrm" pos="9:0" rst="32">
        <comment>
          Time in low power oscillator cycles allowed for the radio module to leave low-power mode  [0...32ms for 32kHz) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="FINECNTCORR">
      <bits access="r" name="FINECNTCORR_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="rw" name="finecntcorr" pos="9:0" rst="0">
        <comment>
          Phase correction value for the CLKN counter in us.  
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="CLKNCNTCORR">
      <bits access="rw" name="abs_delta" pos="31" rst="0">
        <comment>
          Determines whether CLNCNTCORR is an absolute correction or a signed "delta" increment correction 
0: Absolute correction 
1: Signed "delta" increment correction 
        </comment>
      </bits>
      <bits access="r" name="CLKNCNTCORR_reserved_0" pos="30:28" rst="0">
      </bits>
      <bits access="rw" name="clkncntcorr" pos="27:0" rst="0">
        <comment>
          CLKN Counter correction value / signed "delta" increment 
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="DIAGCNTL">
      <bits access="rw" name="diag3_en" pos="31" rst="0">
        <comment>
          0: Disable diagnostic port 3 output. All outputs are set to 0. 
1: Enable diagnostic port 3 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_0" pos="30" rst="0">
      </bits>
      <bits access="rw" name="diag3" pos="29:24" rst="0">
        <comment>
          Only relevant when DIAGEN3 = 1. 
Selection of the outputs that are driven to the diagnostic port 3.  
        </comment>
      </bits>
      <bits access="rw" name="diag2_en" pos="23" rst="0">
        <comment>
          0: Disable diagnostic port 2 output. All outputs are set to 0. 
1: Enable diagnostic port 2 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_1" pos="22" rst="0">
      </bits>
      <bits access="rw" name="diag2" pos="21:16" rst="0">
        <comment>
          Only relevant when DIAGEN2 = 1. 
Selection of the outputs that are driven to the diagnostic port 2.  
        </comment>
      </bits>
      <bits access="rw" name="diag1_en" pos="15" rst="0">
        <comment>
          0: Disable diagnostic port 1 output. All outputs are set to 0. 
1: Enable diagnostic port 1 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_2" pos="14" rst="0">
      </bits>
      <bits access="rw" name="diag1" pos="13:8" rst="0">
        <comment>
          Only relevant when DIAGEN1 = 1. 
Selection of the outputs that are driven to the diagnostic port 1.  
        </comment>
      </bits>
      <bits access="rw" name="diag0_en" pos="7" rst="0">
        <comment>
          0: Disable diagnostic port 0 output. All outputs are set to 0. 
1: Enable diagnostic port 0 output. 
        </comment>
      </bits>
      <bits access="r" name="DIAGCNTL_reserved_3" pos="6" rst="0">
      </bits>
      <bits access="rw" name="diag0" pos="5:0" rst="0">
        <comment>
          Only relevant when DIAGEN0 = 1. 
Selection of the outputs that are driven to the diagnostic port 0.  
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="DIAGSTAT">
      <bits access="r" name="diag3stat" pos="31:24" rst="0">
        <comment>
          Directly connected to bt_dbg0[7:0] output. Debug use only 
        </comment>
      </bits>
      <bits access="r" name="diag2stat" pos="23:16" rst="0">
        <comment>
          Directly connected to bt_dbg1[7:0] output. Debug use only 
        </comment>
      </bits>
      <bits access="r" name="diag1stat" pos="15:8" rst="0">
        <comment>
          Directly connected to bt_dbg2[7:0] output. Debug use only 
        </comment>
      </bits>
      <bits access="r" name="diag0stat" pos="7:0" rst="0">
        <comment>
          Directly connected to bt_dbg3[7:0] output. Debug use only 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DEBUGADDMAX">
      <bits access="rw" name="reg_addmax" pos="31:16" rst="0">
        <comment>
          Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.19). 
        </comment>
      </bits>
      <bits access="rw" name="em_addmax" pos="15:0" rst="0">
        <comment>
          Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19). 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DEBUGADDMIN">
      <bits access="rw" name="reg_addmin" pos="31:16" rst="0">
        <comment>
          Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.19) 
        </comment>
      </bits>
      <bits access="rw" name="em_addmin" pos="15:0" rst="0">
        <comment>
          Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19) 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="ERRORTYPESTAT">
      <bits access="r" name="ERRORTYPESTAT_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="r" name="rxbuf_ptr_error" pos="21" rst="0">
        <comment>
          Indicates  whether  the  Rx  eSCO  (during  Voice  over  HCI  operations)  or  Rx  LM  buffer  pointer value programmed is null: this is a major programming failure. 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="txbuf_ptr_error" pos="20" rst="0">
        <comment>
          Indicates  whether  Tx  eSCO  (during  Voice  over  HCI  operations)  or  Tx  LM  buffer  pointer  value programmed  is  null,  or  if  an  ACL  Tx  packet  is  set  with  a  non  null  length  while  no  buffer  is associated: this is a major programming failure. 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="rxdesc_empty_error" pos="19" rst="0">
        <comment>
          Indicates  whether  Rx  Descriptor  pointer  value  programmed  in  register  is  null:  this  is  a  major programming failure / Valid for non-connected states and Broadcast Scan mode 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="txdesc_empty_error" pos="18" rst="0">
        <comment>
          Indicates whether Tx Descriptor pointer value programmed in Control Structure is null: this is a major programming failure / Valid for non-connected states and Broadcast mode 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="csattnb_error" pos="17" rst="0">
        <comment>
          Indicates  whether  ATT_NB  field  in  Control  Structure  is  null,  or  when  during  eSCO  that eSCOLTCNLT&lt;0/1/2&gt;-RETXNB&lt;0/1/2&gt; register field is null: this is a major programming failure 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="csformat_error" pos="16" rst="0">
        <comment>
          Indicates  whether  CS-FORMAT  has  been  programmed  with  an  invalid  value:  this  is  a  major software programming failure.  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="chmap_error" pos="15" rst="0">
        <comment>
          Channel Map error, happens when actual number of bits set to one in selected CS-CHMAP is different from corresponding CS-NBCHGOOD at the beginning of Frequency Hopping process. 
Note this is valid only if CS-AFHENA=1 
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="hopunderrun_error" pos="14" rst="0">
        <comment>
          Calculation of the hopping frequency not done before Tx/Rx EN is asserted 
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="frm_cntl_timer_error" pos="13" rst="0">
        <comment>
          Indicates an Frame Controller internal timing error 
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="frm_cntl_emacc_error" pos="12" rst="0">
        <comment>
          Indicate a Frame Controller Exchange Memory Access error. 
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="frm_cntl_apfm_error" pos="11" rst="0">
        <comment>
          Indicates  Anticipated  Pre-Fetch  Mechanism  error  in  Frame  Controller:  happens  when  2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached. 
0: No error 
1: Error occured 
        </comment>
      </bits>
      <bits access="r" name="frm_schdl_apfm_error" pos="10" rst="0">
        <comment>
          Indicates  Anticipated  Pre-Fetch  Mechanism  error  in  Frame  Scheduler:  happens  when  2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached. 
0: No error 
1: Error occured 
        </comment>
      </bits>
      <bits access="r" name="frm_schdl_entry_error" pos="9" rst="0">
        <comment>
          Indicates Frame Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624us offset and second one with no offset) 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="mwswci_emacc_error" pos="8" rst="0">
        <comment>
          MWS  WCI  Exchange  Memory  access  error,  happens  when  Exchange  Memory  access  are  not served in time and Audio samples are corrupted  
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="frm_schdl_emacc_error" pos="7" rst="0">
        <comment>
          Frame Scheduler Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted  
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="pcm_emacc_error" pos="6" rst="0">
        <comment>
          PCM  Exchange  Memory  request  access  error,  happens  when  Exchange  Memory  access requests are not served in time and PCM samples are corrupted  
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="audio_emacc_error" pos="5" rst="0">
        <comment>
          Audio EM Access Manager Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted  
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="radiocntl_emacc_error" pos="4" rst="0">
        <comment>
          Radio Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and data are corrupted.  
0: No error  
1: Error occurred  
        </comment>
      </bits>
      <bits access="r" name="pktcntl_emacc_error" pos="3" rst="0">
        <comment>
          Packet Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and Tx/Rx data are corrupted  
0: No error  
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="cryptmode_error" pos="2" rst="0">
        <comment>
          Indicates when the Encryption  mode is enabled with Connectionless Slave Broadcast (Master or Slave) 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="rxcrypt_error" pos="1" rst="0">
        <comment>
          Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to  Packet  Controller  requests.  A  16-bytes  block  has  to  be  decrypted  prior  the  next  block  is received by the Packet Controller 
0: No error 
1: Error occurred 
        </comment>
      </bits>
      <bits access="r" name="txcrypt_error" pos="0" rst="0">
        <comment>
          Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti 
0: No error 
1: Error occurred 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="SWPROFILING">
      <bits access="rw" name="swprof" pos="31:0" rst="0">
        <comment>
          Software Profiling register: used by RW-BT Software for profiling purpose: this value is copied on Diagnostic port  
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="RADIOCNTL0">
      <bits access="r" name="RADIOCNTL0_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="sync_pulse_mode" pos="23" rst="0">
        <comment>
          Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet.
0: Access Code detection indicator provided as pulse
1: Access Code detection indicator provided as level
        </comment>
      </bits>
      <bits access="rw" name="dpcorr_en" pos="22" rst="0">
        <comment>
          Enables the use of the delayed DC offset compensated data path in Radio Correlator block.
1: Enable
0: Disable
        </comment>
      </bits>
      <bits access="rw" name="forceagc_en" pos="21" rst="0">
        <comment>
          Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value
1: Enable
0: Disable
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL0_reserved_1" pos="20:7" rst="0">
      </bits>
      <bits access="rw" name="spifreq" pos="6:5" rst="0">
        <comment>
          Frequency of the SPI clock
00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz)
01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz)
10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz)
11: Do not use
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL0_reserved_2" pos="4:2" rst="0">
      </bits>
      <bits access="r" name="spicomp" pos="1" rst="1">
        <comment>
          This bit is READ ONLY.
0: Indicates that the SPI transfer is in progress.
1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer.
        </comment>
      </bits>
      <bits access="w" name="spigo" pos="0" rst="0">
        <comment>
          Software writing 1 triggers the SPI access. This bit is always read as 0.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOCNTL1">
      <bits access="r" name="RADIOCNTL1_reserved_0" pos="31:21" rst="0">
      </bits>
      <bits access="rw" name="xrfsel" pos="20:16" rst="0">
        <comment>
          Extended radio selection field
5'h00000: No radio selected
5'h00001: RivieraWaves Ripple RF (BT4.0)
5'h00010: External Radio controller support
5'h00011-5'b11111: reserved
        </comment>
      </bits>
      <bits access="rw" name="spiptr" pos="15:0" rst="0">
        <comment>
          Pointer to the buffer containing data to be transferred to or received from the SPI port.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOCNTL2">
      <bits access="rw" name="tx_delay" pos="31:24" rst="0">
        <comment>
          Used to compensate Modem&amp;RF Tx delay. When used, rtrip_delay should be set as Rx delay
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL2_reserved_0" pos="23" rst="0">
      </bits>
      <bits access="rw" name="sync_position" pos="22:16" rst="16">
        <comment>
          Defines sync_p instant when provided to the Modem.
        </comment>
      </bits>
      <bits access="r" name="RADIOCNTL2_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="forceagc_length" pos="11:0" rst="0">
        <comment>
          Defines Rx window time threshold that forces Ripple AGC to max gain
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOCNTL3">
      <bits access="r" name="RADIOCNTL3_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="freqtable_ptr" pos="15:0" rst="64">
        <comment>
          BR/EDR Frequency Table pointer
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RADIOPWRUPDN">
      <bits access="r" name="RADIOPWRUPDN_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="rtrip_delay" pos="30:24" rst="0">
        <comment>
          Round Trip Delay. This correspond to the cumulated Tx plus Rx latency of the radio (in us) 
        </comment>
      </bits>
      <bits access="rw" name="rxpwrupct" pos="23:16" rst="210">
        <comment>
          This register holds the  length in us of the RX power  up  phase for the current radio device. Default value is 210 us (reset value). Operating range depends on supported radio. 
        </comment>
      </bits>
      <bits access="r" name="RADIOPWRUPDN_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="txpwrdnct" pos="12:8" rst="3">
        <comment>
          This  register  extends  the  length  in us of the  TX  power  down  phase  for  the  current  radio  device. 
Default value is 3us (reset value). Operating range depends on supported radio. 
        </comment>
      </bits>
      <bits access="rw" name="txpwrupct" pos="7:0" rst="210">
        <comment>
          This  register  holds  the  length  in us of  the  TX  power  up  phase  for  the  current  radio  device.  Default value is 210 us (reset value). Operating range is depends on supported radio. 
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="r" name="TXMICVAL">
      <bits access="r" name="txmicval" pos="31:0" rst="0">
        <comment>
          AES-CCM plain MIC value.  
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="RXMICVAL">
      <bits access="r" name="rxmicval" pos="31:0" rst="0">
        <comment>
          AES-CCM plain MIC value.  
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="E0PTR">
      <bits access="r" name="E0PTR_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="e0ptr" pos="15:0" rst="0">
        <comment>
          E0 Address pointer 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="RFTESTCNTL">
      <bits access="r" name="RFTESTCNTL_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="sserrren" pos="17" rst="0">
        <comment>
          Applicable in Slave eSCO reserved slot only
0: Normal mode of operation
1: Allow reply on Sync Error
        </comment>
      </bits>
      <bits access="rw" name="herrren" pos="16" rst="0">
        <comment>
          Applicable in Slave eSCO reserved slot only
0: Normal mode of operation
1: Allow reply on HEC Error
        </comment>
      </bits>
      <bits access="r" name="RFTESTCNTL_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="rw" name="infiniterx" pos="7" rst="0">
        <comment>
          Applicable for all frame format 
0: Normal mode of operation 
1: Infinite Rx window 
        </comment>
      </bits>
      <bits access="r" name="RFTESTCNTL_reserved_2" pos="6:3" rst="0">
      </bits>
      <bits access="rw" name="infinitetx" pos="2" rst="0">
        <comment>
          Applicable for all frame format 
0: Normal mode of operation 
1: Infinite Tx window 
        </comment>
      </bits>
      <bits access="rw" name="prbstype" pos="1" rst="0">
        <comment>
          Defines the PRBS type in use 
0: Tx Packet Payload are PRBS9 type 
1: Tx Packet Payload are PRBS15 type 
        </comment>
      </bits>
      <bits access="rw" name="txpldsrc" pos="0" rst="0">
        <comment>
          Applicable for all frame format  
0: Tx Packet Payload source is the Control Structure 
1: Tx Packet Payload are PRBS generator 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="RFTESTFREQ">
      <bits access="r" name="RFTESTFREQ_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="directlopbacken" pos="17" rst="0">
        <comment>
          Direct Loopback Test Mode enable control
0: Normal mode of operation
1: Direct Loopback Mode enabled (Received Packet Header, Payload Header, and Payload data directly re-transmitted in the next slot)
        </comment>
      </bits>
      <bits access="rw" name="testmodeen" pos="16" rst="0">
        <comment>
          Test Mode enable control, applicable if CS-FH_EN=0 
0: Normal mode of operation 
1: Test Mode enable, use &lt;TX/RX&gt;FREQ during Tx/Rx operations. 
        </comment>
      </bits>
      <bits access="r" name="RFTESTFREQ_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="rxfreq" pos="14:8" rst="0">
        <comment>
          Frequency Table index to be used during Rx operation 
        </comment>
      </bits>
      <bits access="r" name="RFTESTFREQ_reserved_2" pos="7" rst="0">
      </bits>
      <bits access="rw" name="txfreq" pos="6:0" rst="0">
        <comment>
          Frequency Table index to be used during Tx operation 
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="TIMGENCNTL">
      <bits access="rw" name="apfm_en" pos="31" rst="1">
        <comment>
          Controls the Anticipated pre-Fetch Abort mechanism 
0: Disabled 
1: Enabled 
        </comment>
      </bits>
      <bits access="r" name="TIMGENCNTL_reserved_0" pos="30:26" rst="0">
      </bits>
      <bits access="rw" name="prefetchabort_time" pos="25:16" rst="479">
        <comment>
          Defines the instant in us at which immediate abort is required after anticipated pre-fetch abort 
        </comment>
      </bits>
      <bits access="r" name="TIMGENCNTL_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rw" name="prefetch_time" pos="8:0" rst="189">
        <comment>
          Defines Exchange Table pre-fetch instant in us 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GROSSTIMTGT">
      <bits access="r" name="GROSSTIMTGT_reserved_0" pos="31:23" rst="0">
      </bits>
      <bits access="rw" name="grosstarget" pos="22:0" rst="0">
        <comment>
          Gross Timer Target value on which an Interrupt must be generated. 
This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET = CLKN[27:5] and CLKN[4:0] = 0. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="FINETIMTGT">
      <bits access="r" name="FINETIMTGT_reserved_0" pos="31:27" rst="0">
      </bits>
      <bits access="rw" name="finetarget" pos="26:0" rst="0">
        <comment>
          Fine Timer Target value on which an interrupt must be generated. 
This timer has a precision of 625us: interrupt is generated only when FINETARGET = CLKN[27:1] 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="SKETCLKN">
      <bits access="r" name="SKETCLKN_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="r" name="sketclkn" pos="27:0" rst="0">
        <comment>
          Returns the CLKN[27:0] value on each bt_sket_irq generation. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCACNTL0">
      <bits access="r" name="PCACNTL0_reserved_0" pos="31:27" rst="0">
      </bits>
      <bits access="rw" name="target_offset" pos="26:16" rst="0">
        <comment>
          Signed  number,  time  offset  to  the  current  frame_sync  position  in  us.  Valid  range  is  [-625, 625]us. When SYNC_SOURCE="1", the following formula must apply: 
TARGET_OFFSET = 559 - RF round trip delay - desired CS-BITOFF  
        </comment>
      </bits>
      <bits access="r" name="PCACNTL0_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="slvlbl" pos="12:8" rst="0">
        <comment>
          Applies only when SYNC_SOURCE equals 1. Defines which connection to align piconet clock on. 
The  connection  is  labelled  using  CS-LINKLBL  the  piconet  clock  is  aligned  when  CS-LINKLBL  = SLVLBL field 
Note  the  RW-BT  Software  must  ensure  the  labelled  connection  is  a  slave  connection,  else  it cannot work properly 
        </comment>
      </bits>
      <bits access="rw" name="corr_step" pos="7:4" rst="1">
        <comment>
          Maximum shift size during incremental phase shift. Must be programmed to 1us (0x1) 
Note  CORR_STEP  is  considered  as  a  signed  value  when  BLINDCORR_EN  is  set  (allows  to  drift forward and backward) 
        </comment>
      </bits>
      <bits access="rw" name="blindcorr_en" pos="3" rst="0">
        <comment>
          0: Align piconet clock on frame_sync rising edge (when CORR_INTERVAL is reached) 
1: Align piconet clock when CORR_INTERVAL is reached, without frame_sync rising edge 
        </comment>
      </bits>
      <bits access="rw" name="frsync_pol" pos="2" rst="0">
        <comment>
          Frame sync signal polarity.  
  0 : rising edge events sensitive 
  1 : falling edge events sensitive 
        </comment>
      </bits>
      <bits access="rw" name="sync_source" pos="1" rst="0">
        <comment>
          Defines synchronization signal source 
0: MWS frame synchronization 
1: Scatternet network scheduling optimization (See section 2.17) 
        </comment>
      </bits>
      <bits access="rw" name="phase_shift_en" pos="0" rst="0">
        <comment>
          Enable incremental phase shift 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCACNTL1">
      <bits access="r" name="PCACNTL1_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="corr_interval" pos="23:16" rst="40">
        <comment>
          Correction interval time in slot interval. 
Default value is 40 (i.e. 40x625us = 25ms) 
        </comment>
      </bits>
      <bits access="r" name="PCACNTL1_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="w" name="clock_shift_en" pos="12" rst="0">
        <comment>
          Performs immediate clock shift update using CLOCK_SHIFT[10:0], when written with a 1. 
Resets at 0 when action is performed. No action happens if it is written with 0. 
        </comment>
      </bits>
      <bits access="r" name="PCACNTL1_reserved_2" pos="11" rst="0">
      </bits>
      <bits access="rw" name="clock_shift" pos="10:0" rst="0">
        <comment>
          Signed value of the clock shift to apply when CLOCK_SHIFT_EN is written with a 1 in [-625, 625]us range 
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="PCASTAT">
      <bits access="r" name="PCASTAT_reserved_0" pos="31:27" rst="0">
      </bits>
      <bits access="r" name="shift_phase" pos="26:16" rst="0">
        <comment>
          Indicate  the  value  of  the  phase  when  an  immediate  shift  has  been  programmed  or  when  a frame_sync event occurs, [-625, 625]us 
        </comment>
      </bits>
      <bits access="r" name="PCASTAT_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="r" name="moment_offset" pos="10:0" rst="0">
        <comment>
          Momentary  offset,  signed  number  which  indicate  the  time  between  target_offset  and  the nearest alignment point, in [-625, 625]us range 
        </comment>
      </bits>
    </reg>
    <hole size="928"/>
    <reg protect="rw" name="eSCOCHANCNTL0">
      <bits access="r" name="tog0" pos="31" rst="0">
        <comment>
          Toggle command for Voice Channel 0. 
Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor 
Please refer to section 2.18.5 for details. 
        </comment>
      </bits>
      <bits access="r" name="eSCOCHANCNTL0_reserved_0" pos="30:16" rst="0">
      </bits>
      <bits access="rw" name="escochanswen0" pos="15" rst="0">
        <comment>
          Enables  eSCO  Channel  0  SW  Transport  (Enable  Audio  data  to  be  routed  directly  to  EM  (or  through AES-CCM if encrypted link), used by Voice Transparent Modes: 
0: Disabled. 
1: Enabled. 
        </comment>
      </bits>
      <bits access="rw" name="escochanen0" pos="14" rst="0">
        <comment>
          Enables eSCO Channel 0 (controls Audio Path EM Access controller voice channel 0): 
0: Disabled. 
1: Enabled. 
        </comment>
      </bits>
      <bits access="rw" name="itmode0" pos="13" rst="0">
        <comment>
          0: bt_audio0_irq is generated on TeSCO/TSCO instant 
1: bt_audio0_irq is generated INTDELAY0[5:0] slots after TeSCO/TSCO instant 
        </comment>
      </bits>
      <bits access="rw" name="intdelay0" pos="12:8" rst="0">
        <comment>
          Valid if ITMODE0 = 1 
Determines the slot number to wait before generating bt_audio0_irq 
        </comment>
      </bits>
      <bits access="rw" name="tesco0" pos="7:0" rst="0">
        <comment>
          eSCO interval (in slots). 
Support  a  [2:16]  range  in  slots  so  as  to  support  both  SCO  and  eSCO  mandatory  LMP  parameters range (see [1]) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOMUTECNTL0">
      <bits access="r" name="eSCOMUTECNTL0_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="mute_sink0" pos="23" rst="0">
        <comment>
          HW mute control: 
0: Do not mute on bad reception of an (e)SCO packet. 
1: Mute after data or bad reception, with the pattern stored in MUTEPATT0 
Note: See Table 2-34 for mute pattern value to apply 
        </comment>
      </bits>
      <bits access="rw" name="mute_source0" pos="22" rst="0">
        <comment>
          HW mute control: 
0: Provides Source buffer to the Packet Controller for Tx operations 
1: Forces POLL/NULL to be sent as a replacement of Audio Packets 
        </comment>
      </bits>
      <bits access="r" name="eSCOMUTECNTL0_reserved_1" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="invl0_1" pos="19:18" rst="2">
        <comment>
          SW mute status for Audio buffer 1 (i.e updated when TOG0=1): 
Mute if not null. Please refer to Table 2-35 for details
        </comment>
      </bits>
      <bits access="rw" name="invl0_0" pos="17:16" rst="2">
        <comment>
          SW mute status for Audio buffer 0 (i.e updated when TOG0=0): 
Mute if not null. Please refer to Table 2-35 for details
        </comment>
      </bits>
      <bits access="rw" name="mutepatt0" pos="15:0" rst="0">
        <comment>
          Value of the null pattern used when HW muting is enabled. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOCURRENTTXPTR0">
      <bits access="rw" name="esco0ptrtx1" pos="31:16" rst="0">
        <comment>
          Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 0. 
Used when eSCOCHANCNTL0-TOG0 = 1 
        </comment>
      </bits>
      <bits access="rw" name="esco0ptrtx0" pos="15:0" rst="0">
        <comment>
          Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 0.  
Used when eSCOCHANCNTL0-TOG0 = 0 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOCURRENTRXPTR0">
      <bits access="rw" name="esco0ptrrx1" pos="31:16" rst="0">
        <comment>
          Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 0. 
Used when eSCOCHANCNTL0-TOG0 = 1 
        </comment>
      </bits>
      <bits access="rw" name="esco0ptrrx0" pos="15:0" rst="0">
        <comment>
          Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 0. 
Used when eSCOCHANCNTL0-TOG0 = 0 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOLTCNTL0">
      <bits access="r" name="eSCOLTCNTL0_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="retxnb0" pos="23:16" rst="1">
        <comment>
          Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). 
Default value is 1 
        </comment>
      </bits>
      <bits access="r" name="eSCOLTCNTL0_reserved_1" pos="15:6" rst="0">
      </bits>
      <bits access="rw" name="escoedrrx0" pos="5" rst="0">
        <comment>
          1: eSCO EDR Mode (2/3 Mbps) in reception 
0: eSCO 1Mbps in reception 
        </comment>
      </bits>
      <bits access="rw" name="escoedrtx0" pos="4" rst="0">
        <comment>
          1: eSCO EDR Mode (2/3 Mbps) in transmission 
0: eSCO 1Mbps in transmission 
        </comment>
      </bits>
      <bits access="rw" name="syntype0" pos="3" rst="0">
        <comment>
          Synchronous packet type: 
0: SCO packet 
1: eSCO packet 
        </comment>
      </bits>
      <bits access="rw" name="synltaddr0" pos="2:0" rst="0">
        <comment>
          LT_ADDR of the Synchronous link (eSCO), used for TX. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOTRCNTL0">
      <bits access="rw" name="txseqn0" pos="31" rst="0">
        <comment>
          Value of the SEQN bit in eSCO TX packets. Used as follows: 
-      Initialized by SW during eSCO link establishment 
-      Toggled by HW on each TSCO/TeSCO, written back afterwards 
        </comment>
      </bits>
      <bits access="r" name="eSCOTRCNTL0_reserved_0" pos="30" rst="0">
      </bits>
      <bits access="rw" name="txlen0" pos="29:20" rst="0">
        <comment>
          Negotiated, maximum number of bytes for eSCO Tx payloads.  
        </comment>
      </bits>
      <bits access="rw" name="txtype0" pos="19:16" rst="0">
        <comment>
          Negotiated Tx packet type, as defined in [1]. 
        </comment>
      </bits>
      <bits access="r" name="eSCOTRCNTL0_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="rxlen0" pos="13:4" rst="0">
        <comment>
          Negotiated,  maximum  number  of  bytes  for  eSCO  Rx  payloads.  The  reception  of  the  payload  is automatically aborted if this buffer size is exceeded. 
        </comment>
      </bits>
      <bits access="rw" name="rxtype0" pos="3:0" rst="0">
        <comment>
          Negotiated Rx packet type, as defined in [1]. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCODAYCNT0">
      <bits access="r" name="eSCODAYCNT0_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="rw" name="daycounter0" pos="10:0" rst="0">
        <comment>
          Day Counter for AES-CCM nonce. 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="eSCOCHANCNTL1">
      <bits access="r" name="tog1" pos="31" rst="0">
        <comment>
          Toggle command for Voice Channel 1.  
Driven  by  TeSCO/TSCO  toggling  instant.  Used  to  perform  selection  of  PCM  pointers  and  Tx/Rx Descriptor. 
Please refer to section 2.18.5 for details. 
        </comment>
      </bits>
      <bits access="r" name="eSCOCHANCNTL1_reserved_0" pos="30:16" rst="0">
      </bits>
      <bits access="rw" name="escochanswen1" pos="15" rst="0">
        <comment>
          Enables  eSCO  Channel  1  SW  Transport  (Enable  Audio  data  to  be  routed  directly  to  EM  (or  through AES-CCM if encrypted link), used by Voice Transparent Modes: 
0: Disabled. 
1: Enabled. 
        </comment>
      </bits>
      <bits access="rw" name="escochanen1" pos="14" rst="0">
        <comment>
          Enables eSCO Channel 1 (controls Audio Path EM Access controller voice channel 1): 
0: Disabled. 
1: Enabled. 
        </comment>
      </bits>
      <bits access="rw" name="itmode1" pos="13" rst="0">
        <comment>
          0: bt_audio1_irq is generated on TeSCO/TSCO instant 
1: bt_audio1_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant 
        </comment>
      </bits>
      <bits access="rw" name="intdelay1" pos="12:8" rst="0">
        <comment>
          Valid if ITMODE1 = 1 
Determines the slot number to wait before generating bt_audio1_irq 
        </comment>
      </bits>
      <bits access="rw" name="tesco1" pos="7:0" rst="0">
        <comment>
          eSCO interval (in slots). 
Support  a  [2:16]  range  in  slots  so  as  to  support  both  SCO  and  eSCO  mandatory  LMP  parameters range (see [1]) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOMUTECNTL1">
      <bits access="r" name="eSCOMUTECNTL1_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="mute_sink1" pos="23" rst="0">
        <comment>
          HW mute control: 
0: Do not mute on bad reception of an (e)SCO packet. 
1: Mute after data or bad reception, with the pattern stored in MUTEPATT1
Note: See Table 2-34 for mute pattern value to apply 
        </comment>
      </bits>
      <bits access="rw" name="mute_source1" pos="22" rst="0">
        <comment>
          HW mute control: 
0: Provides Source buffer to the Packet Controller for Tx operations 
1: Forces POLL/NULL to be sent as a replacement of Audio Packets 
        </comment>
      </bits>
      <bits access="r" name="eSCOMUTECNTL1_reserved_1" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="invl1_1" pos="19:18" rst="2">
        <comment>
          SW mute status for Audio buffer 1 (i.e updated when TOG1=1): 
Mute if not null. Please refer to Table 2-35 for details
        </comment>
      </bits>
      <bits access="rw" name="invl1_0" pos="17:16" rst="2">
        <comment>
          SW mute status for Audio buffer 0 (i.e updated when TOG1=0): 
Mute if not null. Please refer to Table 2-35 for details
        </comment>
      </bits>
      <bits access="rw" name="mutepatt1" pos="15:0" rst="0">
        <comment>
          Value of the null pattern used when HW muting is enabled. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOCURRENTTXPTR1">
      <bits access="rw" name="esco1ptrtx1" pos="31:16" rst="0">
        <comment>
          Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 1. 
Used when eSCOCHANCNTL1-TOG1 = 1 
        </comment>
      </bits>
      <bits access="rw" name="esco1ptrtx0" pos="15:0" rst="0">
        <comment>
          Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 1. 
Used when eSCOCHANCNTL1-TOG1 = 0 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOCURRENTRXPTR1">
      <bits access="rw" name="esco1ptrrx1" pos="31:16" rst="0">
        <comment>
          Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 1. 
Used when eSCOCHANCNTL1-TOG1 = 1 
        </comment>
      </bits>
      <bits access="rw" name="esco1ptrrx0" pos="15:0" rst="0">
        <comment>
          Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 1. 
Used when eSCOCHANCNTL1-TOG1 = 0 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOLTCNTL1">
      <bits access="r" name="eSCOLTCNTL1_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="retxnb1" pos="23:16" rst="1">
        <comment>
          Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). 
Default value is 1 
        </comment>
      </bits>
      <bits access="r" name="eSCOLTCNTL1_reserved_1" pos="15:6" rst="0">
      </bits>
      <bits access="rw" name="escoedrrx1" pos="5" rst="0">
        <comment>
          1: eSCO EDR Mode (2/3 Mbps) in reception 
0: eSCO 1Mbps in reception 
        </comment>
      </bits>
      <bits access="rw" name="escoedrtx1" pos="4" rst="0">
        <comment>
          1: eSCO EDR Mode (2/3 Mbps) in transmission 
0: eSCO 1Mbps in transmission 
        </comment>
      </bits>
      <bits access="rw" name="syntype1" pos="3" rst="0">
        <comment>
          Synchronous packet type: 
0: SCO packet 
1: eSCO packet 
        </comment>
      </bits>
      <bits access="rw" name="syntaddr1" pos="2:0" rst="0">
        <comment>
          LT_ADDR of the Synchronous link (eSCO), used for TX. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOTRCNTL1">
      <bits access="rw" name="txseqn1" pos="31" rst="0">
        <comment>
          Value of the SEQN bit in eSCO TX packets. Used as follows: 
-      Initialized by SW during eSCO link establishment 
-      Toggled by HW each TSCO/TeSCO, written back afterwards 
        </comment>
      </bits>
      <bits access="r" name="eSCOTRCNTL1_reserved_0" pos="30" rst="0">
      </bits>
      <bits access="rw" name="txlen1" pos="29:20" rst="0">
        <comment>
          Negotiated, maximum number of bytes for eSCO Tx payloads.  
        </comment>
      </bits>
      <bits access="rw" name="txtype1" pos="19:16" rst="0">
        <comment>
          Negotiated Tx packet type, as defined in [1]. 
        </comment>
      </bits>
      <bits access="r" name="eSCOTRCNTL1_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="rxlen1" pos="13:4" rst="0">
        <comment>
          Negotiated,  maximum  number  of  bytes  for  eSCO  Rx  payloads.  The  reception  of  the  payload  is automatically aborted if this buffer size is exceeded. 
        </comment>
      </bits>
      <bits access="rw" name="rxtype1" pos="3:0" rst="0">
        <comment>
          Negotiated Rx packet type, as defined in [1]. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCODAYCNT1">
      <bits access="r" name="eSCODAYCNT1_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="rw" name="daycounter1" pos="10:0" rst="0">
        <comment>
          Day Counter for AES-CCM nonce. 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="eSCOCHANCNTL2">
      <bits access="r" name="tog2" pos="31" rst="0">
        <comment>
          Toggle command for Voice Channel 2.  
Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor 
Please refer to section 2.18.5 for details. 
        </comment>
      </bits>
      <bits access="r" name="eSCOCHANCNTL2_reserved_0" pos="30:16" rst="0">
      </bits>
      <bits access="rw" name="escochanswen2" pos="15" rst="0">
        <comment>
          Enables  eSCO  Channel  2  SW  Transport  (Enable  Audio  data  to  be  routed  directly  to  EM  (or  through AES-CCM if encrypted link), used by Voice Transparent Modes: 
0: Disabled. 
1: Enabled. 
        </comment>
      </bits>
      <bits access="rw" name="escochanen2" pos="14" rst="0">
        <comment>
          Enables eSCO Channel 2 (controls Audio Path EM Access controller voice channel 2): 
0: Disabled. 
1: Enabled. 
        </comment>
      </bits>
      <bits access="rw" name="itmode2" pos="13" rst="0">
        <comment>
          0: bt_audio2_irq is generated on TeSCO/TSCO instant 
1: bt_audio2_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant 
        </comment>
      </bits>
      <bits access="rw" name="intdelay2" pos="12:8" rst="0">
        <comment>
          Valid if ITMODE2 = 1 
Determines the slot number to wait before generating bt_audio2_irq 
        </comment>
      </bits>
      <bits access="rw" name="tesco2" pos="7:0" rst="0">
        <comment>
          eSCO interval (in slots). 
Support  a  [2:16]  range  in  slots  so  as  to  support  both  SCO  and  eSCO  mandatory  LMP  parameters range (see [1]) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOMUTECNTL2">
      <bits access="r" name="eSCOMUTECNTL2_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="mute_sink2" pos="23" rst="0">
        <comment>
          HW mute control: 
0: Do not mute on bad reception of an (e)SCO packet. 
1: Mute after data or bad reception, with the pattern stored in MUTEPATT2
Note: See Table 2-34 for mute pattern value to apply 
        </comment>
      </bits>
      <bits access="rw" name="mute_source2" pos="22" rst="0">
        <comment>
          HW mute control: 
0: Provides Source buffer to the Packet Controller for Tx operations 
1: Forces POLL/NULL to be sent as a replacement of Audio Packets 
        </comment>
      </bits>
      <bits access="r" name="eSCOMUTECNTL2_reserved_1" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="invl2_1" pos="19:18" rst="2">
        <comment>
          SW mute status for Audio buffer 1 (i.e updated when TOG2=1): 
Mute if not null. Please refer to Table 2-35 for details
        </comment>
      </bits>
      <bits access="rw" name="invl2_0" pos="17:16" rst="2">
        <comment>
          SW mute status for Audio buffer 0 (i.e updated when TOG2=0): 
Mute if not null. Please refer to Table 2-35 for details
        </comment>
      </bits>
      <bits access="rw" name="mutepatt2" pos="15:0" rst="0">
        <comment>
          Value of the null pattern used when HW muting is enabled. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOCURRENTTXPTR2">
      <bits access="rw" name="esco2ptrtx1" pos="31:16" rst="0">
        <comment>
          Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 2. 
Used when eSCOCHANCNTL2-TOG2 = 1 
        </comment>
      </bits>
      <bits access="rw" name="esco2ptrtx0" pos="15:0" rst="0">
        <comment>
          Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 2. 
Used when eSCOCHANCNTL2-TOG2 = 0 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOCURRENTRXPTR2">
      <bits access="rw" name="esco2ptrrx1" pos="31:16" rst="0">
        <comment>
          Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 2. 
Used when eSCOCHANCNTL2-TOG2 = 1 
        </comment>
      </bits>
      <bits access="rw" name="esco2ptrrx0" pos="15:0" rst="0">
        <comment>
          Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 2. 
Used when eSCOCHANCNTL2-TOG2 = 0 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOLTCNTL2">
      <bits access="r" name="eSCOLTCNTL2_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="retxnb2" pos="23:16" rst="1">
        <comment>
          Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). 
Default value is 1 
        </comment>
      </bits>
      <bits access="r" name="eSCOLTCNTL2_reserved_1" pos="15:6" rst="0">
      </bits>
      <bits access="rw" name="escoedrrx2" pos="5" rst="0">
        <comment>
          1: eSCO EDR Mode (2/3 Mbps) in reception 
0: eSCO 1Mbps in reception 
        </comment>
      </bits>
      <bits access="rw" name="escoedrtx2" pos="4" rst="0">
        <comment>
          1: eSCO EDR Mode (2/3 Mbps) in transmission 
0: eSCO 1Mbps in transmission 
        </comment>
      </bits>
      <bits access="rw" name="syntype2" pos="3" rst="0">
        <comment>
          Synchronous packet type: 
0: SCO packet 
1: eSCO packet 
        </comment>
      </bits>
      <bits access="rw" name="syntaddr2" pos="2:0" rst="0">
        <comment>
          LT_ADDR of the Synchronous link (eSCO), used for TX. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCOTRCNTL2">
      <bits access="rw" name="txseqn2" pos="31" rst="0">
        <comment>
          Value of the SEQN bit in eSCO TX packets. Used as follows: 
-      Initialized by SW during eSCO link establishment 
-      Toggled by HW each TSCO/TeSCO, written back afterwards 
        </comment>
      </bits>
      <bits access="r" name="eSCOTRCNTL2_reserved_0" pos="30" rst="0">
      </bits>
      <bits access="rw" name="txlen2" pos="29:20" rst="0">
        <comment>
          Negotiated, maximum number of bytes for eSCO Tx payloads.  
        </comment>
      </bits>
      <bits access="rw" name="txtype2" pos="19:16" rst="0">
        <comment>
          Negotiated Tx packet type, as defined in [1]. 
        </comment>
      </bits>
      <bits access="r" name="eSCOTRCNTL2_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="rxlen2" pos="13:4" rst="0">
        <comment>
          Negotiated,  maximum  number  of  bytes  for  eSCO  Rx  payloads.  The  reception  of  the  payload  is automatically aborted if this buffer size is exceeded. 
        </comment>
      </bits>
      <bits access="rw" name="rxtype2" pos="3:0" rst="0">
        <comment>
          Negotiated Rx packet type, as defined in [1]. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="eSCODAYCNT2">
      <bits access="r" name="eSCODAYCNT2_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="rw" name="daycounter2" pos="10:0" rst="0">
        <comment>
          Day Counter for AES-CCM nonce. 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="AUDIOCNTL0">
      <bits access="r" name="AUDIOCNTL0_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="rw" name="linear_format0" pos="21:20" rst="3">
        <comment>
          Sample Linear format for voice channel 0 
00: 8-bit samples 
01: 13-bit samples 
10: 14-bit samples 
11: 16-bit samples  
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL0_reserved_1" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="sample_type0" pos="17:16" rst="1">
        <comment>
          PCM / VoHCI Sample Type on Audio Path Channel 0 
00: Signed 1's complement 
01: Signed 2's complement 
10: Signed magnitude 
11: Unsigned 
        </comment>
      </bits>
      <bits access="rw" name="aulawen0" pos="15" rst="0">
        <comment>
          a/u-Law control for voice channel 0 
1: Enables a/u-Law transcoding 
0: Disables a/u-Law transcoding / bypass mode 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL0_reserved_2" pos="14:12" rst="0">
      </bits>
      <bits access="rw" name="aulaw_code0" pos="11:8" rst="0">
        <comment>
          a/u-Law configuration code for voice channel 0. (See Table 2-40) 
        </comment>
      </bits>
      <bits access="rw" name="cvsden0" pos="7" rst="0">
        <comment>
          CVSD control for voice channel 0 
1: Enables CVSD transcoding 
0: Disables CVSD transcoding / bypass mode 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL0_reserved_3" pos="6:1" rst="0">
      </bits>
      <bits access="rw" name="cvsd_bitorder0" pos="0" rst="0">
        <comment>
          Bit ordering at Byte interface for voice channel 0 
0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder.  
1:  MSB  First.  Compatible  to  BT  spec.  1.0B  (ref.  to  [1])  The  bits  are  sent  in  the  reverse  order (maintains backward compatibility). 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="AUDIOCNTL1">
      <bits access="r" name="AUDIOCNTL1_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="rw" name="linear_format1" pos="21:20" rst="3">
        <comment>
          Sample Linear format for voice channel 1 
00: 8-bit samples 
01: 13-bit samples 
10: 14-bit samples 
11: 16-bit samples 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL1_reserved_1" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="sample_type1" pos="17:16" rst="1">
        <comment>
          PCM / VoHCI Sample Type on Audio Path Channel 1 
00: Signed 1's complement 
01: Signed 2's complement 
10: Signed magnitude 
11: Unsigned 
        </comment>
      </bits>
      <bits access="rw" name="aulawen1" pos="15" rst="0">
        <comment>
          a/u-Law control for voice channel 1 
1: Enables a/u-Law transcoding 
0: Disables a/u-Law transcoding / bypass mode 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL1_reserved_2" pos="14:12" rst="0">
      </bits>
      <bits access="rw" name="aulaw_code1" pos="11:8" rst="0">
        <comment>
          a/u-Law configuration code for voice channel 1. (See Table 2-40) 
        </comment>
      </bits>
      <bits access="rw" name="cvsden1" pos="7" rst="0">
        <comment>
          CVSD control for voice channel 1 
1: Enables CVSD transcoding 
0: Disables CVSD transcoding / bypass mode 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL1_reserved_3" pos="6:1" rst="0">
      </bits>
      <bits access="rw" name="cvsd_bitorder1" pos="0" rst="0">
        <comment>
          Bit ordering at Byte interface for voice channel 1 
0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder.  
1:  MSB  First.  Compatible  to  BT  spec.  1.0B  (ref.  to  [1])  The  bits  are  sent  in  the  reverse  order (maintains backward compatibility). 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="AUDIOCNTL2">
      <bits access="r" name="AUDIOCNTL2_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="rw" name="linear_format2" pos="21:20" rst="3">
        <comment>
          Sample Linear format for voice channel 2 
00: 8-bit samples 
01: 13-bit samples 
10: 14-bit samples 
11: 16-bit samples 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL2_reserved_1" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="sample_type2" pos="17:16" rst="1">
        <comment>
          PCM / VoHCI Sample Format on Audio Path Channel 2 
00: Signed 1's complement 
01: Signed 2's complement 
10: Signed magnitude 
11: Unsigned 
        </comment>
      </bits>
      <bits access="rw" name="aulawen2" pos="15" rst="0">
        <comment>
          a/u-Law control for voice channel 2 
1: Enables a/u-Law transcoding 
0: Disables a/u-Law transcoding / bypass mode 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL2_reserved_2" pos="14:12" rst="0">
      </bits>
      <bits access="rw" name="aulaw_code2" pos="11:8" rst="0">
        <comment>
          a/u-Law configuration code for voice channel 2. (See Table 2-40) 
        </comment>
      </bits>
      <bits access="rw" name="cvsden2" pos="7" rst="0">
        <comment>
          CVSD control for voice channel 2 
1: Enables CVSD transcoding 
0: Disables CVSD transcoding / bypass mode 
        </comment>
      </bits>
      <bits access="r" name="AUDIOCNTL2_reserved_3" pos="6:1" rst="0">
      </bits>
      <bits access="rw" name="cvsd_bitorder2" pos="0" rst="0">
        <comment>
          Bit ordering at Byte interface for voice channel 2 
0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder.  
1:  MSB  First.  Compatible  to  BT  spec.  1.0B  (ref.  to  [1])  The  bits  are  sent  in  the  reverse  order (maintains backward compatibility). 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="PCMGENCNTL">
      <bits access="r" name="PCMGENCNTL_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="rw" name="vxchsel" pos="9:8" rst="0">
        <comment>
          Voice channel Selection. Select the voice channel to be routed to the PCM 
00: Voice Channel 0 routed to PCM 
01: Voice Channel 1 routed to PCM 
10: Voice Channel 2 routed to PCM 
11: Reserved 
        </comment>
      </bits>
      <bits access="r" name="PCMGENCNTL_reserved_1" pos="7" rst="0">
      </bits>
      <bits access="rw" name="loopback" pos="6" rst="0">
        <comment>
          Loopback Test mode control 
1: Loopback Mode enabled 
0: Loopback Mode disabled / Normal operations 
        </comment>
      </bits>
      <bits access="rw" name="mono_lr_sel" pos="5" rst="0">
        <comment>
          Valid when SAMPTYPE is set to Stereo mode, else not applicable 
0: Select Left channel audio samples for Mono operation 
1: Select Right channel audio samples for Mono operation 
        </comment>
      </bits>
      <bits access="rw" name="mono_stereo" pos="4" rst="0">
        <comment>
          Audio channel Mono/Stereo mode control 
0: Audio channel carries Mono samples 
1: Audio channel carries Stereo samples 
        </comment>
      </bits>
      <bits access="rw" name="mstslv" pos="3" rst="0">
        <comment>
          Master/Slave mode control 
0: PCM is master (i.e. PCM generates pcmclk_out and pcmfsync_out from PLL) 
1: PCM is slave (i.e. PLL disabled and pcmclk_in and pcmfsync_in are used) 
        </comment>
      </bits>
      <bits access="rw" name="byteswap" pos="2" rst="0">
        <comment>
          Byte swapping control, valid only SAMPSZ is set to 16-bits 
0: Samples to be sent used "as-is" 
1: MSB and LSB bytes are swapped within samples 
        </comment>
      </bits>
      <bits access="rw" name="lrswap" pos="1" rst="0">
        <comment>
          Valid in Stereo mode only, defines the Left / Right channel order 
0: Left channel then Right channel 
1: Right channel then Left channel 
        </comment>
      </bits>
      <bits access="rw" name="pcmen" pos="0" rst="0">
        <comment>
          PCM main control 
0: PCM disabled (i.e. pcm_gclk clock not enabled) 
1: PCM enabled (i.e. pcm_gclk clock enabled) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMPHYSCNTL0">
      <bits access="r" name="PCMPHYSCNTL0_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="rw" name="firstactslot" pos="21:20" rst="0">
        <comment>
          Configures the first active slot of the frame, in [0:3] range 
00: first active slot is slot 0 
01: first active slot is slot 1 
10: first active slot is slot 2 
11: first active slot is slot 3 
The maximum value this field can be configured to is determined by the SLOTNB-1 parameters. 
        </comment>
      </bits>
      <bits access="r" name="PCMPHYSCNTL0_reserved_1" pos="19" rst="0">
      </bits>
      <bits access="rw" name="slotnb" pos="18:16" rst="0">
        <comment>
          Number of slots within a PCM frame  
Valid values are in [1:4] range. 
Other values are meaningless 
        </comment>
      </bits>
      <bits access="r" name="PCMPHYSCNTL0_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="samptype" pos="13" rst="0">
        <comment>
          PCM Codec Sample type  
0: PCM codec supports Mono operation 
1: PCM codec supports Stereo operation 
        </comment>
      </bits>
      <bits access="rw" name="sampsz" pos="12" rst="0">
        <comment>
          PCM codec Sample size 
0: PCM Frame carries 8-bit samples 
1: PCM Frame carries 16-bit samples 
        </comment>
      </bits>
      <bits access="r" name="PCMPHYSCNTL0_reserved_3" pos="11" rst="0">
      </bits>
      <bits access="rw" name="lsb1st" pos="10" rst="0">
        <comment>
          Bit ordering within a PCM Frame 
0: Sample are sent/received MSB first 
1: Samples are sent/received LSB first 
        </comment>
      </bits>
      <bits access="rw" name="pcm_iom" pos="9" rst="0">
        <comment>
          PCM / IOM mode selection 
0: PCM mode (single clocking) 
1: IOM mode (double clocking) 
        </comment>
      </bits>
      <bits access="rw" name="lrchpol" pos="8" rst="0">
        <comment>
          Selection  of  the  PCM  Frame  Synchronization  polarity  (Valid  when  SAMPTYPE  is  set  to  Stereo mode, else not applicable) 
0: Right channel when = 0, Left channel when = 1 
1: Right channel when = 1, Left channel when = 0 
        </comment>
      </bits>
      <bits access="r" name="PCMPHYSCNTL0_reserved_4" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="doutcfg" pos="5:4" rst="0">
        <comment>
          Physical configuration of the pcmd_out pad. 
00: Open-drain, hi-Z outside transmission 
01: Push-pull, hi-Z outside transmission 
10: Push-pull, driven to 0 outside transmission 
11: Reserved 
        </comment>
      </bits>
      <bits access="r" name="PCMPHYSCNTL0_reserved_5" pos="3" rst="0">
      </bits>
      <bits access="rw" name="fsyncshp" pos="2:0" rst="0">
        <comment>
          Physical shape of the PCM Frame Synchronization signal. 
000: LF enclosing the last falling PCM Interface Clock edge in frame (Mono only) 
001: FR enclosing the first rising PCM Interface Clock edge in frame (Mono only) 
010: FF enclosing the first falling PCM Interface Clock edge in frame (Mono only) 
011: LONG enclosing the first slot (8 bits) of the frame (Mono / Stereo 8-bits only) 
100: LONG_16 enclosing first two slots (16 bits) of the frame (Mono 16 bits / Stereo 16-bits only) 
101:  STEREO  Left/Right  Frame  differentiating  (Stereo  only,  covers  left  or  right  channel  only, polarity is set according to LRCHPOL) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMPHYSCNTL1">
      <bits access="rw" name="clkinv" pos="31" rst="0">
        <comment>
          Selection of the PCM Interface Clock polarity 
0: Data is clocked out with the rising edge (standard) 
1: Data is clocked out with the falling edge 
        </comment>
      </bits>
      <bits access="r" name="PCMPHYSCNTL1_reserved_0" pos="30:24" rst="0">
      </bits>
      <bits access="rw" name="pcmclklimit" pos="23:16" rst="0">
        <comment>
          PCM Clock counter limit 
        </comment>
      </bits>
      <bits access="r" name="PCMPHYSCNTL1_reserved_1" pos="15:9" rst="0">
      </bits>
      <bits access="rw" name="pcmclkval" pos="8:0" rst="0">
        <comment>
          PCM Clock Counter value. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMPADDING">
      <bits access="rw" name="rsamppad" pos="31:16" rst="0">
        <comment>
          Right channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first)  
        </comment>
      </bits>
      <bits access="rw" name="lsamppad" pos="15:0" rst="0">
        <comment>
          Left channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first) 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMPLLCNTL0">
      <bits access="r" name="PCMPLLCNTL0_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="rw" name="rl" pos="19:0" rst="0">
        <comment>
          PLL control word, see equation below. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMPLLCNTL1">
      <bits access="r" name="PCMPLLCNTL1_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="olc" pos="30:20" rst="0">
        <comment>
          Open Loop Correction value, see equation below.  
        </comment>
      </bits>
      <bits access="r" name="PCMPLLCNTL1_reserved_1" pos="19" rst="0">
      </bits>
      <bits access="rw" name="a" pos="18:0" rst="0">
        <comment>
          PLL control word, see equation below. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMPLLCNTL2">
      <bits access="r" name="PCMPLLCNTL2_reserved_0" pos="31:19" rst="0">
      </bits>
      <bits access="rw" name="w" pos="18:0" rst="0">
        <comment>
          PLL control word, see equation below. 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMSOURCEPTR">
      <bits access="rw" name="pcmsourceptr1" pos="31:16" rst="0">
        <comment>
          PCM Source Pointer 1 / Air to PCM direction 
        </comment>
      </bits>
      <bits access="rw" name="pcmsourceptr0" pos="15:0" rst="0">
        <comment>
          PCM Source Pointer 0 / Air to PCM direction 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PCMSINKPTR">
      <bits access="rw" name="pcmsinkptr1" pos="31:16" rst="0">
        <comment>
          PCM Sink Pointer 1 / PCM to Air direction 
        </comment>
      </bits>
      <bits access="rw" name="pcmsinkptr0" pos="15:0" rst="0">
        <comment>
          PCM Sink Pointer 0 / PCM to Air direction 
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="rw" name="BREDRPRIOSCHARB">
      <bits access="r" name="BREDRPRIOSCHARB_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="bredrpriomode" pos="15" rst="0">
        <comment>
          Determine BR/EDR Priority Scheduling Arbitration Mode 
0: BR/EDR Decision instant not used 
1: BR/EDR Decision instant used 
        </comment>
      </bits>
      <bits access="r" name="BREDRPRIOSCHARB_reserved_1" pos="14:8" rst="0">
      </bits>
      <bits access="rw" name="bredrmargin" pos="7:0" rst="0">
        <comment>
          Determine the decision instant margin for Priority Scheduling Arbitration. Decision instant is defined as per formula of section 3.6 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PLCADDR01">
      <bits access="rw" name="plcbaseaddr1" pos="31:16" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
      <bits access="rw" name="plcbaseaddr0" pos="15:0" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PLCADDR23">
      <bits access="rw" name="plcbaseaddr3" pos="31:16" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
      <bits access="rw" name="plcbaseaddr2" pos="15:0" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PLCADDR45">
      <bits access="rw" name="plcbaseaddr5" pos="31:16" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
      <bits access="rw" name="plcbaseaddr4" pos="15:0" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PLCADDR67">
      <bits access="rw" name="plcbaseaddr7" pos="31:16" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
      <bits access="rw" name="plcbaseaddr6" pos="15:0" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PLCADDR89">
      <bits access="rw" name="plcbaseaddr9" pos="31:16" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
      <bits access="rw" name="plcbaseaddr8" pos="15:0" rst="0">
        <comment>
          PLC Pool Base Addr
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PLCADDRB">
      <bits access="r" name="PLCADDRB_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="plcbufaddr" pos="15:0" rst="0">
        <comment>
          PLC Pool buf Addr
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="PLCCONF">
      <bits access="s" name="plc_int_clr" pos="31" rst="1">
        <comment>
        bit type is changed from wos to s.

          plc interrput clear pulse
        </comment>
      </bits>
      <bits access="r" name="plc_int" pos="30" rst="0">
        <comment>
          plc interrput
        </comment>
      </bits>
      <bits access="r" name="plc_done" pos="29" rst="0">
        <comment>
          plc_done
        </comment>
      </bits>
      <bits access="r" name="plc_fsm_state" pos="28:25" rst="0">
        <comment>
          plc ctrl fsm state
        </comment>
      </bits>
      <bits access="s" name="conf_plc_restart" pos="24" rst="0">
        <comment>
        bit type is changed from wos to s.

          plc_restart
        </comment>
      </bits>
      <bits access="r" name="PLCCONF_reserved_0" pos="23" rst="0">
      </bits>
      <bits access="rw" name="conf_plc_int_mask" pos="22" rst="0">
        <comment>
          mask for plc interrupt
        </comment>
      </bits>
      <bits access="rw" name="conf_pcm_use_mem_access_sel" pos="21" rst="0">
        <comment>
          pcm use mem access method
        </comment>
      </bits>
      <bits access="rw" name="conf_scaling_mode" pos="20" rst="0">
        <comment>
          plc scaling mode
        </comment>
      </bits>
      <bits access="rw" name="conf_frame_mode" pos="19:18" rst="0">
        <comment>
          frame_mode length_x000D_
0: 120_x000D_  1: 90 2:60_x000D_ 3:30
        </comment>
      </bits>
      <bits access="rw" name="conf_plc_type" pos="17" rst="0">
        <comment>
          indicate current farme bad or good
        </comment>
      </bits>
      <bits access="rw" name="conf_plc_en" pos="16" rst="0">
        <comment>
          enable for PLC
        </comment>
      </bits>
      <bits access="rw" name="conf_no_pitch_find_ref_threshold_dist" pos="15:0" rst="0">
        <comment>
          threshold for finding pitch
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative = "rda8909_bt_mem.xml">
  <var name="BT_ROM_SIZE"           value="256*1024" />   
  <var name="BT_RAM_SIZE"           value="256*1024" />   
  <var name="BT_EXCHANGE_RAM_SIZE"  value="24*1024" />    

  
  <module name="bt_rom" category="WCN">
    <memory name="rom_array" size="BT_ROM_SIZE">
      <comment>WCN Rom Space
        <br/>This rom is used for WCN RISC-V boot code.
      </comment>
    </memory>
  </module>

  
  <module name="bt_ram" category="WCN">
    <memory name="ram_array" size="BT_RAM_SIZE">
      <comment>WCN Ram Space
        <br/>
      </comment>
    </memory>
  </module>

  
  <module name="bt_exchange_ram" category="WCN">
    <memory name="ram_array" size="BT_EXCHANGE_RAM_SIZE">
      <comment>BT Exchange RAM Space
      </comment>
    </memory>
  </module>


</archive>
<archive relative="bt_modem.xml">
  <module name="bt_modem" category="WCN">
    <reg protect="rw" name="bypass_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="rw" name="bypass_dccancel" pos="15" rst="0">
        <comment>
          Bypass DC Cancel
1'h0:: not_bypass: RX DC Cancel is not bypassed
1'h1:: bypass: RX DC Cancel is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_dccancel2" pos="14" rst="1">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="bypass_mixer" pos="13" rst="0">
        <comment>
          Bypass Mixer
1'h0:: not_bypass: RX Mixer is not bypassed
1'h1:: bypass: RX Mixer is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_srrc" pos="12" rst="0">
        <comment>
          Bypass Square-root-raised-cosine Filter
1'h0:: not_bypass: RX SRRC filter is not bypassed
1'h1:: bypass: RX SRRC filter is bypassed
        </comment>
      </bits>
      <bits access="r" name="bypass_ctrl_reserved_0" pos="11:9" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="bypass_derr1_gfsk" pos="8" rst="0">
        <comment>
          Bypass GFSK Derr1
1'h0:: not_bypass: RX GFSK Derr1 is not bypassed
1'h1:: bypass: RX GFSK Derr1 is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_derr2_gfsk" pos="7" rst="0">
        <comment>
          Bypass GFSK Derr2
1'h0:: not_bypass: RX GFSK Derr2 is not bypassed
1'h1:: bypass: RX GFSK Derr2 is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_patch_gfsk" pos="6" rst="0">
        <comment>
          Bypass GFSK Patch
1'h0:: not_bypass: GFSK Patch is not bypassed
1'h1:: bypass: GFSK Patch is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_smppt_gfsk" pos="5" rst="0">
        <comment>
          Bypass GFSK Sample Step
1'h0:: not_bypass: RX GFSK Sample Step is 1
1'h1:: bypass: RX GFSK Sample Step is 0
        </comment>
      </bits>
      <bits access="rw" name="bypass_derr1_dpsk" pos="4" rst="0">
        <comment>
          Bypass DPSK Derr1
1'h0:: not_bypass: RX DPSK Derr1 is not bypassed
1'h1:: bypass: RX DPSK Derr1 is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_derr2_dpsk" pos="3" rst="0">
        <comment>
          Bypass DPSK Derr2
1'h0:: not_bypass: RX DPSK Derr2 is not bypassed
1'h1:: bypass: RX DPSK Derr2 is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_patch_dpsk" pos="2" rst="0">
        <comment>
          Bypass DPSK Patch
1'h0:: not_bypass: DPSK Patch is not bypassed
1'h1:: bypass: DPSK Patch is bypassed
        </comment>
      </bits>
      <bits access="rw" name="bypass_smppt_dpsk" pos="1" rst="0">
        <comment>
          Bypass DPSK Sample Step
1'h0:: not_bypass: RX DPSK Sample Step is 1
1'h1:: bypass: RX DPSK Sample Step is 0
        </comment>
      </bits>
      <bits access="rw" name="sel_rssi_src" pos="0" rst="0">
        <comment>
          Select RSSI Source
1'h0:: srrc_output: RSSI input data is from SRRC filter output
1'h1:: mixer_output: RSSI input data is from mixer output
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sw_swap_dccal">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="sw_swap_dccal_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="swch_clk_adc" pos="14" rst="0">
        <comment>
          Switch ADC Clock Edge
1'h0:: not_switch: ADC clock edge is not switched
1'h1:: switch: ADC clock edge is switched
        </comment>
      </bits>
      <bits access="rw" name="sel_sync" pos="13" rst="0">
        <comment>
          Select New Packet
1'h0:: from_LL: newpacket_dsp is from baseband
1'h1:: from_reg: newpacket_dsp is from newpacket_reg
        </comment>
      </bits>
      <bits access="rw" name="swch_clk_dac" pos="12" rst="1">
        <comment>
          Switch DAC Clock Edge
1'h0:: not_switch: DAC clock edge is not switched
1'h1:: switch: DAC clock edge is switched
        </comment>
      </bits>
      <bits access="rw" name="rsvd0" pos="11" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="lpf_dwidth_sel" pos="10:9" rst="1">
        <comment>
          LPF Data Width Select
2'h0:: shift_9bits
2'h1:: shift_8bits
2'h2:: shift_7bits
2'h3:: shift_6bits
        </comment>
      </bits>
      <bits access="rw" name="swch_sign_i_tx" pos="8" rst="0">
        <comment>
          Switch TX DAC datai sign
1'h0:: unsigned: TX DAC datai is unsigned; analog common format
1'h1:: signed: TX DAC datai is signed
        </comment>
      </bits>
      <bits access="rw" name="swch_sign_q_tx" pos="7" rst="0">
        <comment>
          Switch TX DAC dataq sign
1'h0:: unsigned: TX DAC dataq is unsigned; analog common format
1'h1:: signed: TX DAC dataq is signed
        </comment>
      </bits>
      <bits access="rw" name="swch_sign_rx" pos="6" rst="0">
        <comment>
          Switch RX ADC IQ data sign
1'h0:: unsigned: RX ADC data is unsigned; analog common format
1'h1:: signed: RX ADC data is signed
        </comment>
      </bits>
      <bits access="rw" name="iq_sel_pol" pos="5" rst="0">
        <comment>
          SRRC IQ_SEL Polarity
1'h0:: iq_sel_inv
1'h1:: iq_sel_raw
        </comment>
      </bits>
      <bits access="r" name="sw_swap_dccal_reserved_1" pos="4:3" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="sel_sumerr_range" pos="2:0" rst="3">
        <comment>
          Sum Error Range Control
3'h0 Left shift 3 bits of sum err and limit sumerr within [-2^-4, 2^-4]
3'h1 Left shift 2 bits of sum err and limit sumerr within [-2^-3, 2^-3]
3'h2 Left shift 1 bits of sum err and limit sumerr within [-2^-2, 2^-2]
3'h3 Hold the sum err
3'h4 Right shift 1 bits of sum err
3'h5 Right shift 2 bits of sum err
3'h6 Right shift 3 bits of sum err
3'h7 Right shift 4 bits of sum err;
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dem750_afc_freq">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="afc_smtif" pos="15:0" rst="58075">
        <comment>
          Set the AFC frequency of dem750 of rx link
dec2hex(2^16-round(2*740/13e3*2^16))
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dpsk_gfsk_tx_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="tx_gain_dpsk" pos="15:8" rst="208">
        <comment>
          DPSK TX Gain in EDR
        </comment>
      </bits>
      <bits access="rw" name="delay_gfsk" pos="7:4" rst="4">
        <comment>
          Set the delay of input gfsk symbol, delay unit is 13MHz clock cycle.
        </comment>
      </bits>
      <bits access="rw" name="delay_dpsk" pos="3:0" rst="8">
        <comment>
          Set the delay of input dpsk symbol, delay unit is 13MHz clock cycle.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_gain_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="cnt_guard_ini" pos="15:10" rst="40">
        <comment>
          Control the guard time length of bt frame
Guard time = (55-cnt_guard_ini)*T13Mclk
        </comment>
      </bits>
      <bits access="rw" name="tx_power_gain_sel" pos="9" rst="1">
        <comment>
          LL tx_power and debug tx_apc selection.
1'h1:: selected LL tx_power
1'h0::selected debug tx_apc
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_bypass" pos="8" rst="0">
        <comment>
          according to tx_power mapping digital gain.
1'h1:: bypass auto gain mapping function
1'h0:: no bypass
        </comment>
      </bits>
      <bits access="rw" name="tx_gain_gfsk" pos="7:0" rst="152">
        <comment>
          GFSK TX Gain in BR
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_out1">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_out1_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="rssi_out" pos="9:0" rst="0">
        <comment>
          RSSI Output.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sw_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="rssi_lock_by_agc" pos="15" rst="0">
        <comment>
          Receiver Strength Signal Indicator lock by agc done signal
        </comment>
      </bits>
      <bits access="rw" name="swap_iq" pos="14" rst="0">
        <comment>
          Swap I/Q
1'h0:: no_swap: I/Q is not swaped
1'h1:: swap: I/Q is swaped
        </comment>
      </bits>
      <bits access="rw" name="swap_iq_dccl_0" pos="13" rst="0">
        <comment>
          Swap I/Q of ddcl input data
1'h0:: no_swap: I/Q of ddcl input data is not swaped
1'h1:: swap: I/Q of ddcl input data is swaped
        </comment>
      </bits>
      <bits access="rw" name="swap_iq_smtif_0" pos="12" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="swap_iq_mixer_0" pos="11" rst="0">
        <comment>
          Swap I/Q of Mixer output data
1'h0:: no_swap: I/Q of mixer output data is not swaped
1'h1:: swap: I/Q of mixer output data is swaped
        </comment>
      </bits>
      <bits access="rw" name="swap_pn_i_dccl_0" pos="10" rst="0">
        <comment>
          Swap ddcl input I data polarity
1'h0:: no_swap: I data polarity of ddcl input is not swaped
1'h1:: swap: I data polarity of ddcl input is swaped
        </comment>
      </bits>
      <bits access="rw" name="swap_pn_q_dccl_0" pos="9" rst="0">
        <comment>
          Swap ddcl input Q data polarity
1'h0:: no_swap: Q data polarity of ddcl input is not swaped
1'h1:: swap: Q data polarity of ddcl input is swaped
        </comment>
      </bits>
      <bits access="rw" name="notch_disb" pos="8" rst="1">
        <comment>
          Disable the ramping for edr guard time in ramp_gain_tx
        </comment>
      </bits>
      <bits access="rw" name="tx_gain_gfsk_edr" pos="7:0" rst="112">
        <comment>
          GFSK TX Gain in EDR
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="adcclk_sw_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="adcclk_sw_ctrl_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="en_bbpkg_flg" pos="14" rst="1">
        <comment>
          BB Newpacket flag enable
1'h0:: Disable: the BB Newpacket flag enable
1'h1:: Enable: the BB Newpacket flag enable
        </comment>
      </bits>
      <bits access="rw" name="pckt_sel" pos="13" rst="0">
        <comment>
          Packet select
1'h0:: packet72
1'h1:: new_packet
        </comment>
      </bits>
      <bits access="rw" name="ct_u_gfsk" pos="12:9" rst="10">
        <comment>
          gfsk u_err 10/32
        </comment>
      </bits>
      <bits access="rw" name="ct_u_1_gfsk" pos="8:4" rst="28">
        <comment>
          gfsk u_dc 4/512
        </comment>
      </bits>
      <bits access="rw" name="ct_u_sp_gfsk" pos="3:0" rst="9">
        <comment>
          gfsk ct_u_sp for rx demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dpsk_demod_sw">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="ct_u_patch" pos="15:13" rst="1">
        <comment>
          Switch err_in_patch for bt_dsp rx demod
        </comment>
      </bits>
      <bits access="rw" name="ct_u_dpsk" pos="12:9" rst="8">
        <comment>
          dpsk u_err 8/32
        </comment>
      </bits>
      <bits access="rw" name="ct_u_1_dpsk" pos="8:4" rst="5">
        <comment>
          dpsk u_dc 5/64
        </comment>
      </bits>
      <bits access="rw" name="ct_u_sp_dpsk" pos="3:0" rst="9">
        <comment>
          Switch dpsk ct_u for bt_dsp rx demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="min_phase_err">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="min_error_th" pos="15:0" rst="3318">
        <comment>
          Set the minimum phase error for  rx demod.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="afc_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="sel_afc_gfskdem" pos="15:14" rst="2">
        <comment>
          Select the GFSK AFC of demod
        </comment>
      </bits>
      <bits access="rw" name="sel_afc_dpskseek" pos="13:12" rst="2">
        <comment>
          Select the DPSK AFC of demod
        </comment>
      </bits>
      <bits access="rw" name="rsvd1" pos="11:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="th_gfsk_dem" pos="9:0" rst="41">
        <comment>
          GFSK demod threshold
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dpsk_gfsk_smp_th">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="diff_enable_dpsk" pos="15" rst="0">
        <comment>
          DPSK diff enable
1'h0:: Disable
1'h1:: Enable
        </comment>
      </bits>
      <bits access="rw" name="diff_enable_gfsk" pos="14" rst="0">
        <comment>
          GFSK diff enable
1'h0:: Disable
1'h1:: Enable
        </comment>
      </bits>
      <bits access="rw" name="sp_th_sel_dpsk" pos="13:12" rst="0">
        <comment>
          DPSK sample threshold for demod
        </comment>
      </bits>
      <bits access="rw" name="sp_th_sel_gfsk" pos="11:10" rst="0">
        <comment>
          GFSK sample threshold for demod
        </comment>
      </bits>
      <bits access="rw" name="th_gfsk_dem2" pos="9:0" rst="10">
        <comment>
          GFSK sample 2nd threshold for demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dpsk_gfsk_smp_th_1">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="dpsk_gfsk_smp_th_1_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="ref_a2_sek" pos="9:0" rst="111">
        <comment>
          gfsk sample reference a2 for demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_smp_ref_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="ref_a1_sek" pos="15:8" rst="25">
        <comment>
          GFSK sample reference a1 for demod
        </comment>
      </bits>
      <bits access="rw" name="ref_a3_sek" pos="7:0" rst="25">
        <comment>
          GFSK sample reference a3 for demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_smp_ref_ctrl_1">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="rsvd2" pos="15:14" rst="1">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="guard_time_conf" pos="13:9" rst="1">
        <comment>
          tx guard timing delay to switch amp in ramp_gain_tx; counter in 13M
        </comment>
      </bits>
      <bits access="rw" name="dc_ct2" pos="8:0" rst="32">
        <comment>
          RESERVED
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rateconv_ctrl1">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="dc_ct" pos="15:7" rst="136">
        <comment>
          DC Cancle ct code for demod
        </comment>
      </bits>
      <bits access="rw" name="dac_test_en" pos="6" rst="0">
        <comment>
          DAC Test Enable
1'h0 dac data is 52m_tx IQ
1'h1 dac data depends on dac_data_sel
        </comment>
      </bits>
      <bits access="rw" name="dac_data_sel" pos="5:0" rst="0">
        <comment>
          DAC Data Mux Select
6'b000000:: tx_52m_i:      tx_52m_q
6'b000001:: tx_26m_i:     tx_26m_q
6'b000010:: iqim_cancel_i:      iqim_cancel_q
6'b000011:: tx_13m_i:      tx_13m_q
6'b000100:: mixer_tx_i:      mixer_tx_q
6'b000101:: accu_tx:     blend_tx
6'b000110:: gfilter_tx:     diff_tx
6'b000111:: ampm_am:     ampm_pm
6'b001000:: cordic_tx_amp:     cordic_tx_ang
6'b001001:: symbol2iq_tx_i:     symbol2iq_tx_q
6'b001010:: tx_test_data0:      tx_test_data1
6'b100000:: angle:       angle_rc
6'b100001:: adc_data_i:       adc_data_q
6'b100010:: adc_din_i:       adc_din_q
6'b100011:: lpf_i:       lpf_q
6'b100100:: rateconv_i:      rateconv_q
6'b100101:: calib_i:         calib_q
6'b100110:: dc_calib_i:      dc_calib_q
6'b100111:: cancel_flt_i:       cancel_flt_q
6'b101000:: notch_i:       notch_q
6'b101001:: gain_i:        gain_q
6'b101010:: ble_mux_i:     ble_mux_q
6'b101011:: mixer_i:      mixer_q
6'b101100:: srrc_i:     srrc_q
6'b101101:: mixer_i_13_0:    mixer_q[13:0]
6'b101110:: srrc_i_11_0:     srrc_q[11:0]
6'b101111:: err_gfsk:       err_dpsk
6'b110000:: afc_gfsk:       afc_in
6'b110001:: angle_offset:      angle_offset1
6'b110010:: rssi_out:      rssi_out
6'b110011:: rx_test_data0:       rx_test_data1
6'b110100:: rx_test_data2:      rx_test_data3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rateconv_ctrl2">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="rateconv_ctrl2_reserved_0" pos="15:7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dc_hold_edr_en" pos="6" rst="1">
        <comment>
          DC cancle1 edr dc hold enable
        </comment>
      </bits>
      <bits access="rw" name="rssi_tm_th" pos="5:0" rst="60">
        <comment>
          RSSI threshold
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="demod_smp_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="ini_rst_th" pos="15:10" rst="1">
        <comment>
          Count sample threshold reset for demod.
        </comment>
      </bits>
      <bits access="rw" name="ref_ready_th" pos="9:4" rst="0">
        <comment>
          GFSK iph th reference for demod.
        </comment>
      </bits>
      <bits access="rw" name="cnt_sample_ini" pos="3:0" rst="5">
        <comment>
          Sample point initial value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="mix_guard_th" pos="15:10" rst="1">
        <comment>
          Guard time length threshold for demod
        </comment>
      </bits>
      <bits access="rw" name="dpsk_seek_st_cnt" pos="9:5" rst="10">
        <comment>
          DPSK Seek Start Count
        </comment>
      </bits>
      <bits access="rw" name="agc_en_fix7" pos="4" rst="1">
        <comment>
          Fix7 enable during demod
1'h0:: Disable
1'h1:: Enable
        </comment>
      </bits>
      <bits access="rw" name="agc_mod_fix7" pos="3" rst="0">
        <comment>
          Fix7 mode select during bt dsp demod
1'h0:: threshold_2
1'h1:: threshold_3
        </comment>
      </bits>
      <bits access="rw" name="agc_sinc_over_en" pos="2" rst="0">
        <comment>
          Rounding enable after sinc.
1'h0:: Disable
1'h1:: Enable
        </comment>
      </bits>
      <bits access="rw" name="agc_sinc_over_th" pos="1:0" rst="1">
        <comment>
          Threshold of Rounding after sinc.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_th_ctrl1">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="agc_th_max" pos="15:8" rst="96">
        <comment>
          AGC maximum threshold for demod
        </comment>
      </bits>
      <bits access="rw" name="agc_th_min" pos="7:0" rst="24">
        <comment>
          AGC minimum threshold for demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_th_ctrl2">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="agc_th_max_lg" pos="15:8" rst="220">
        <comment>
          AGC maximum large threshold for demod
        </comment>
      </bits>
      <bits access="rw" name="agc_th_min_lg" pos="7:0" rst="40">
        <comment>
          AGC minimum large threshold for demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_ctrl1">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="agc_ctrl1_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="agc_ct_th_min" pos="14" rst="0">
        <comment>
          AGC minimum threshold for demod
        </comment>
      </bits>
      <bits access="rw" name="agc_en_lg_stp" pos="13" rst="1">
        <comment>
          AGC logarithmic step enable for demod
1'h0:: Disable
1'h1:: Enable
        </comment>
      </bits>
      <bits access="rw" name="agc_step_mode" pos="12:11" rst="1">
        <comment>
          AGC step mode for demod
2'b00:: AGC_step_1
2'b01:: AGC_step_2
2'b10:: AGC_step_3
2'b11:: AGC_step_4
        </comment>
      </bits>
      <bits access="rw" name="agc_step_over" pos="10:9" rst="2">
        <comment>
          AGC step over
        </comment>
      </bits>
      <bits access="rw" name="agc_en_dly" pos="8:6" rst="6">
        <comment>
          Delay timer count enable
3'b000:: Delay_0us
3'b001:: Delay_0p5us
3'b010:: Delay_1us
3'b011:: Delay_2us
3'b100:: Delay_3us
3'b101:: Delay_4us
3'b110:: Delay_6us
3'b111:: Delay_8us
        </comment>
      </bits>
      <bits access="rw" name="agc_index_ini_dsp" pos="5:2" rst="13">
        <comment>
          AGC gain index initial value for bt dsp
        </comment>
      </bits>
      <bits access="rw" name="agc_mod_dem" pos="1:0" rst="3">
        <comment>
          Demod mode select
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_ctrl2">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="agc_th_min_gn" pos="15:14" rst="1">
        <comment>
          AGC minimum threshold gain select for demod
2'b00:: Gain_2
2'b01:: Gain_4
2'b10:: Gain_8
2'b11:: Gain_16

        </comment>
      </bits>
      <bits access="rw" name="agc_tm_intv" pos="13:7" rst="24">
        <comment>
          AGCtm_intv_int initial value for demod
        </comment>
      </bits>
      <bits access="rw" name="agc_tm_intv_lg" pos="6:0" rst="48">
        <comment>
          AGC tm_intv_int logarithmic initial value for demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_dgc_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="rw" name="sel_reg_agc" pos="15" rst="1">
        <comment>
          AGC index select
1'h0:: dgc_index_dsp
1'h1:: dgc_index_mx
        </comment>
      </bits>
      <bits access="rw" name="dgc_index_dsp" pos="14:12" rst="0">
        <comment>
          DGC gain index
        </comment>
      </bits>
      <bits access="rw" name="dgc_index_max" pos="11:9" rst="4">
        <comment>
          Maximum agc gain index
        </comment>
      </bits>
      <bits access="rw" name="pass_newpacket_sel" pos="8" rst="0">
        <comment>
          Newpacket select for demod
1'h0 If newpacket from BB has one zero byte, select GID for demod, else select newpacket from BB
1'h1 Select newpacket from BB
        </comment>
      </bits>
      <bits access="rw" name="newpacket_zero_wd_cnt" pos="7:6" rst="0">
        <comment>
          Newpacket zero bytes number
2'b00 If the 1st  byte of newpacket  is zero, 
newpacket_bb_sel is logic high, else low
2'b01 If the 1st &amp; 2nd  byte of newpacket  is zero, 
newpacket_bb_sel is logic high, else low
2'b10 If the 1st &amp; 2nd &amp; 3rd byte of newpacket  is zero,
newpacket_bb_sel is logic high, else low
2'b11 If the 1st &amp; 2nd &amp; 3rd &amp;4th byte of newpacket  is zero, newpacket_bb_sel is logic high, else low
        </comment>
      </bits>
      <bits access="r" name="agc_dgc_ctrl_reserved_0" pos="5:3" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="agc_mode_dsp" pos="2:0" rst="4">
        <comment>
          AGC mode for dsp
3'h0:: Normal
3'h1:: RESERVED
3'h2:: Hold_after_timer
3'h3:: fix_to_index_ini
3'h4:: Hold_by_FSM
3'h5:: Th_large_mode: select by FSM
others RESERVED
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_dccal_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="rw" name="agc_tm_wait" pos="15:11" rst="7">
        <comment>
          AGC hold waiting time length
        </comment>
      </bits>
      <bits access="rw" name="agc_tm_hold" pos="10:6" rst="10">
        <comment>
          AGC hold time length
        </comment>
      </bits>
      <bits access="r" name="agc_dccal_ctrl_reserved_0" pos="5:4" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="rx_dc_cal_done" pos="3" rst="0">
        <comment>
          RX DC Calibration Done
        </comment>
      </bits>
      <bits access="rw" name="dc_cal_rx_dly" pos="2:1" rst="1">
        <comment>
          RX DC Calibration Delay for 1 loop
2'h0:: 0p6ms
2'h1:: 1p2ms
2'h2:: 2p4ms
2'h3:: 4p8ms
        </comment>
      </bits>
      <bits access="rw" name="rx_fix_dcofst" pos="0" rst="0">
        <comment>
          DC offset fix select for rx
1'h0:: by_calib: DC offset data set by calibration
1'h1:: by_reg: DC offset data set by register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rx_dccal_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="rx_dc_cali_i_fix" pos="15:8" rst="0">
        <comment>
          RX DC fixed offset data for I path when if_fix_dcofst is 1; otherwise use the auto calc values.
        </comment>
      </bits>
      <bits access="rw" name="rx_dc_cali_q_fix" pos="7:0" rst="0">
        <comment>
          RX DC fixed offset data for Q path when if_fix_dcofst is 1; otherwise use the auto calc values.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rx_dcofst_inuse">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="r" name="rx_dcoffset_i" pos="15:8" rst="0">
        <comment>
          rx dc offset for dc calibration; selected from dc_cali_i_fix &amp; dc_i2d_work_i
        </comment>
      </bits>
      <bits access="r" name="rx_dcoffset_q" pos="7:0" rst="0">
        <comment>
          rx dc offset for dc calibration; selected from dc_cali_q_fix &amp; dc_i2d_work_q
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_dc_calib">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_dc_cal_done" pos="15" rst="0">
        <comment>
          TX Calibration Done
        </comment>
      </bits>
      <bits access="r" name="tx_dc_calib_reserved_0" pos="14:13" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="tx_fix_dcofst" pos="12" rst="0">
        <comment>
          Fix TX DC Offset
        </comment>
      </bits>
      <bits access="rw" name="tx_cal_cnt" pos="11:10" rst="2">
        <comment>
          TX Calibration Step Counters for 25KHz
2'b00:: 0p125_range
2'b01:: 0p25_range
2'b10:: 0p5_range
2'b11:: full_range
        </comment>
      </bits>
      <bits access="rw" name="tx_cal_cmp_pol" pos="9" rst="0">
        <comment>
          TX Calibration Comparison Polarity
        </comment>
      </bits>
      <bits access="rw" name="tx_cal_pol" pos="8" rst="1">
        <comment>
          TX Calibration Offset Polarity
0:: no_switch: the polarity of TX calibration offset
1:: switch: the polarity of TX calibration offset
        </comment>
      </bits>
      <bits access="rw" name="tx_cal_sel" pos="7:6" rst="0">
        <comment>
          TX Calibration Selection
2'b00:: mean: (tx_cal1 + tx_cal2)/2
2'b01:: tx_cal1
2'b10:: tx_cal2
        </comment>
      </bits>
      <bits access="rw" name="tx_cal_shift" pos="5:4" rst="2">
        <comment>
          TX Calibration Offset Shift
2'b00:: x4: left shift by 2 bits
2'b01:: x2: left shift by 1 bit
2'b10:: x1: no shift
        </comment>
      </bits>
      <bits access="rw" name="tx_apc" pos="3:1" rst="7">
        <comment>
          TX Gain Table Pointer during work
        </comment>
      </bits>
      <bits access="rw" name="bypass_tx_cal" pos="0" rst="0">
        <comment>
          Bypass TX Calibration Offset
1'b0:: not_bypass
1'b1:: bypass
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_fix_i_dcofst">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_fix_i_dcofst_reserved_0" pos="15:12" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="tx_dc_idata_fix" pos="11:0" rst="0">
        <comment>
          Fixed TX I Signed Data for DC offset
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_fix_q_dcofst">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_fix_q_dcofst_reserved_0" pos="15:12" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="tx_dc_qdata_fix" pos="11:0" rst="0">
        <comment>
          TX Q Signed Data for DC offset
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="tx_i_dcofst_inuse">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_i_dcofst_inuse_reserved_0" pos="15:12" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="dc_cal_tx_idata" pos="11:0" rst="0">
        <comment>
          TX I Signed Data offset in use
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="tx_q_dcofst_inuse">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_q_dcofst_inuse_reserved_0" pos="15:12" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="dc_cal_tx_qdata" pos="11:0" rst="0">
        <comment>
          TX Q Signed Data offset in use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl1">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl1_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0000" pos="14:8" rst="9">
        <comment>
          RSSI gain 0000
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl1_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0001" pos="6:0" rst="19">
        <comment>
          ARSSI gain 0001
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl2">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl2_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0010" pos="14:8" rst="27">
        <comment>
          RSSI gain 0010
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl2_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0011" pos="6:0" rst="35">
        <comment>
          ARSSI gain 0011
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl3">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl3_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0100" pos="14:8" rst="41">
        <comment>
          RSSI gain 0100
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl3_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0101" pos="6:0" rst="49">
        <comment>
          ARSSI gain 0101
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl4">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl4_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0110" pos="14:8" rst="55">
        <comment>
          RSSI gain 0110
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl4_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain0111" pos="6:0" rst="63">
        <comment>
          ARSSI gain 0111
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl5">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl5_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1000" pos="14:8" rst="9">
        <comment>
          RSSI gain 1000
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl5_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1001" pos="6:0" rst="19">
        <comment>
          ARSSI gain 1001
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl6">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl6_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1010" pos="14:8" rst="27">
        <comment>
          RSSI gain 1010
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl6_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1011" pos="6:0" rst="35">
        <comment>
          ARSSI gain 1011
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl7">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl7_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1100" pos="14:8" rst="41">
        <comment>
          RSSI gain 1100
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl7_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1101" pos="6:0" rst="49">
        <comment>
          ARSSI gain 1101
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rssi_gain_ctrl8">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_gain_ctrl8_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1110" pos="14:8" rst="55">
        <comment>
          RSSI gain 1110
        </comment>
      </bits>
      <bits access="r" name="rssi_gain_ctrl8_reserved_1" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="rssi_ana_gain1111" pos="6:0" rst="63">
        <comment>
          ARSSI gain 1111
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="modem_tpd_sel">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="modem_tpd_sel_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dac_clk_force_en" pos="9" rst="0">
        <comment>
          DAC Clock Force Enable while rx data to dac
        </comment>
      </bits>
      <bits access="rw" name="tpd_clk_sel" pos="8" rst="0">
        <comment>
          Test Ports Clock Select
0:: clk_rx
1:: clk_tx 
        </comment>
      </bits>
      <bits access="rw" name="tpd_data_sel" pos="7:4" rst="0">
        <comment>
          Test Ports Data Select
4'h0::  dac_data_i
4'h1::  dac_data_q
4'h2::  dout_tx_i_sum
4'h3::  dout_tx_q_sum
4'h4::  dout_tx_dac_i: depends on dac_data_sel
4'h5::  dout_tx_dac_q
4'h6::  dout_rx_dac_i
4'h7::  dout_rx_dac_q
4'h8::  dout_tx_dac_i_13m: by en_tx_13m
4'h9::  dout_tx_dac_q_13m: by en_tx_13m
4'ha::  dout_rx_dac_i_13m: by en_rx_13m
4'hb::  dout_rx_dac_q_13m: by en_rx_13m
4'hc::  dout_rx_dac_i_14m: by en_rx_14m
4'hd::  dout_rx_dac_q_14m: by en_rx_14m
4'he::  dout_tx_dac_i_26m: by en_tx_26m
4'hf::  dout_tx_dac_q_26m: by en_tx_26m
        </comment>
      </bits>
      <bits access="rw" name="tpd_trig_sel" pos="3:0" rst="0">
        <comment>
          Test Ports Trigger Select
4'h0::  dem_st_chg
4'h1::  agc_st_chg
4'h2::  agc_flg_dem
4'h3::  ble_access_rb
4'h4::  if_peak
4'h5::  if_seeked_all
4'h6::  seek_en
4'h7::  flg_getsymbol
4'h8::  tx_symbol_off_gfsk
4'h9::  tx_amp_sel
4'ha::  tx_flg_start
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="demod_smp_th_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="dem_sp_th2" pos="15:8" rst="162">
        <comment>
          Demod sample threshold2
        </comment>
      </bits>
      <bits access="rw" name="dem_sp_th1" pos="7:0" rst="64">
        <comment>
          Demod sample threshold1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="newpacket_byte4">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="newpacket_4" pos="15:0" rst="49152">
        <comment>
          The 4th byte newpacket for demod when sel_sync(register_41[13]) is 1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="newpacket_byte3">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="newpacket_3" pos="15:0" rst="26214">
        <comment>
          The 3rd byte newpacket for demod when sel_sync(register_41[13]) is 1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="newpacket_byte2">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="newpacket_2" pos="15:0" rst="13107">
        <comment>
          The 2nd byte newpacket for demod when sel_sync(register_41[13]) is 1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="newpacket_byte1">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="newpacket_1" pos="15:0" rst="21845">
        <comment>
          The 1st byte newpacket for demod when sel_sync(register_41[13]) is 1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_mod_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="rw" name="bt_mod" pos="15" rst="1">
        <comment>
          Bluetooth GFSK modulation filter select
        </comment>
      </bits>
      <bits access="rw" name="rssi_ct_u" pos="14:12" rst="4">
        <comment>
          RSSI gain control
        </comment>
      </bits>
      <bits access="r" name="gfsk_mod_ctrl_reserved_0" pos="11:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="ref_a2_dem" pos="9:0" rst="117">
        <comment>
          GFSK demod a2 reference for rx demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_mod_ref_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="ref_a1_dem" pos="15:8" rst="22">
        <comment>
          GFSK demod a1 reference for rx demod
        </comment>
      </bits>
      <bits access="rw" name="ref_a3_dem" pos="7:0" rst="22">
        <comment>
          GFSK demod a3 reference for rx demod
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sym_dly_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="sym_dly_ctrl_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="ramp_speed_gfsk" pos="13" rst="0">
        <comment>
          GFSK ramp speed select
1'h0:: Slow
1'h1:: Fast
        </comment>
      </bits>
      <bits access="rw" name="delay_gfsk_off" pos="12:9" rst="8">
        <comment>
          GFSK symbol end flag delay, with 13MHz clk step
        </comment>
      </bits>
      <bits access="rw" name="delay_gfsk_off_1m" pos="8:6" rst="4">
        <comment>
          GFSK symbol end flag delay, with 1MHz clk step
        </comment>
      </bits>
      <bits access="rw" name="delay_dpsk_1m" pos="5:3" rst="0">
        <comment>
          DPSK symbol delay, with 1MHz clk step
        </comment>
      </bits>
      <bits access="rw" name="delay_gfsk_1m" pos="2:0" rst="0">
        <comment>
          GFSK symbol delay, with 1MHz clk step
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_out2">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="rssi_out2_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="rssi_noise_out" pos="9:0" rst="0">
        <comment>
          RSSI noise out 
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="trx_clk_ctrl">
      <bits access="r" name="reserved_18" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_17" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="16" rst="0">
      </bits>
      <bits access="r" name="trx_clk_ctrl_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="swch_clk_52m_rx" pos="14" rst="0">
        <comment>
          Switch the clk edge to sample rf ADC data
1'h0:: negedge: to sample the RF ADC data
1'h1:: posedge: to sample the RF ADC data
        </comment>
      </bits>
      <bits access="rw" name="tx_rx_dir" pos="13" rst="0">
        <comment>
          TX/RX direction
1'h0:: by_hw: TX/RX flag setting by deleying resetn_dsp_tx
1'h1:: by_reg: TX/RX flag setting by register
        </comment>
      </bits>
      <bits access="rw" name="tx_rx_reg" pos="12" rst="0">
        <comment>
          TX/RX flag
1'h0:: RX
1'h1:: TX
        </comment>
      </bits>
      <bits access="r" name="trx_clk_ctrl_reserved_1" pos="11:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="apc_switch_mode" pos="9:6" rst="3">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="r" name="trx_clk_ctrl_reserved_2" pos="5:0" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="iq_swap_ctrl">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="rw" name="swch_clk_52m_tx" pos="15" rst="1">
        <comment>
          TX link 52M clk edge switch
1'h0:: Not_Switch
1'h1:: Switch
        </comment>
      </bits>
      <bits access="rw" name="iq_swap_gain2" pos="14" rst="0">
        <comment>
          Digital gain2 output I/Q swap
1'h0:: Not_Swap
1'h1:: Swap
        </comment>
      </bits>
      <bits access="rw" name="iq_swap_lpf" pos="13" rst="0">
        <comment>
          Rate converter LPF filter output I/Q swap
1'h0:: Not_Swap
1'h1:: Swap
        </comment>
      </bits>
      <bits access="rw" name="iq_swap_srrc" pos="12" rst="0">
        <comment>
          SRRC filter output I/Q swap
1'h0:: Not_Swap
1'h1:: Swap
        </comment>
      </bits>
      <bits access="r" name="iq_swap_ctrl_reserved_0" pos="11:7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="lpf_en_1" pos="6" rst="1">
        <comment>
          Low Pass Filter Enable in Channel Group1
1'h0:: bypass
1'h1:: enable
        </comment>
      </bits>
      <bits access="rw" name="rate_conv_en_1" pos="5" rst="1">
        <comment>
          Rate Converter Enable in Channel Group1
1'h0:: bypass
1'h1:: enable
        </comment>
      </bits>
      <bits access="rw" name="notch_en_1" pos="4" rst="1">
        <comment>
          Notch Filter Enable in Channel Group1
1'h0:: bypass
1'h1:: enable
        </comment>
      </bits>
      <bits access="r" name="iq_swap_ctrl_reserved_1" pos="3" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="lpf_en_0" pos="2" rst="1">
        <comment>
          Low Pass Filter Enable in Channel Group0
1'h0:: bypass
1'h1:: enable
        </comment>
      </bits>
      <bits access="rw" name="rate_conv_en_0" pos="1" rst="0">
        <comment>
          Rate Converter Enable in Channel Group0
1'h0:: bypass
1'h1:: enable
        </comment>
      </bits>
      <bits access="rw" name="notch_en_0" pos="0" rst="0">
        <comment>
          Notch Filter Enable in Channel Group0
1'h0:: bypass
1'h1:: enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_sync_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="gfsk_sync_ctrl_reserved_0" pos="15:11" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dynamic_sync_en" pos="10" rst="0">
        <comment>
          Dynamic sync enable for demod of rx link
1'h0:: static
1'h1:: Dynamic
        </comment>
      </bits>
      <bits access="rw" name="dynamic_sync_th" pos="9:0" rst="0">
        <comment>
          Dynamic sync threshold
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_demod_ctrl">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="min_error_th2" pos="15:0" rst="0">
        <comment>
          The 2nd minimum sync phase error threshold
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_mod_idx">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="h_gain" pos="15:0" rst="12704">
        <comment>
          GFSK modulation index
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dpsk_gfsk_misc_ctrl">
      <bits access="r" name="reserved_17" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="16" rst="0">
      </bits>
      <bits access="rw" name="iq_swap_tx" pos="15" rst="0">
        <comment>
          Tx link IQ swap
1'h0:: Not_swap
1'h1:: Swap
        </comment>
      </bits>
      <bits access="r" name="dpsk_gfsk_misc_ctrl_reserved_0" pos="14:12" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_gfsk" pos="11:9" rst="6">
        <comment>
          GFSK delay after gfsk modulation
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_dpsk" pos="8:6" rst="0">
        <comment>
          DPSK delay after dpsk modulation
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_amp" pos="5:3" rst="3">
        <comment>
          DPSK amplitude delay after dpsk modulation
        </comment>
      </bits>
      <bits access="r" name="dpsk_gfsk_misc_ctrl_reserved_1" pos="2:0" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="modem_dbm_sel">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="modem_dbm_sel_reserved_0" pos="15:5" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dbm_data_sel" pos="4:0" rst="0">
        <comment>
          Debug Master Data Select
5'h0::  gfilter_tx_dout
5'h1::  symbol2iq_tx_dout_q: symbol2iq_tx_dout_i
5'h2::  cordic_tx_amp_dout: cordic_tx_angle_dout
5'h3::  ampm_tx_dout_am: ampm_tx_dout_pm
5'h4::  diff_tx_dout
5'h5::  freq_blend_tx_dout
5'h6::  intigrate_tx_dout
5'h7::  cordic_iq_tx_dout_q: cordic_iq_tx_dout_i
5'h8::  dout_tx_13m_q: dout_tx_13m_i
5'h9::  iqim_cancel_dout_q: iqim_cancel_dout_i
5'ha::  dout_tx_26m_q: dout_tx_26m_i
5'hb::  dout_tx_52m_q: dout_tx_52m_i
5'hc:: dac_grp_bit_q_outp: dac_grp_bit_i_outp
5'h10:: adc_data_q: adc_data_i
5'h11:: adc_din_q: adc_din_i
5'h12:: lpf_q: lpf_i
5'h13:: rateconv_q: rateconv_i
5'h14:: calib_q: calib_i
5'h15:: dc_calib_q: dc_calib_i
5'h16:: cancel_flt_i: cancel_flt_q
5'h17:: notch_q: notch_i
5'h18:: gain_q: gain_i
5'h19:: ble_mux_q: ble_mux_i
5'h1a:: mixer_q: mixer_i
5'h1b:: srrc_q: srrc_i
5'h1c:: rssi_out
5'h1d:: angle_rc: angle
5'h1e:: angle_offset1: angle_offset
5'h1f:: err_dpsk: err_gfsk
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_mod_idx_le">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="h_gain_le" pos="15:0" rst="20165">
        <comment>
          GFSK modulation index for BLE mode
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="newpacket_byte4_inuse">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="r" name="newpacket_dsp4" pos="15:0" rst="32368">
        <comment>
          newpacket byte 4 inuse; selected from newpacket_reg, GID &amp; newpacket_bb
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="newpacket_byte3_inuse">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="r" name="newpacket_dsp3" pos="15:0" rst="16867">
        <comment>
          newpacket byte 3 inuse; selected from newpacket_reg, GID &amp; newpacket_bb
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="newpacket_byte2_inuse">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="r" name="newpacket_dsp2" pos="15:0" rst="16384">
        <comment>
          newpacket byte 2 inuse; selected from newpacket_reg, GID &amp; newpacket_bb
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="newpacket_byte1_inuse">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="r" name="newpacket_dsp1" pos="15:0" rst="13">
        <comment>
          newpacket byte 1 inuse; selected from newpacket_reg, GID &amp; newpacket_bb
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="le_mode_ctrl1">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="ref_a1_sek_le" pos="15:8" rst="40">
        <comment>
          ??
        </comment>
      </bits>
      <bits access="rw" name="ref_a1_dem_le" pos="7:0" rst="35">
        <comment>
          ??
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="le_mode_ctrl2">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="ref_a2_sek_le" pos="15:8" rst="176">
        <comment>
          ??
        </comment>
      </bits>
      <bits access="rw" name="ref_a2_dem_le" pos="7:0" rst="186">
        <comment>
          ??
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="le_mode_ctrl3">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="ref_a3_sek_le" pos="15:8" rst="40">
        <comment>
          ??
        </comment>
      </bits>
      <bits access="rw" name="ref_a3_dem_le" pos="7:0" rst="35">
        <comment>
          ??
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="le_mode_ctrl4">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="min_error_th_le" pos="15:0" rst="2334">
        <comment>
          ??
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="le_mode_ctrl5">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="rsvd5" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="ref_point_sel_le" pos="13:12" rst="2">
        <comment>
          ??
        </comment>
      </bits>
      <bits access="rw" name="mix_guard_th_le" pos="11:6" rst="4">
        <comment>
          ??
        </comment>
      </bits>
      <bits access="rw" name="ref_ready_th_le" pos="5:0" rst="3">
        <comment>
          ??
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rf_ctrl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="rf_ctrl_reserved_0" pos="15:1" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="sync_shift_mode" pos="0" rst="0">
        <comment>
          ??
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_q_im">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_q_im_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="tx_iqim_phase_err" pos="14:0" rst="0">
        <comment>
          Error on Q to reduce IQ mismatch Image
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_i_im">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_i_im_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="tx_iqim_amp_err" pos="14:0" rst="0">
        <comment>
          Error on I to reduce IQ mismatch Image
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p0">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p0_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_shift" pos="14:12" rst="0">
        <comment>
          PM Compensation Shift
        </comment>
      </bits>
      <bits access="rw" name="pm_comp_bypass" pos="11" rst="1">
        <comment>
          PM Compensation Bypass
1'b0:: enable
1'b1:: bypass
        </comment>
      </bits>
      <bits access="rw" name="am_comp_bypass" pos="10" rst="1">
        <comment>
          AM Compensation Bypass
1'b0:: enable
1'b1:: bypass
        </comment>
      </bits>
      <bits access="rw" name="am_p0" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p1">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p1_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p1" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p2">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p2_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p2" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p3">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p3_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p3" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p4">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p4_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p4" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p5">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p5_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p5" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p6">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p6_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p6" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p7">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p7_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p7" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p8">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p8_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p8" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p9">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p9_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p9" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p10">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p10_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p10" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p11">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p11_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p11" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p12">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p12_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p12" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef12
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p13">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p13_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p13" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef13
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p14">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p14_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p14" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef14
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p15">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p15_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p15" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef15
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_am_p16">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_am_p16_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="am_p16" pos="9:0" rst="0">
        <comment>
          AMAM Compensation Coef16
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p0">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p0_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p0" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p1">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p1_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p1" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p2">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p2_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p2" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p3">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p3_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p3" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p4">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p4_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p4" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p5">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p5_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p5" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p6">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p6_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p6" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p7">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p7_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p7" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p8">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p8_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p8" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p9">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p9_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p9" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p10">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p10_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p10" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p11">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p11_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p11" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p12">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p12_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p12" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef12
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p13">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p13_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p13" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef13
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p14">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p14_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p14" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef14
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p15">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p15_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p15" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef15
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_pm_p16">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_pm_p16_reserved_0" pos="15:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="pm_p16" pos="9:0" rst="0">
        <comment>
          AMPM Compensation Coef16
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="notch_coef">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="notch_coef_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="notch_b" pos="13:0" rst="15347">
        <comment>
          Notch Filter Coefficient B
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="adapt_edr3_demod">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="rw" name="notch_a" pos="15:12" rst="14">
        <comment>
          Notch Filter Coefficient A
        </comment>
      </bits>
      <bits access="r" name="adapt_edr3_demod_reserved_0" pos="11:10" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="edr3_adapt_en" pos="9" rst="0">
        <comment>
          EDR3 Adapt Demodulation Enable
1'b0:: disable
1'b1:: enable
        </comment>
      </bits>
      <bits access="rw" name="ct_u_dpsk1" pos="8:5" rst="2">
        <comment>
          second u_err of the dpsk 2/32
        </comment>
      </bits>
      <bits access="rw" name="ct_u_1_dpsk1" pos="4:0" rst="26">
        <comment>
          second u_dc of the dpsk 2/512
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="adapt_edr3_thresh">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="adapt_edr3_thresh_reserved_0" pos="15:12" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="edr3_adapt_th" pos="11:0" rst="819">
        <comment>
          EDR3 Adapt Demodulation Threshold
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_auto_gain1_gfsk">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk7" pos="15:12" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h7
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk6" pos="11:8" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h6
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk5" pos="7:4" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h5
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk4" pos="3:0" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_auto_gain0_gfsk">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk3" pos="15:12" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h3
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk2" pos="11:8" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h2
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk1" pos="7:4" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h1
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk0" pos="3:0" rst="9">
        <comment>
          auto gfsk digital gain high 4bits. Tx_power=3'h0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_auto_gain1_gfsk_edr">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr7" pos="15:12" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h7
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr6" pos="11:8" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h6
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr5" pos="7:4" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h5
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr4" pos="3:0" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_auto_gain0_gfsk_edr">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr3" pos="15:12" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h3
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr2" pos="11:8" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h2
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr1" pos="7:4" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h1
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_gfsk_edr0" pos="3:0" rst="7">
        <comment>
          auto gfsk edr digital gain high 4bits. Tx_power=3'h0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_auto_gain1_dpsk">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk7" pos="15:12" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h7
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk6" pos="11:8" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h6
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk5" pos="7:4" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h5
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk4" pos="3:0" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_auto_gain0_dpsk">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk3" pos="15:12" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h3
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk2" pos="11:8" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h2
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk1" pos="7:4" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h1
        </comment>
      </bits>
      <bits access="rw" name="tx_auto_gain_dpsk0" pos="3:0" rst="13">
        <comment>
          auto dpsk digital gain high 4bits. Tx_power=3'h0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="gfsk_mod_eql_gain">
      <bits access="r" name="reserved_15" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="16" rst="0">
      </bits>
      <bits access="rw" name="equ_g_gfsk" pos="15:0" rst="807">
        <comment>
          GFSK modulation equalization gain
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_lfp_delay_ctrl">
      <bits access="r" name="reserved_18" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_17" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_lfp_delay_ctrl_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_freq2" pos="14:12" rst="4">
        <comment>
          Phase path delay number 2, with 26MHz clk step
        </comment>
      </bits>
      <bits access="r" name="tx_lfp_delay_ctrl_reserved_1" pos="11" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_freq1" pos="10:8" rst="4">
        <comment>
          Phase path delay number 1, with 26MHz clk step
        </comment>
      </bits>
      <bits access="r" name="tx_lfp_delay_ctrl_reserved_2" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="lpfil_freq_tx_bypass" pos="6" rst="0">
        <comment>
          GFSK Low pass filter bypass
1'h0 Not bypass
1'h1 bypass
Note:
IQ Tx mode: register_c9[5:4]=00
Polar Loop &amp; IQ Tx mode: register_c9[5:4]=01
All Polar Loop Tx mode: register_c9[5:4]=11
        </comment>
      </bits>
      <bits access="rw" name="lpfil_freq_tx_enable" pos="5" rst="0">
        <comment>
          GFSK low pass filter enable
1'h0  Enable LPFil, output low pass gfsk signal
1'h1, Disable LPFil, output is zero
        </comment>
      </bits>
      <bits access="rw" name="lpfil_freq_tx_bw_ct" pos="4:0" rst="8">
        <comment>
          GFSK low pass filter pass band width select
1:: lpfil_freq_tx_bw_ct[4]=0
BW = 100K + lpfil_freq_tx_bw_ct* 20
2:: lpfil_freq_tx_bw_ct[4]=1
BW = 50K
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_hfp_delay">
      <bits access="r" name="reserved_19" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_18" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_17" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_hfp_delay_reserved_0" pos="15" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dly_sel_freq" pos="14:12" rst="2">
        <comment>
          Delay of the gfsk and dpsk mixed phase
        </comment>
      </bits>
      <bits access="r" name="tx_hfp_delay_reserved_1" pos="11" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_iq1" pos="10:8" rst="4">
        <comment>
          I/Q path delay number 1, with 26MHz clk step
        </comment>
      </bits>
      <bits access="r" name="tx_hfp_delay_reserved_2" pos="7" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_iq2" pos="6:4" rst="4">
        <comment>
          I/Q path delay number 2, with 26MHz clk step
        </comment>
      </bits>
      <bits access="r" name="tx_hfp_delay_reserved_3" pos="3" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="dly_ct_freq_high" pos="2:0" rst="2">
        <comment>
          High frequency path delay
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_polar_mode_ctl">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_polar_mode_ctl_reserved_0" pos="15:5" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="tx_tmp_dly" pos="4:2" rst="2">
        <comment>
          amp tmp delay
        </comment>
      </bits>
      <bits access="rw" name="tx_polar_mode_sel" pos="1" rst="1">
        <comment>
          tx polar modulation mode selected
1'b0::phase mode
1'b1::frequency mode
        </comment>
      </bits>
      <bits access="rw" name="tx_apf_bypass" pos="0" rst="1">
        <comment>
          tx polar modulation all pass filter bypass ctl
1'b1::bypass
1'b0::no bypass
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_apf_num_b1">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_apf_num_b1_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="num_coe_b1" pos="13:0" rst="12">
        <comment>
          tx polar modulation apf num coe-2.14
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_apf_num_b2">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_apf_num_b2_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="num_coe_b2" pos="13:0" rst="12">
        <comment>
          tx polar modulation apf num coe
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_apf_num_b3">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_apf_num_b3_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="num_coe_b3" pos="13:0" rst="12">
        <comment>
          tx polar modulation apf num coe
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_apf_num_b4">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_apf_num_b4_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="num_coe_b4" pos="13:0" rst="12">
        <comment>
          tx polar modulation apf num coe
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_apf_den_a2">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_apf_den_a2_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="den_coe_a2" pos="13:0" rst="12">
        <comment>
          tx polar modulation apf den coe-2.14
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_apf_den_a3">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_apf_den_a3_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="den_coe_a3" pos="13:0" rst="12">
        <comment>
          tx polar modulation apf den coe
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_apf_den_a4">
      <bits access="r" name="reserved_16" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="16" rst="0">
      </bits>
      <bits access="r" name="tx_apf_den_a4_reserved_0" pos="15:14" rst="0">
        <comment>
          RESERVED
        </comment>
      </bits>
      <bits access="rw" name="den_coe_a4" pos="13:0" rst="12">
        <comment>
          tx polar modulation apf den coe
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_pulp_debug_unit.xml">
  <module name="bt_pulp_debug_unit" category="WCN">
    <reg protect="rw" name="dbg_ctrl">
      <bits access="r" name="dbg_ctrl_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="rw" name="halt" pos="16" rst="0">
        <comment>
          when 1 written,core enters debug mode, when 0 written, core exits debug mode
when read, 1 means core is in debug mode
        </comment>
      </bits>
      <bits access="r" name="dbg_ctrl_reserved_1" pos="15:1" rst="0">
      </bits>
      <bits access="rw" name="sste" pos="0" rst="0">
        <comment>
          single step enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_hit">
      <bits access="r" name="dbg_hit_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="r" name="sleep" pos="16" rst="0">
        <comment>
          set when the core is a sleeping state and wait for an event
        </comment>
      </bits>
      <bits access="r" name="dbg_hit_reserved_1" pos="15:1" rst="0">
      </bits>
      <bits access="rw" name="ssth" pos="0" rst="0">
        <comment>
          single-step hit, sticky bit that must be cleared by external debugger
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_ie">
      <bits access="r" name="dbg_ie_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="ecall" pos="11" rst="0">
        <comment>
          environment call for M-mode
        </comment>
      </bits>
      <bits access="r" name="dbg_ie_reserved_1" pos="10:8" rst="0">
      </bits>
      <bits access="rw" name="saf" pos="7" rst="0">
        <comment>
          store access fault (together with laf)
        </comment>
      </bits>
      <bits access="rw" name="sam" pos="6" rst="0">
        <comment>
          store address Misaligned (never traps)
        </comment>
      </bits>
      <bits access="rw" name="laf" pos="5" rst="0">
        <comment>
          load access fault (together with saf)
        </comment>
      </bits>
      <bits access="rw" name="lam" pos="4" rst="0">
        <comment>
          load access Misaligned (never traps)
        </comment>
      </bits>
      <bits access="rw" name="bp" pos="3" rst="0">
        <comment>
          ebreak instruction causes trap
        </comment>
      </bits>
      <bits access="rw" name="ill" pos="2" rst="0">
        <comment>
          illegal instruction
        </comment>
      </bits>
      <bits access="rw" name="iaf" pos="1" rst="0">
        <comment>
          instruction access fault (not implemented)
        </comment>
      </bits>
      <bits access="rw" name="iam" pos="0" rst="0">
        <comment>
          instruction address misaligned (never traps)
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="dbg_cause">
      <bits access="r" name="irq" pos="31" rst="0">
        <comment>
          interrupt caused us to enter debug mode
        </comment>
      </bits>
      <bits access="r" name="dbg_cause_reserved_0" pos="30:5" rst="0">
        <comment>
          set when the core is a sleeping state and wait for an event
        </comment>
      </bits>
      <bits access="r" name="cause" pos="4:0" rst="0">
        <comment>
          exception/interrupt number
        </comment>
      </bits>
    </reg>
    <hole size="8064"/>
    <reg protect="rw" name="dbg_gpr0">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr1">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr2">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr3">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr4">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr5">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr6">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr7">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr8">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr9">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr10">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr11">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr12">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr13">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr14">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr15">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr16">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr17">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr18">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr19">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr20">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr21">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr22">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr23">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr24">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr25">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr26">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr27">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr28">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr29">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr30">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_gpr31">
      <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
        <comment>
          general purpose register
        </comment>
      </bits>
    </reg>
    <hole size="56320"/>
    <reg protect="rw" name="dbg_npc">
      <bits access="rw" name="npc" pos="31:0" rst="0">
        <comment>
          Next PC to be executed
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="dbg_ppc">
      <bits access="r" name="ppc" pos="31:0" rst="0">
        <comment>
          previous PC, already executed
        </comment>
      </bits>
    </reg>
    <hole size="90048"/>
    <reg protect="rw" name="dbg_mstatus">
      <bits access="r" name="dbg_mstatus_reserved_0" pos="31:3" rst="0">
      </bits>
      <bits access="r" name="prv" pos="2:1" rst="3">
        <comment>
          Statically 2'b11 and cannot be altered
        </comment>
      </bits>
      <bits access="rw" name="int_en" pos="0" rst="0">
        <comment>
          Interrupt enable:
When an exception is encountered, Interrupt Enable will be set to 1'h0.
When the eret instruction is executed, the original value of the Interrupt Enable will be restored, as MESTATUS will replace MSTATUS.
If you want to be enable interrupt handling in your exception handler, set the Interrupt Enable to 1'b1 inside your handler code.
        </comment>
      </bits>
    </reg>
    <hole size="2048"/>
    <reg protect="rw" name="dbg_mepc">
      <bits access="rw" name="mepc" pos="31:0" rst="0">
        <comment>
          When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. 
When an eret instruction is executed, the value from MEPC replaces the current program counter.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="dbg_mcause">
      <bits access="r" name="interrupt" pos="31" rst="0">
        <comment>
          this bit is  set when the exception was triggerd by an interrupt
        </comment>
      </bits>
      <bits access="r" name="dbg_mcause_reserved_0" pos="30:5" rst="0">
      </bits>
      <bits access="r" name="excp_code" pos="4:0" rst="0">
        <comment>
          exception code
        </comment>
      </bits>
    </reg>
    <hole size="36256"/>
    <reg protect="rw" name="dbg_loop_start0">
      <bits access="rw" name="lpstart0" pos="31:0" rst="0">
        <comment>
          hardware loop 0 start
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_loop_end0">
      <bits access="rw" name="lpend0" pos="31:0" rst="0">
        <comment>
          hardware loop 0 end
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_loop_cnt0">
      <bits access="rw" name="lpcount0" pos="31:0" rst="0">
        <comment>
          hardware loop 0 counter
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="dbg_loop_start1">
      <bits access="rw" name="lpstart1" pos="31:0" rst="0">
        <comment>
          hardware loop 1 start
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_loop_end1">
      <bits access="rw" name="lpend1" pos="31:0" rst="0">
        <comment>
          hardware loop 1 end
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dbg_loop_cnt1">
      <bits access="rw" name="lpcount1" pos="31:0" rst="0">
        <comment>
          hardware loop 1 counter
        </comment>
      </bits>
    </reg>
    <hole size="288"/>
    <reg protect="rw" name="dbg_mestatus">
      <bits access="r" name="dbg_mestatus_reserved_0" pos="31:3" rst="0">
      </bits>
      <bits access="r" name="prv" pos="2:1" rst="3">
        <comment>
          Statically 2'b11 and cannot be altered
        </comment>
      </bits>
      <bits access="rw" name="int_en" pos="0" rst="0">
        <comment>
          Interrupt enable:
When an exception is encountered, the current value of MSTATUS is saved in MESTATUS.
When an eret instruction is executed, the value from MESTATUS replaces MSTATUS register.
        </comment>
      </bits>
    </reg>
    <hole size="59360"/>
    <reg protect="r" name="dbg_mcpuid">
      <bits access="r" name="base" pos="31:30" rst="0">
        <comment>
          read as 0, which means RV32I
        </comment>
      </bits>
      <bits access="r" name="dbg_mcpuid_reserved_0" pos="29:26" rst="0">
      </bits>
      <bits access="r" name="extension" pos="25:0" rst="8392960">
        <comment>
          RI5CY only supports the I and M extension, plus the RI5CY non-standard extensions. This means bits 8(I), 12(M) and 23(X) are 1, the rest is 0.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="dbg_mimpid">
      <bits access="r" name="implementation" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="source" pos="15:0" rst="32768">
      </bits>
    </reg>
    <hole size="448"/>
    <reg protect="r" name="dbg_hartid">
      <bits access="r" name="dbg_hartid_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="r" name="cluster_id" pos="10:5" rst="0">
        <comment>
          ID of the cluster
        </comment>
      </bits>
      <bits access="r" name="reserved_1" pos="4" rst="0">
      </bits>
      <bits access="r" name="core_id" pos="3:0" rst="0">
        <comment>
          ID of the within the cluster
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_pulp_irq.xml">
  <module name="bt_pulp_irq" category="WCN">
    <reg protect="rw" name="enable">
      <bits access="rw" name="enable" pos="31:0" rst="0">
        <comment>
          interrupt enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pending">
      <bits access="rw" name="pending" pos="31:0" rst="0">
        <comment>
          interrupt pending
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="set_pending">
      <bits access="rs" name="set_pending" pos="31:0" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          set interrupt pending
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clear_pending">
      <bits access="rc" name="clear_pending" pos="31:0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          clear interrupt pending
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_pulp_sleep.xml">
  <module name="bt_pulp_sleep" category="WCN">
    <reg protect="rw" name="sleep_ctrl">
      <bits access="rw" name="sleep_ctrl_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="rw" name="sleep_enable" pos="0" rst="0">
        <comment>
          Enable sleep
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="sleep_status">
      <bits access="r" name="sleep_status_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="r" name="sleep" pos="0" rst="0">
        <comment>
          sleep stauts
0: not_sleep
1: sleep
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_rf_if.xml">
  <module name="bt_rf_if" category="WCN">
    <reg protect="r" name="revision">
      <bits access="r" name="revision_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="r" name="revid" pos="3:0" rst="1">
        <comment>
          Revision ID.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_control">
      <bits access="r" name="sys_control_reserved_0" pos="31:9" rst="0">
      </bits>
      <bits access="rw" name="fm_adc_clk_mode" pos="8:7" rst="0">
        <comment>
          fm adc clock mode.
2'h0:: divider
divider of rfpll
2'h1:: aupll
43.008MHz
2'h2:: adpll
43.008MHz
        </comment>
      </bits>
      <bits access="rw" name="bt_hopping_en" pos="6" rst="1">
        <comment>
          enable bt hopping while channel is muliplier of 26MHz during rx procedure.
If this bit is set to 1'h1, rf_interface will change the ADC clock to 28MHz generated by adpll instead of 26MHz crystal clock to avoid the receiving interference caused by 26MHz adc clock.
        </comment>
      </bits>
      <bits access="rw" name="bt_tune_diff_en" pos="5" rst="1">
        <comment>
          enable BT ARFCN tune diff mode.
If this bit is set to 1'h1, rf_interface will redo the rx/tx procedure (including RFPLL calibration process) if ARFCN changes during one rx/tx procedure.
        </comment>
      </bits>
      <bits access="rw" name="clk_digital_enable_reg" pos="4" rst="0">
        <comment>
          enable all digital clock.
If this bit is set to 1'h1, all digital clocks including gating ones will be forcely on.
        </comment>
      </bits>
      <bits access="rw" name="rf_mode" pos="3:2" rst="0">
        <comment>
          RF mode.
2'h0:: BT
2'h1:: WIFI
2'h2:: FM
        </comment>
      </bits>
      <bits access="rw" name="chip_self_cal_enable" pos="1" rst="0">
        <comment>
          Chip self_cal enable.
Self cal process will be triggered at posedge of chip_self_cal_enable.
        </comment>
      </bits>
      <bits access="rw" name="soft_resetn" pos="0" rst="1">
        <comment>
          soft reset. Active low.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_control">
      <bits access="r" name="bt_control_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="rw" name="bt_ch_type" pos="7" rst="0">
        <comment>
          BT channel type.
1'h0:: normal
1'h1:: multiplier
Multiplier of 26MHz. _x000D_
        </comment>
      </bits>
      <bits access="rw" name="bt_arfcn" pos="6:0" rst="39">
        <comment>
          BT Channel number. _x000D_
7'h00 : Channel0 _x000D_
7'h4E : Channel78
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_control">
      <bits access="r" name="wf_control_reserved_0" pos="31:23" rst="0">
      </bits>
      <bits access="rw" name="wf_freq_direct" pos="22:6" rst="0">
        <comment>
          frequency direct reg. u7.10, unit is MHz
        </comment>
      </bits>
      <bits access="rw" name="wf_freq_mode" pos="5" rst="0">
      </bits>
      <bits access="rw" name="wf_chn" pos="4:1" rst="0">
        <comment>
          WIFI channel.
        </comment>
      </bits>
      <bits access="rw" name="wf_tune" pos="0" rst="0">
        <comment>
          Start tune.
WIFI will be started at the posedge of wf_tune.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="fm_control">
      <bits access="rw" name="fm_freq_direct" pos="31:16" rst="0">
        <comment>
          frequency direct reg. u6.10, unit is MHz
        </comment>
      </bits>
      <bits access="r" name="fm_control_reserved_0" pos="15" rst="0">
      </bits>
      <bits access="rw" name="fm_band_sel" pos="14:13" rst="2">
        <comment>
          FM band select.
2'h0:: 87_108MHz : (US/Europe)
2'h1:: 76_91MHz : (Japan)
2'h2:: 76_108MHz : (World Wide)
2'h3:: 65_76MHz : (East Europe)
        </comment>
      </bits>
      <bits access="rw" name="fm_freq_mode" pos="12" rst="0">
        <comment>
          FM freq mode.
1'h0:: channel
channel number mode. Channel Freq = 25KHz*fm_chan_reg + bottom freq
1'h1:: direct
direct mode. Channel Freq = bottom freq + fm_freq_direct
        </comment>
      </bits>
      <bits access="rw" name="fm_chan_reg" pos="11:1" rst="1028">
        <comment>
          FM channel.
        </comment>
      </bits>
      <bits access="rw" name="fm_tune" pos="0" rst="0">
        <comment>
          Start tune.
FM will be started at the posedge of fm_tune.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="inter_freq_setting">
      <bits access="r" name="inter_freq_setting_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="fm_imgrej" pos="27" rst="0">
        <comment>
          FM intermediate frequency mode.
1'h0:: positive
1'h1:: negtive
        </comment>
      </bits>
      <bits access="rw" name="fm_if" pos="26:16" rst="128">
        <comment>
          FM intermediate freqeuncy. u1.10. Unit is Mhz. Default is 125KHz. _x000D_
        </comment>
      </bits>
      <bits access="r" name="inter_freq_setting_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="bt_zif" pos="12" rst="0">
        <comment>
          enable zero intermediate frequency.
1'h0:: use_bt_freq
use intermediate frequency defined by bt_digital_lo_freq;
1'h1:: use_0hz
use 0Hz intermediate frequency.
        </comment>
      </bits>
      <bits access="rw" name="bt_imgrej" pos="11" rst="0">
        <comment>
          BT intermediate frequency mode.
1'h0:: positive
1'h1:: negtive
        </comment>
      </bits>
      <bits access="rw" name="bt_if" pos="10:0" rst="758">
        <comment>
          BT intermediate freqeuncy. u1.10. Unit is Mhz. Default is740KHz.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ldo_setting">
      <bits access="r" name="ldo_setting_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="rw" name="sel_bg" pos="1" rst="0">
      </bits>
      <bits access="rw" name="ivref_bit" pos="0" rst="1">
      </bits>
    </reg>
    <reg protect="rw" name="bt_lna_rmx_setting">
      <bits access="rw" name="bt_rmx_lo_vcom_bit" pos="31:30" rst="1">
      </bits>
      <bits access="rw" name="bt_balun_cap_bit_rx" pos="29:27" rst="0">
      </bits>
      <bits access="rw" name="bt_balun_cap_bit_tx" pos="26:24" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_reg_bit" pos="23:21" rst="4">
      </bits>
      <bits access="rw" name="bt_lna_reg_bypass" pos="20" rst="0">
      </bits>
      <bits access="r" name="bt_lna_rmx_setting_reserved_0" pos="19:17" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_vcas_bit" pos="16:15" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_selfbias_en" pos="14" rst="0">
      </bits>
      <bits access="r" name="bt_lna_rmx_setting_reserved_1" pos="13" rst="0">
      </bits>
      <bits access="rw" name="bt_rmx_i2i_ibit" pos="12:9" rst="4">
      </bits>
      <bits access="rw" name="bt_rmx_lo_ifvcom_sel" pos="8" rst="1">
      </bits>
      <bits access="r" name="bt_lna_rmx_setting_reserved_2" pos="7:4" rst="0">
      </bits>
      <bits access="rw" name="bt_rmx_reg_bit" pos="3:1" rst="4">
      </bits>
      <bits access="rw" name="bt_rmx_reg_bypass" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="fm_lna_rmx_rxflt_setting">
      <bits access="r" name="fm_lna_rmx_rxflt_setting_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="fm_lna_lv_mode" pos="17" rst="0">
      </bits>
      <bits access="rw" name="fm_lna_ibit" pos="16:14" rst="4">
      </bits>
      <bits access="rw" name="fm_lna_reg_bit" pos="13:11" rst="4">
      </bits>
      <bits access="rw" name="fm_lna_reg_bypass" pos="10" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_harm_rej_en" pos="9" rst="1">
      </bits>
      <bits access="rw" name="fm_rmx_lobias_bit" pos="8:7" rst="2">
      </bits>
      <bits access="rw" name="fm_rmx_reg_bit" pos="6:4" rst="4">
      </bits>
      <bits access="rw" name="fm_rmx_reg_bypass" pos="3" rst="0">
      </bits>
      <bits access="rw" name="fm_rxflt_op_ibit" pos="2:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="rxflt_setting">
      <bits access="r" name="rxflt_setting_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="rw" name="adc_reg_bypass" pos="19" rst="0">
      </bits>
      <bits access="rw" name="rxflt_rstn_dr" pos="18" rst="0">
      </bits>
      <bits access="rw" name="rxflt_rstn_reg" pos="17" rst="0">
      </bits>
      <bits access="rw" name="rxflt_mode_sel_dr" pos="16" rst="0">
      </bits>
      <bits access="rw" name="rxflt_mode_sel_reg" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="rxflt_bt_if_ctrl" pos="13:12" rst="2">
      </bits>
      <bits access="rw" name="rxflt_wf_if_ctrl" pos="11:10" rst="2">
      </bits>
      <bits access="rw" name="rxflt_fm_if_ctrl" pos="9:8" rst="2">
      </bits>
      <bits access="rw" name="rxflt_cap_bit" pos="7:4" rst="7">
      </bits>
      <bits access="rw" name="rxflt_op_drv_bit" pos="3:1" rst="0">
      </bits>
      <bits access="rw" name="rxflt_iqswap" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="adc_setting">
      <bits access="rw" name="adc_vcm_sel" pos="31:28" rst="9">
      </bits>
      <bits access="rw" name="adc_comp_power_bit" pos="27" rst="1">
      </bits>
      <bits access="rw" name="adc_clk_xtal_en_dr" pos="26" rst="0">
      </bits>
      <bits access="rw" name="adc_clk_xtal_en_reg" pos="25" rst="0">
      </bits>
      <bits access="rw" name="adc_clk_sel_dr" pos="24" rst="0">
      </bits>
      <bits access="rw" name="adc_clk_sel_reg" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="adc_clk_edge_sel" pos="21" rst="0">
      </bits>
      <bits access="rw" name="adc_clk_div2" pos="20" rst="1">
      </bits>
      <bits access="rw" name="adc_delay_bit" pos="19:14" rst="50">
      </bits>
      <bits access="rw" name="adc_vref_rbit" pos="13:12" rst="0">
      </bits>
      <bits access="rw" name="adc_vref_vbit" pos="11:10" rst="2">
      </bits>
      <bits access="rw" name="adc_clk_ducy_sel" pos="9:6" rst="0">
      </bits>
      <bits access="rw" name="adc_reg_ibit" pos="5:3" rst="0">
      </bits>
      <bits access="rw" name="adc_reg_rbit" pos="2:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bt_dac_setting">
      <bits access="r" name="bt_dac_setting_reserved_0" pos="31:6" rst="0">
      </bits>
      <bits access="rw" name="bt_dac_vlow_ctrl_bit" pos="5:3" rst="3">
      </bits>
      <bits access="rw" name="bt_dac_clk_edge" pos="2" rst="1">
      </bits>
      <bits access="rw" name="bt_dac_vtr_sel" pos="1" rst="0">
      </bits>
      <bits access="rw" name="bt_dac_vdd_sel" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bt_padrv_tmx_setting">
      <bits access="r" name="bt_padrv_tmx_setting_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_delay_padrv" pos="30:23" rst="30">
      </bits>
      <bits access="rw" name="bt_padrv_ibit" pos="22:17" rst="12">
      </bits>
      <bits access="r" name="bt_padrv_tmx_setting_reserved_1" pos="16:12" rst="0">
        <comment>
          bt_tmx_lobias
        </comment>
      </bits>
      <bits access="rw" name="bt_tmx_ibit" pos="11:10" rst="1">
      </bits>
      <bits access="r" name="bt_padrv_tmx_setting_reserved_2" pos="9:6" rst="0">
        <comment>
          bt_tmx_cap_bit
        </comment>
      </bits>
      <bits access="rw" name="bt_tmx_cal_clk_edge" pos="5" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_pll_test" pos="4" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_dac_mon_en" pos="3" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_reg_lodiv_bit" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="fm_dsp_setting">
      <bits access="r" name="fm_dsp_setting_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="rw" name="fm_dsp_resetn_delay" pos="3:2" rst="0">
      </bits>
      <bits access="rw" name="fm_dsp_resetn_dr" pos="1" rst="0">
      </bits>
      <bits access="rw" name="fm_dsp_resetn_reg" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="vco_setting">
      <bits access="r" name="vco_setting_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="rw" name="vco_reg_bypass" pos="9" rst="0">
      </bits>
      <bits access="rw" name="vco_buf_ibit" pos="8:5" rst="8">
      </bits>
      <bits access="rw" name="vco_buf_bias_bit" pos="4:3" rst="1">
      </bits>
      <bits access="rw" name="vco_div2_bias_bit" pos="2:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_setting0">
      <bits access="rw" name="rfpll_cp_r_bit_tx" pos="31:30" rst="1">
      </bits>
      <bits access="rw" name="rfpll_cp_r_bit_rx" pos="29:28" rst="1">
      </bits>
      <bits access="rw" name="rfpll_reg_peri_bit" pos="27:24" rst="0">
      </bits>
      <bits access="rw" name="rfpll_reg_peri_bypass" pos="23" rst="0">
      </bits>
      <bits access="rw" name="rfpll_reg_presc" pos="22:19" rst="8">
      </bits>
      <bits access="rw" name="reset_rfpll_lock_delay" pos="18:17" rst="0">
      </bits>
      <bits access="rw" name="rfpll_refmulti2_en" pos="16" rst="1">
      </bits>
      <bits access="rw" name="rfpll_bypass_notch" pos="15" rst="0">
      </bits>
      <bits access="rw" name="rfpll_peri_dvdd_r_bit" pos="14:11" rst="8">
      </bits>
      <bits access="rw" name="rfpll_div_fm_lo_clk_dr" pos="10" rst="0">
      </bits>
      <bits access="rw" name="rfpll_div_fm_lo_clk_reg" pos="9:6" rst="6">
      </bits>
      <bits access="rw" name="rfpll_div_fm_adc_clk_dr" pos="5" rst="0">
      </bits>
      <bits access="rw" name="rfpll_div_fm_adc_clk_reg" pos="4:0" rst="28">
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_setting1">
      <bits access="rw" name="mdll_div_rx" pos="31:28" rst="2">
      </bits>
      <bits access="rw" name="rfpll_lowpwr_mode" pos="27" rst="0">
      </bits>
      <bits access="rw" name="rfpll_lock_flag_duration" pos="26:25" rst="0">
      </bits>
      <bits access="rw" name="rfpll_gain_bit_rx" pos="24:22" rst="4">
      </bits>
      <bits access="rw" name="rfpll_cp_bit_rx" pos="21:16" rst="3">
      </bits>
      <bits access="rw" name="mdll_div_tx" pos="15:12" rst="2">
      </bits>
      <bits access="rw" name="rfpll_reg_presc_rc" pos="11:9" rst="4">
      </bits>
      <bits access="rw" name="rfpll_gain_bit_tx" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="rfpll_cp_bit_tx" pos="5:0" rst="3">
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_setting2">
      <bits access="rw" name="rfpll_r_bit_rx" pos="31:27" rst="12">
      </bits>
      <bits access="rw" name="rfpll_lpf_gain_rx" pos="26:22" rst="0">
      </bits>
      <bits access="rw" name="rfpll_pfd_res_bit_rx" pos="21:16" rst="0">
      </bits>
      <bits access="rw" name="rfpll_r_bit_tx" pos="15:11" rst="12">
      </bits>
      <bits access="rw" name="rfpll_lpf_gain_tx" pos="10:6" rst="0">
      </bits>
      <bits access="rw" name="rfpll_pfd_res_bit_tx" pos="5:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_status">
      <bits access="r" name="rfpll_status_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="rw" name="rfpll_ref_mode_tx" pos="3" rst="1">
      </bits>
      <bits access="rw" name="rfpll_ref_mode_rx" pos="2" rst="1">
      </bits>
      <bits access="r" name="rfpll_lock_flag" pos="1" rst="0">
      </bits>
      <bits access="r" name="rfpll_lock_det" pos="0" rst="0">
        <comment>
          Indicate if rfpll in lock state.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="adpll_setting0">
      <bits access="rw" name="adpll_band_sel" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="adpll_lock_flag_duration" pos="29:28" rst="0">
      </bits>
      <bits access="rw" name="adpll_testsig_sel" pos="27:26" rst="0">
      </bits>
      <bits access="rw" name="adpll_vco_high_test" pos="25" rst="0">
      </bits>
      <bits access="rw" name="adpll_vco_low_test" pos="24" rst="0">
      </bits>
      <bits access="rw" name="reset_adpll_lock_delay" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="adpll_rstn_dr" pos="21" rst="0">
      </bits>
      <bits access="rw" name="adpll_rstn_reg" pos="20" rst="0">
      </bits>
      <bits access="rw" name="adpll_digreg_range" pos="19:16" rst="8">
      </bits>
      <bits access="rw" name="adpll_cp_rbit" pos="15:13" rst="4">
      </bits>
      <bits access="rw" name="adpll_cp_ibit" pos="12:9" rst="8">
      </bits>
      <bits access="rw" name="adpll_cpc2_bit" pos="8:6" rst="4">
      </bits>
      <bits access="rw" name="adpll_cpr2_bit" pos="5:3" rst="4">
      </bits>
      <bits access="rw" name="adpll_refmulti2_en" pos="2" rst="1">
      </bits>
      <bits access="rw" name="adpll_pcon_mode" pos="1" rst="0">
      </bits>
      <bits access="rw" name="adpll_sdm_clk_test_en" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="adpll_setting1">
      <bits access="r" name="adpll_setting1_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2bt_adc_en" pos="7" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2bt_dig_en" pos="6" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2fmwf_adc_en" pos="5" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2wf_dig_en" pos="4" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2bt_adc_sel" pos="3" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2bt_dig_sel" pos="2" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2fmwf_adc_sel" pos="1" rst="0">
      </bits>
      <bits access="rw" name="adpll_clk2wf_dig_sel" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="adpll_status">
      <bits access="r" name="adpll_status_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="adpll_lock_flag" pos="1" rst="0">
      </bits>
      <bits access="r" name="adpll_lock_det" pos="0" rst="0">
        <comment>
          Indicate if pll in lock state.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_sdm_setting0">
      <bits access="r" name="rfpll_sdm_setting0_reserved_0" pos="31:19" rst="0">
      </bits>
      <bits access="rw" name="rfpll_freq_former_shift_ct" pos="18:16" rst="5">
      </bits>
      <bits access="rw" name="rfpll_freq_former_bypass" pos="15" rst="0">
      </bits>
      <bits access="rw" name="rfpll_div_dr" pos="14" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_clk_sel_0" pos="13" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_clk_sel_1" pos="12" rst="1">
      </bits>
      <bits access="rw" name="reset_rfpll_sdm_delay" pos="11:10" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_resetn_dr" pos="9" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_resetn_reg" pos="8" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_clk_edge" pos="7" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_int_dec_sel" pos="6:5" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_dither_bypass" pos="4" rst="0">
      </bits>
      <bits access="rw" name="rfpll_sdm_delay_sel" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_sdm_setting1">
      <bits access="r" name="rfpll_sdm_setting1_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="rfpll_div_reg" pos="30:0" rst="0">
        <comment>
          To be used when rfpll_pll_freq_dr=1._x000D_
Fomula is freq*2^24/(mdll_div*crystal_clk)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="adpll_sdm_setting0">
      <bits access="r" name="adpll_sdm_setting0_reserved_0" pos="31:13" rst="0">
      </bits>
      <bits access="rw" name="adpll_sdm_freq_dr" pos="12" rst="0">
        <comment>
          If 1, pll frequency is decided by freq register;_x000D_
        </comment>
      </bits>
      <bits access="rw" name="adpll_sdm_clk_sel_0" pos="11" rst="0">
      </bits>
      <bits access="rw" name="adpll_sdm_clk_sel_1" pos="10" rst="1">
      </bits>
      <bits access="rw" name="reset_adpll_sdm_delay" pos="9:8" rst="0">
        <comment>
          Delay time select after txon|rxon|self_cal_en after pll_cal_ready &amp; prescaler_div_ready_x000D_
0:: 1us
1:: 2us
2:: 8us
3:: 16us
        </comment>
      </bits>
      <bits access="rw" name="adpll_sdm_resetn_dr" pos="7" rst="0">
        <comment>
          If 1, adpll sdm resetn uses sdm_resetn_reg; _x000D_
if 0, use logic value.
        </comment>
      </bits>
      <bits access="rw" name="adpll_sdm_resetn_reg" pos="6" rst="0">
        <comment>
          adpll Sdm modulator module reset register
        </comment>
      </bits>
      <bits access="rw" name="adpll_sdm_clk_fbc_inv" pos="5" rst="0">
        <comment>
          Invert SDM clock edge.
        </comment>
      </bits>
      <bits access="rw" name="adpll_sdm_int_dec_sel" pos="4:2" rst="3">
      </bits>
      <bits access="rw" name="adpll_sdm_dither_bypass" pos="1" rst="0">
        <comment>
          SDM dither bypass enable.
        </comment>
      </bits>
      <bits access="rw" name="adpll_sdm_refdiv2_en" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="adpll_sdm_setting1">
      <bits access="rw" name="adpll_sdm_freq_reg" pos="31:0" rst="0">
        <comment>
          To be used when adpll_sdm_freq_dr=1._x000D_
Fomula is freq*2^23/crystal_clk
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxflt_cal_setting0">
      <bits access="rw" name="wf_rxflt_cal_loop_pol" pos="31" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_loop_coef" pos="30:20" rst="1209">
      </bits>
      <bits access="rw" name="rxflt_cal_bit_dr" pos="19" rst="0">
      </bits>
      <bits access="rw" name="rxflt_cal_range_bit" pos="18:16" rst="7">
      </bits>
      <bits access="rw" name="rxflt_cal_mode" pos="15" rst="1">
      </bits>
      <bits access="rw" name="rxflt_cal_clk_edge" pos="14" rst="0">
      </bits>
      <bits access="rw" name="bt_gain_table_full_mode" pos="13" rst="1">
      </bits>
      <bits access="rw" name="wf_gain_table_full_mode" pos="12" rst="1">
      </bits>
      <bits access="rw" name="fm_gain_table_full_mode" pos="11" rst="1">
      </bits>
      <bits access="rw" name="rxflt_cal_clk_edge_sel" pos="10" rst="0">
      </bits>
      <bits access="rw" name="rxflt_cal_mode_sel" pos="9:8" rst="0">
      </bits>
      <bits access="rw" name="rxflt_cal_polarity" pos="7" rst="0">
      </bits>
      <bits access="rw" name="rxflt_cal_iqswap" pos="6" rst="0">
      </bits>
      <bits access="rw" name="rxflt_cal_cnt" pos="5:2" rst="8">
      </bits>
      <bits access="rw" name="rxflt_cal_init_delay" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="rxflt_cal_setting1">
      <bits access="r" name="rxflt_cal_setting1_reserved_0" pos="31:26" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_loop_adc_rng" pos="25:16" rst="750">
      </bits>
      <bits access="rw" name="rxflt_cal_i_bit_reg" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="rxflt_cal_q_bit_reg" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="r" name="cal_results">
      <bits access="r" name="cal_results_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="r" name="vco_band" pos="29:20" rst="512">
        <comment>
          current vco_band
        </comment>
      </bits>
      <bits access="r" name="vco_ibit" pos="19:16" rst="8">
        <comment>
          current vco_ibit
        </comment>
      </bits>
      <bits access="r" name="rxflt_cal_i_bit" pos="15:8" rst="128">
        <comment>
          current rxflt_cal_i_bit
        </comment>
      </bits>
      <bits access="r" name="rxflt_cal_q_bit" pos="7:0" rst="128">
        <comment>
          current rxflt_cal_q_bit
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="vco_cal_setting">
      <bits access="r" name="vco_cal_setting_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="vco_ibit_dr" pos="15" rst="0">
        <comment>
          if 1, vco_ibit is triggered by register;
if 0, vco_ibit is triggered by logic.
        </comment>
      </bits>
      <bits access="rw" name="vco_ibit_reg" pos="14:11" rst="8">
      </bits>
      <bits access="rw" name="vco_pkd_ref_bit" pos="10:8" rst="3">
      </bits>
      <bits access="rw" name="vco_pkd_clk_edge" pos="7" rst="0">
        <comment>
          vco_pkd_clk edge selection
        </comment>
      </bits>
      <bits access="rw" name="vco_cal_clk_edge_sel" pos="6" rst="0">
      </bits>
      <bits access="rw" name="vco_cal_mode" pos="5" rst="0">
        <comment>
          vco calibration mode. 1'h1: fast;'1d0:normal
        </comment>
      </bits>
      <bits access="rw" name="vco_cal_cnt" pos="4:3" rst="0">
        <comment>
          if vco_cal_mode=0, define the calibration period.
(vco_cal_cnt+1)*16*(vco_cal_wait_cnt+1)*4us
        </comment>
      </bits>
      <bits access="rw" name="vco_cal_init_delay" pos="2:1" rst="0">
        <comment>
          vco calibration initial delay.
2'h0:4us;2'h1:8us;2'h2:16us;2'h3:32us.
        </comment>
      </bits>
      <bits access="rw" name="vco_cal_polarity" pos="0" rst="0">
        <comment>
          vco_pkd_out polarity
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_cal_setting0">
      <bits access="r" name="rfpll_cal_setting0_reserved_0" pos="31:27" rst="0">
      </bits>
      <bits access="rw" name="rfpll_cal_clk_sel" pos="26" rst="0">
        <comment>
          Select the positive or negative edge of cal clk
        </comment>
      </bits>
      <bits access="rw" name="rfpll_cal_bit" pos="25:24" rst="1">
        <comment>
          Control voltage when in calibration._x000D_
0 :: lowest_x000D_
1 :: medial_01_x000D_
2 :: medial_10
3 :: highest
        </comment>
      </bits>
      <bits access="rw" name="rfpll_open_en" pos="23" rst="0">
        <comment>
          If 1, pll will be open loop.
        </comment>
      </bits>
      <bits access="rw" name="vco_band_dr" pos="22" rst="0">
        <comment>
          Pll_vco_band_reg direct reg enable.
        </comment>
      </bits>
      <bits access="rw" name="vco_band_reg" pos="21:12" rst="512">
        <comment>
          VCO band  setting.
        </comment>
      </bits>
      <bits access="rw" name="rfpll_cal_freq_dr" pos="11" rst="0">
      </bits>
      <bits access="rw" name="rfpll_cnt_enable_polarity" pos="10" rst="0">
        <comment>
          If 1, change pll_cnt_en edge mode(posedge or negedge of 26mhz clk)
        </comment>
      </bits>
      <bits access="rw" name="rfpll_vco_bit_hold_time" pos="9:7" rst="0">
        <comment>
          Vco bit hold time when vco bit changed during pll vco band calibration._x000D_
3'h0:: vco_bit_hold_time_0 : 0.25us_x000D_
3'h1:: vco_bit_hold_time_1 : 0.5us_x000D_
3'h2:: vco_bit_hold_time_2 : 0.75us_x000D_
3'h3:: vco_bit_hold_time_3 : 1us_x000D_
3'h4:: vco_bit_hold_time_4 : 1.25us_x000D_
3'h5:: vco_bit_hold_time_5 : 1.5us_x000D_
3'h6:: vco_bit_hold_time_6 : 1.75us_x000D_
3'h7:: vco_bit_hold_time_7 : 2us
        </comment>
      </bits>
      <bits access="rw" name="rfpll_cal_opt" pos="6" rst="1">
        <comment>
          If 1, select the best vco band bit
        </comment>
      </bits>
      <bits access="rw" name="rfpll_cal_cnt_sel" pos="5:3" rst="1">
        <comment>
          pll cal count time select_x000D_
3'h0:: each_cnt_time_0 : 0.5us_x000D_
3'h1:: each_cnt_time_1 : 1us_x000D_
3'h2:: each_cnt_time_2 : 2us_x000D_
3'h4:: each_cnt_time_3 : 4us_x000D_
3'h5:: each_cnt_time_4 : 8us
        </comment>
      </bits>
      <bits access="rw" name="rfpll_init_delay" pos="2:0" rst="0">
        <comment>
          Define pll_cal initial delay, which is the  time between RXON(TXON) and rxpll_cal_enable._x000D_ Unit is us.
3'h0:: loop_0
3'h1:: loop_1_x000D_
3'h2::  loop_2_x000D_
3'h3:: loop_3_x000D_
3'h4:: loop_4_x000D_
3'h5:: loop_5_x000D_
3'h6:: loop_6_x000D_
3'h7:: loop_7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_cal_setting1">
      <bits access="r" name="rfpll_cal_setting1_reserved_0" pos="31:16" rst="14">
      </bits>
      <bits access="rw" name="rfpll_cal_freq_reg" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="cal_dr_setting">
      <bits access="r" name="cal_dr_setting_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_fsm_type" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_fsm_type" pos="13:12" rst="0">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_fsm_resetn_dr" pos="11" rst="0">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_fsm_resetn_reg" pos="10" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_fsm_resetn_dr" pos="9" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_fsm_resetn_reg" pos="8" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_fsm_resetn_dr" pos="7" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_fsm_resetn_reg" pos="6" rst="0">
      </bits>
      <bits access="rw" name="vco_cal_resetn_dr" pos="5" rst="0">
      </bits>
      <bits access="rw" name="vco_cal_resetn_reg" pos="4" rst="0">
      </bits>
      <bits access="rw" name="rfpll_cal_resetn_dr" pos="3" rst="0">
      </bits>
      <bits access="rw" name="rfpll_cal_resetn_reg" pos="2" rst="0">
      </bits>
      <bits access="rw" name="self_cal_ready_dr" pos="1" rst="0">
      </bits>
      <bits access="rw" name="self_cal_ready_reg" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="cal_status">
      <bits access="r" name="cal_status_reserved_0" pos="31:9" rst="0">
      </bits>
      <bits access="r" name="fm_rxflt_cal_fsm_ready" pos="8" rst="0">
      </bits>
      <bits access="r" name="wf_rxflt_cal_fsm_ready" pos="7" rst="0">
      </bits>
      <bits access="r" name="bt_rxflt_cal_fsm_ready" pos="6" rst="0">
      </bits>
      <bits access="r" name="vco_cal_ready" pos="5" rst="0">
      </bits>
      <bits access="r" name="rfpll_cal_ready" pos="4" rst="0">
      </bits>
      <bits access="r" name="rxflt_cal_ready" pos="3" rst="0">
      </bits>
      <bits access="r" name="fm_self_cal_ready" pos="2" rst="0">
      </bits>
      <bits access="r" name="wf_self_cal_ready" pos="1" rst="0">
      </bits>
      <bits access="r" name="bt_self_cal_ready" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="power_dr">
      <bits access="r" name="power_dr_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="rw" name="bt_rmx_i2i_en_dr" pos="19" rst="0">
      </bits>
      <bits access="rw" name="pu_bg_dr" pos="18" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_fm_lna_dr" pos="17" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_fm_rmx_dr" pos="16" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_lna_dr" pos="15" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_rmx_dr" pos="14" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_rxflt_dr" pos="13" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_adc_dr" pos="12" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_dac_dr" pos="11" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_padrv_dr" pos="10" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_tmx_dr" pos="9" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_dr" pos="8" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_txlo_dr" pos="7" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_rxlo_dr" pos="6" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_pkd_dr" pos="5" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_peri_dr" pos="4" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_presc_dr" pos="3" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_fm_lo_clk_dr" pos="2" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_fm_adc_clk_dr" pos="1" rst="0">
        <comment>
          enable direct power control.
If this bit is set to 1'h1, corresponding power is directely controlled by register.
        </comment>
      </bits>
      <bits access="rw" name="pu_adpll_dr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="power_reg">
      <bits access="r" name="power_reg_reserved_0" pos="31:21" rst="0">
      </bits>
      <bits access="rw" name="pu_lvshifter_reg" pos="20" rst="1">
      </bits>
      <bits access="rw" name="bt_rmx_i2i_en_reg" pos="19" rst="0">
      </bits>
      <bits access="rw" name="pu_bg_reg" pos="18" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_fm_lna_reg" pos="17" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_fm_rmx_reg" pos="16" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_lna_reg" pos="15" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_rmx_reg" pos="14" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_rxflt_reg" pos="13" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_adc_reg" pos="12" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_dac_reg" pos="11" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_padrv_reg" pos="10" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_bt_tmx_reg" pos="9" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_reg" pos="8" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_txlo_reg" pos="7" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_rxlo_reg" pos="6" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_vco_pkd_reg" pos="5" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_peri_reg" pos="4" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_presc_reg" pos="3" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_fm_lo_clk_reg" pos="2" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_rfpll_fm_adc_clk_reg" pos="1" rst="0">
        <comment>
          power control direct register.
1'h0: power down; 1'h1: power up.
        </comment>
      </bits>
      <bits access="rw" name="pu_adpll_reg" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="power_status">
      <bits access="r" name="power_status_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="r" name="bt_rmx_i2i_en" pos="19" rst="0">
      </bits>
      <bits access="r" name="pu_bg" pos="18" rst="1">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_fm_lna" pos="17" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_fm_rmx" pos="16" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_bt_lna" pos="15" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_bt_rmx" pos="14" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_rxflt" pos="13" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_adc" pos="12" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_bt_dac" pos="11" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_bt_padrv" pos="10" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_bt_tmx" pos="9" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_vco" pos="8" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_vco_txlo" pos="7" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_vco_rxlo" pos="6" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_vco_pkd" pos="5" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_rfpll_peri" pos="4" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_rfpll_presc" pos="3" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_rfpll_fm_lo_clk" pos="2" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_rfpll_fm_adc_clk" pos="1" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
      <bits access="r" name="pu_adpll" pos="0" rst="0">
        <comment>
          power up status.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_0">
      <bits access="r" name="bt_gain_table_0_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_0" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_0" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_0" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_0" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_0" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=0
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_0_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_1" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_1" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_1" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_1" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_1" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_1">
      <bits access="r" name="bt_gain_table_1_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_2" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_2" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_2" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_2" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_2" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=2
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_1_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_3" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_3" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_3" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_3" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_3" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_2">
      <bits access="r" name="bt_gain_table_2_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_4" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_4" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_4" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_4" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_4" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=4
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_2_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_5" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_5" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_5" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_5" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_5" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_3">
      <bits access="r" name="bt_gain_table_3_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_6" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_6" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_6" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_6" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_6" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=6
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_3_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_7" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_7" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_7" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_7" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_7" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_4">
      <bits access="r" name="bt_gain_table_4_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_8" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_8" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_8" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_8" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_8" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=8
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_4_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_9" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_9" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_9" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_9" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_9" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_5">
      <bits access="r" name="bt_gain_table_5_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_a" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_a" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_a" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_a" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_a" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=a
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_5_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_b" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_b" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_b" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_b" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_b" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=b
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_6">
      <bits access="r" name="bt_gain_table_6_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_c" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_c" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_c" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_c" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_c" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=c
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_6_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_d" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_d" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_d" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_d" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_d" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=d
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_gain_table_7">
      <bits access="r" name="bt_gain_table_7_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_e" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_e" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_e" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_e" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_e" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=e
        </comment>
      </bits>
      <bits access="r" name="bt_gain_table_7_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_gain1_f" pos="13:10" rst="15">
        <comment>
          lna_gain1 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_gain2_f" pos="9:8" rst="3">
        <comment>
          lna_gain2 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="bt_rmx_gain_f" pos="7:4" rst="15">
        <comment>
          rmx_gain when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain1_f" pos="3:2" rst="3">
        <comment>
          filter_gain1 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="bt_rxflt_gain2_f" pos="1:0" rst="3">
        <comment>
          filter_gain2 when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_ibit_table_0">
      <bits access="r" name="bt_ibit_table_0_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_0" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_0" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=0
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_0_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_1" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_1" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=1
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_0_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_2" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_2" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=2
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_0_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_3" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_3" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_ibit_table_1">
      <bits access="r" name="bt_ibit_table_1_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_4" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_4" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=4
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_1_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_5" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_5" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=5
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_1_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_6" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_6" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=6
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_1_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_7" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_7" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_ibit_table_2">
      <bits access="r" name="bt_ibit_table_2_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_8" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_8" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=8
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_2_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_9" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_9" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=9
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_2_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_a" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_a" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=a
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_2_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_b" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_b" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=b
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_ibit_table_3">
      <bits access="r" name="bt_ibit_table_3_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_c" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_c" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=c
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_3_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_d" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_d" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=d
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_3_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_e" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_e" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=e
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_3_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_ibit1_f" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="bt_lna_ibit2_f" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_ibit_table_4">
      <bits access="r" name="bt_ibit_table_4_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_0" pos="30:28" rst="4">
        <comment>
          rx filter op_ibit when agc_index=0
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_4_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_1" pos="26:24" rst="4">
        <comment>
          rx filter op_ibit when agc_index=1
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_4_reserved_2" pos="23" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_2" pos="22:20" rst="4">
        <comment>
          rx filter op_ibit when agc_index=2
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_4_reserved_3" pos="19" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_3" pos="18:16" rst="4">
        <comment>
          rx filter op_ibit when agc_index=3
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_4_reserved_4" pos="15" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_4" pos="14:12" rst="4">
        <comment>
          rx filter op_ibit when agc_index=4
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_4_reserved_5" pos="11" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_5" pos="10:8" rst="4">
        <comment>
          rx filter op_ibit when agc_index=5
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_4_reserved_6" pos="7" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_6" pos="6:4" rst="4">
        <comment>
          rx filter op_ibit when agc_index=6
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_4_reserved_7" pos="3" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_7" pos="2:0" rst="4">
        <comment>
          rx filter op_ibit when agc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_ibit_table_5">
      <bits access="r" name="bt_ibit_table_5_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_8" pos="30:28" rst="4">
        <comment>
          rx filter op_ibit when agc_index=8
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_5_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_9" pos="26:24" rst="4">
        <comment>
          rx filter op_ibit when agc_index=9
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_5_reserved_2" pos="23" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_a" pos="22:20" rst="4">
        <comment>
          rx filter op_ibit when agc_index=a
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_5_reserved_3" pos="19" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_b" pos="18:16" rst="4">
        <comment>
          rx filter op_ibit when agc_index=b
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_5_reserved_4" pos="15" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_c" pos="14:12" rst="4">
        <comment>
          rx filter op_ibit when agc_index=c
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_5_reserved_5" pos="11" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_d" pos="10:8" rst="4">
        <comment>
          rx filter op_ibit when agc_index=d
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_5_reserved_6" pos="7" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_e" pos="6:4" rst="4">
        <comment>
          rx filter op_ibit when agc_index=e
        </comment>
      </bits>
      <bits access="r" name="bt_ibit_table_5_reserved_7" pos="3" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_op_ibit_f" pos="2:0" rst="4">
        <comment>
          rx filter op_ibit when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_0">
      <bits access="r" name="wf_gain_table_0_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_0" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_0" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_0" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_0" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_0" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=0
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_0_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_1" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_1" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_1" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_1" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_1" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_1">
      <bits access="r" name="wf_gain_table_1_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_2" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_2" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_2" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_2" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_2" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=2
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_1_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_3" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_3" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_3" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_3" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_3" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_2">
      <bits access="r" name="wf_gain_table_2_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_4" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_4" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_4" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_4" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_4" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=4
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_2_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_5" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_5" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_5" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_5" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_5" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_3">
      <bits access="r" name="wf_gain_table_3_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_6" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_6" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_6" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_6" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_6" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=6
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_3_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_7" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_7" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_7" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_7" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_7" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_4">
      <bits access="r" name="wf_gain_table_4_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_8" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_8" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_8" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_8" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_8" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=8
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_4_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_9" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_9" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_9" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_9" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_9" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_5">
      <bits access="r" name="wf_gain_table_5_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_a" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_a" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_a" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_a" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_a" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=a
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_5_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_b" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_b" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_b" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_b" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_b" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=b
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_6">
      <bits access="r" name="wf_gain_table_6_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_c" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_c" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_c" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_c" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_c" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=c
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_6_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_d" pos="13:10" rst="0">
        <comment>
          lna_gain1 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_d" pos="9:8" rst="0">
        <comment>
          lna_gain2 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_d" pos="7:4" rst="0">
        <comment>
          rmx_gain when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_d" pos="3:2" rst="0">
        <comment>
          filter_gain1 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_d" pos="1:0" rst="0">
        <comment>
          filter_gain2 when agc_index=d
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_gain_table_7">
      <bits access="r" name="wf_gain_table_7_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_e" pos="29:26" rst="0">
        <comment>
          lna_gain1 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_e" pos="25:24" rst="0">
        <comment>
          lna_gain2 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_e" pos="23:20" rst="0">
        <comment>
          rmx_gain when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_e" pos="19:18" rst="0">
        <comment>
          filter_gain1 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_e" pos="17:16" rst="0">
        <comment>
          filter_gain2 when agc_index=e
        </comment>
      </bits>
      <bits access="r" name="wf_gain_table_7_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_gain1_f" pos="13:10" rst="15">
        <comment>
          lna_gain1 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_gain2_f" pos="9:8" rst="3">
        <comment>
          lna_gain2 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="wf_rmx_gain_f" pos="7:4" rst="15">
        <comment>
          rmx_gain when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain1_f" pos="3:2" rst="3">
        <comment>
          filter_gain1 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="wf_rxflt_gain2_f" pos="1:0" rst="3">
        <comment>
          filter_gain2 when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_ibit_table_0">
      <bits access="r" name="wf_ibit_table_0_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_0" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_0" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=0
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_0_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_1" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_1" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=1
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_0_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_2" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_2" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=2
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_0_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_3" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_3" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_ibit_table_1">
      <bits access="r" name="wf_ibit_table_1_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_4" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_4" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=4
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_1_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_5" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_5" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=5
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_1_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_6" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_6" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=6
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_1_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_7" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_7" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_ibit_table_2">
      <bits access="r" name="wf_ibit_table_2_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_8" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_8" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=8
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_2_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_9" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_9" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=9
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_2_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_a" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_a" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=a
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_2_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_b" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_b" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=b
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_ibit_table_3">
      <bits access="r" name="wf_ibit_table_3_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_c" pos="30:28" rst="4">
        <comment>
          lna_ibit1 when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_c" pos="27:24" rst="8">
        <comment>
          lna_ibit2 when agc_index=c
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_3_reserved_1" pos="23" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_d" pos="22:20" rst="4">
        <comment>
          lna_ibit1 when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_d" pos="19:16" rst="8">
        <comment>
          lna_ibit2 when agc_index=d
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_3_reserved_2" pos="15" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_e" pos="14:12" rst="4">
        <comment>
          lna_ibit1 when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_e" pos="11:8" rst="8">
        <comment>
          lna_ibit2 when agc_index=e
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_3_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="rw" name="wf_lna_ibit1_f" pos="6:4" rst="4">
        <comment>
          lna_ibit1 when agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="wf_lna_ibit2_f" pos="3:0" rst="8">
        <comment>
          lna_ibit2 when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_ibit_table_4">
      <bits access="r" name="wf_ibit_table_4_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_0" pos="30:28" rst="4">
        <comment>
          rx filter op_ibit when agc_index=0
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_4_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_1" pos="26:24" rst="4">
        <comment>
          rx filter op_ibit when agc_index=1
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_4_reserved_2" pos="23" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_2" pos="22:20" rst="4">
        <comment>
          rx filter op_ibit when agc_index=2
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_4_reserved_3" pos="19" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_3" pos="18:16" rst="4">
        <comment>
          rx filter op_ibit when agc_index=3
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_4_reserved_4" pos="15" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_4" pos="14:12" rst="4">
        <comment>
          rx filter op_ibit when agc_index=4
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_4_reserved_5" pos="11" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_5" pos="10:8" rst="4">
        <comment>
          rx filter op_ibit when agc_index=5
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_4_reserved_6" pos="7" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_6" pos="6:4" rst="4">
        <comment>
          rx filter op_ibit when agc_index=6
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_4_reserved_7" pos="3" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_7" pos="2:0" rst="4">
        <comment>
          rx filter op_ibit when agc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wf_ibit_table_5">
      <bits access="r" name="wf_ibit_table_5_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_8" pos="30:28" rst="4">
        <comment>
          rx filter op_ibit when agc_index=8
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_5_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_9" pos="26:24" rst="4">
        <comment>
          rx filter op_ibit when agc_index=9
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_5_reserved_2" pos="23" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_a" pos="22:20" rst="4">
        <comment>
          rx filter op_ibit when agc_index=a
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_5_reserved_3" pos="19" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_b" pos="18:16" rst="4">
        <comment>
          rx filter op_ibit when agc_index=b
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_5_reserved_4" pos="15" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_c" pos="14:12" rst="4">
        <comment>
          rx filter op_ibit when agc_index=c
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_5_reserved_5" pos="11" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_d" pos="10:8" rst="4">
        <comment>
          rx filter op_ibit when agc_index=d
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_5_reserved_6" pos="7" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_e" pos="6:4" rst="4">
        <comment>
          rx filter op_ibit when agc_index=e
        </comment>
      </bits>
      <bits access="r" name="wf_ibit_table_5_reserved_7" pos="3" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_op_ibit_f" pos="2:0" rst="4">
        <comment>
          rx filter op_ibit when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_padrv_tmx_gain_table_0">
      <bits access="r" name="bt_padrv_tmx_gain_table_0_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_0" pos="29:27" rst="7">
        <comment>
          tmx gain when apc_index=0
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_0" pos="26:24" rst="7">
        <comment>
          padrv gain when apc_index=0
        </comment>
      </bits>
      <bits access="r" name="bt_padrv_tmx_gain_table_0_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_1" pos="21:19" rst="7">
        <comment>
          tmx gain when apc_index=1
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_1" pos="18:16" rst="7">
        <comment>
          padrv gain when apc_index=1
        </comment>
      </bits>
      <bits access="r" name="bt_padrv_tmx_gain_table_0_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_2" pos="13:11" rst="7">
        <comment>
          tmx gain when apc_index=2
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_2" pos="10:8" rst="7">
        <comment>
          padrv gain when apc_index=2
        </comment>
      </bits>
      <bits access="r" name="bt_padrv_tmx_gain_table_0_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_3" pos="5:3" rst="7">
        <comment>
          tmx gain when apc_index=3
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_3" pos="2:0" rst="7">
        <comment>
          padrv gain when apc_index=3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_padrv_tmx_gain_table_1">
      <bits access="r" name="bt_padrv_tmx_gain_table_1_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_4" pos="29:27" rst="7">
        <comment>
          tmx gain when apc_index=4
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_4" pos="26:24" rst="7">
        <comment>
          padrv gain when apc_index=4
        </comment>
      </bits>
      <bits access="r" name="bt_padrv_tmx_gain_table_1_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_5" pos="21:19" rst="7">
        <comment>
          tmx gain when apc_index=5
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_5" pos="18:16" rst="7">
        <comment>
          padrv gain when apc_index=5
        </comment>
      </bits>
      <bits access="r" name="bt_padrv_tmx_gain_table_1_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_6" pos="13:11" rst="7">
        <comment>
          tmx gain when apc_index=6
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_6" pos="10:8" rst="7">
        <comment>
          padrv gain when apc_index=6
        </comment>
      </bits>
      <bits access="r" name="bt_padrv_tmx_gain_table_1_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="bt_tmx_gain_7" pos="5:3" rst="7">
        <comment>
          tmx gain when apc_index=7
        </comment>
      </bits>
      <bits access="rw" name="bt_padrv_gain_7" pos="2:0" rst="7">
        <comment>
          padrv gain when apc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="fm_lna_gain_table">
      <bits access="rw" name="fm_lna_gain_bit_0" pos="31:30" rst="0">
        <comment>
          fm lna gain bit when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_1" pos="29:28" rst="0">
        <comment>
          fm lna gain bit when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_2" pos="27:26" rst="0">
        <comment>
          fm lna gain bit when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_3" pos="25:24" rst="0">
        <comment>
          fm lna gain bit when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_4" pos="23:22" rst="0">
        <comment>
          fm lna gain bit when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_5" pos="21:20" rst="0">
        <comment>
          fm lna gain bit when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_6" pos="19:18" rst="0">
        <comment>
          fm lna gain bit when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_7" pos="17:16" rst="0">
        <comment>
          fm lna gain bit when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_8" pos="15:14" rst="0">
        <comment>
          fm lna gain bit when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_9" pos="13:12" rst="0">
        <comment>
          fm lna gain bit when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_a" pos="11:10" rst="0">
        <comment>
          fm lna gain bit when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_b" pos="9:8" rst="0">
        <comment>
          fm lna gain bit when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_c" pos="7:6" rst="0">
        <comment>
          fm lna gain bit when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_d" pos="5:4" rst="0">
        <comment>
          fm lna gain bit when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_e" pos="3:2" rst="0">
        <comment>
          fm lna gain bit when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="fm_lna_gain_bit_f" pos="1:0" rst="3">
        <comment>
          fm lna gain bit when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="fm_rmx_gain_table_0">
      <bits access="r" name="fm_rmx_gain_table_0_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_0" pos="30:28" rst="0">
        <comment>
          fm mixer gain bit when agc_index=0
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_0_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_1" pos="26:24" rst="0">
        <comment>
          fm mixer gain bit when agc_index=1
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_0_reserved_2" pos="23" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_2" pos="22:20" rst="0">
        <comment>
          fm mixer gain bit when agc_index=2
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_0_reserved_3" pos="19" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_3" pos="18:16" rst="0">
        <comment>
          fm mixer gain bit when agc_index=3
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_0_reserved_4" pos="15" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_4" pos="14:12" rst="0">
        <comment>
          fm mixer gain bit when agc_index=4
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_0_reserved_5" pos="11" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_5" pos="10:8" rst="0">
        <comment>
          fm mixer gain bit when agc_index=5
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_0_reserved_6" pos="7" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_6" pos="6:4" rst="0">
        <comment>
          fm mixer gain bit when agc_index=6
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_0_reserved_7" pos="3" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_7" pos="2:0" rst="0">
        <comment>
          fm mixer gain bit when agc_index=7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="fm_rmx_gain_table_1">
      <bits access="r" name="fm_rmx_gain_table_1_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_8" pos="30:28" rst="0">
        <comment>
          fm mixer gain bit when agc_index=8
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_1_reserved_1" pos="27" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_9" pos="26:24" rst="0">
        <comment>
          fm mixer gain bit when agc_index=9
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_1_reserved_2" pos="23" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_a" pos="22:20" rst="0">
        <comment>
          fm mixer gain bit when agc_index=a
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_1_reserved_3" pos="19" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_b" pos="18:16" rst="0">
        <comment>
          fm mixer gain bit when agc_index=b
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_1_reserved_4" pos="15" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_c" pos="14:12" rst="0">
        <comment>
          fm mixer gain bit when agc_index=c
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_1_reserved_5" pos="11" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_d" pos="10:8" rst="0">
        <comment>
          fm mixer gain bit when agc_index=d
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_1_reserved_6" pos="7" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_e" pos="6:4" rst="0">
        <comment>
          fm mixer gain bit when agc_index=e
        </comment>
      </bits>
      <bits access="r" name="fm_rmx_gain_table_1_reserved_7" pos="3" rst="0">
      </bits>
      <bits access="rw" name="fm_rmx_gain_bit_f" pos="2:0" rst="7">
        <comment>
          fm mixer gain bit when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_gain_table">
      <bits access="rw" name="fm_rxflt_gain_bit_0" pos="31:30" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=0
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_1" pos="29:28" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_2" pos="27:26" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_3" pos="25:24" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_4" pos="23:22" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=4
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_5" pos="21:20" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_6" pos="19:18" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_7" pos="17:16" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_8" pos="15:14" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=8
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_9" pos="13:12" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_a" pos="11:10" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_b" pos="9:8" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_c" pos="7:6" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=c
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_d" pos="5:4" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_e" pos="3:2" rst="0">
        <comment>
          fm rxflt gain bit when agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="fm_rxflt_gain_bit_f" pos="1:0" rst="3">
        <comment>
          fm rxflt gain bit when agc_index=f
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="direct_gain_setting">
      <bits access="r" name="direct_gain_setting_reserved_0" pos="31:21" rst="0">
      </bits>
      <bits access="rw" name="bt_agc_gain_dr" pos="20" rst="0">
      </bits>
      <bits access="rw" name="bt_agc_gain_reg" pos="19:16" rst="15">
      </bits>
      <bits access="r" name="direct_gain_setting_reserved_1" pos="15:13" rst="0">
      </bits>
      <bits access="rw" name="wf_agc_gain_dr" pos="12" rst="0">
      </bits>
      <bits access="rw" name="wf_agc_gain_reg" pos="11:8" rst="15">
      </bits>
      <bits access="r" name="direct_gain_setting_reserved_2" pos="7:5" rst="0">
      </bits>
      <bits access="rw" name="fm_agc_gain_dr" pos="4" rst="0">
      </bits>
      <bits access="rw" name="fm_agc_gain_reg" pos="3:0" rst="15">
      </bits>
    </reg>
    <reg protect="rw" name="channel_setting0">
      <bits access="r" name="channel_setting0_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_cap_bit_lo" pos="15:13" rst="7">
      </bits>
      <bits access="rw" name="bt_rmx_lo_ifvcom_bit_lo" pos="12:9" rst="8">
      </bits>
      <bits access="rw" name="bt_tmx_cap_bit_lo" pos="8:5" rst="15">
      </bits>
      <bits access="rw" name="bt_tmx_lobias_lo" pos="4:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="channel_setting1">
      <bits access="r" name="channel_setting1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_cap_bit_md" pos="15:13" rst="3">
      </bits>
      <bits access="rw" name="bt_rmx_lo_ifvcom_bit_md" pos="12:9" rst="8">
      </bits>
      <bits access="rw" name="bt_tmx_cap_bit_md" pos="8:5" rst="7">
      </bits>
      <bits access="rw" name="bt_tmx_lobias_md" pos="4:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="channel_setting2">
      <bits access="r" name="channel_setting2_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="bt_lna_cap_bit_hi" pos="15:13" rst="3">
      </bits>
      <bits access="rw" name="bt_rmx_lo_ifvcom_bit_hi" pos="12:9" rst="8">
      </bits>
      <bits access="rw" name="bt_tmx_cap_bit_hi" pos="8:5" rst="7">
      </bits>
      <bits access="rw" name="bt_tmx_lobias_hi" pos="4:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg0">
      <bits access="rw" name="bt_rxflt_cal_i_bit_0" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_0" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_1" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_1" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg1">
      <bits access="rw" name="bt_rxflt_cal_i_bit_2" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_2" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_3" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_3" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg2">
      <bits access="rw" name="bt_rxflt_cal_i_bit_4" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_4" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_5" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_5" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg3">
      <bits access="rw" name="bt_rxflt_cal_i_bit_6" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_6" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_7" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_7" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg4">
      <bits access="rw" name="bt_rxflt_cal_i_bit_8" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_8" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_9" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_9" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg5">
      <bits access="rw" name="bt_rxflt_cal_i_bit_a" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_a" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_b" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_b" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg6">
      <bits access="rw" name="bt_rxflt_cal_i_bit_c" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_c" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_d" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_d" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg7">
      <bits access="rw" name="bt_rxflt_cal_i_bit_e" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_e" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_f" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_f" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg8">
      <bits access="rw" name="bt_rxflt_cal_i_bit_c_lo" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_c_lo" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_d_lo" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_d_lo" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_reg9">
      <bits access="rw" name="bt_rxflt_cal_i_bit_e_lo" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_e_lo" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_f_lo" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_f_lo" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_rega">
      <bits access="rw" name="bt_rxflt_cal_i_bit_c_hi" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_c_hi" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_d_hi" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_d_hi" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="bt_rxflt_cal_bit_regb">
      <bits access="rw" name="bt_rxflt_cal_i_bit_e_hi" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_e_hi" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_i_bit_f_hi" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_q_bit_f_hi" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg0">
      <bits access="rw" name="wf_rxflt_cal_i_bit_0" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_0" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_1" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_1" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg1">
      <bits access="rw" name="wf_rxflt_cal_i_bit_2" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_2" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_3" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_3" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg2">
      <bits access="rw" name="wf_rxflt_cal_i_bit_4" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_4" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_5" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_5" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg3">
      <bits access="rw" name="wf_rxflt_cal_i_bit_6" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_6" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_7" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_7" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg4">
      <bits access="rw" name="wf_rxflt_cal_i_bit_8" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_8" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_9" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_9" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg5">
      <bits access="rw" name="wf_rxflt_cal_i_bit_a" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_a" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_b" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_b" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg6">
      <bits access="rw" name="wf_rxflt_cal_i_bit_c" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_c" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_d" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_d" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg7">
      <bits access="rw" name="wf_rxflt_cal_i_bit_e" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_e" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_f" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_f" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg8">
      <bits access="rw" name="wf_rxflt_cal_i_bit_c_lo" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_c_lo" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_d_lo" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_d_lo" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_reg9">
      <bits access="rw" name="wf_rxflt_cal_i_bit_e_lo" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_e_lo" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_f_lo" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_f_lo" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_rega">
      <bits access="rw" name="wf_rxflt_cal_i_bit_c_hi" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_c_hi" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_d_hi" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_d_hi" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="wf_rxflt_cal_bit_regb">
      <bits access="rw" name="wf_rxflt_cal_i_bit_e_hi" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_e_hi" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_i_bit_f_hi" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_q_bit_f_hi" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg0">
      <bits access="rw" name="fm_rxflt_cal_i_bit_0" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_0" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_1" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_1" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg1">
      <bits access="rw" name="fm_rxflt_cal_i_bit_2" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_2" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_3" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_3" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg2">
      <bits access="rw" name="fm_rxflt_cal_i_bit_4" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_4" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_5" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_5" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg3">
      <bits access="rw" name="fm_rxflt_cal_i_bit_6" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_6" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_7" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_7" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg4">
      <bits access="rw" name="fm_rxflt_cal_i_bit_8" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_8" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_9" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_9" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg5">
      <bits access="rw" name="fm_rxflt_cal_i_bit_a" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_a" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_b" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_b" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg6">
      <bits access="rw" name="fm_rxflt_cal_i_bit_c" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_c" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_d" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_d" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="fm_rxflt_cal_bit_reg7">
      <bits access="rw" name="fm_rxflt_cal_i_bit_e" pos="31:24" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_e" pos="23:16" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_i_bit_f" pos="15:8" rst="128">
      </bits>
      <bits access="rw" name="fm_rxflt_cal_q_bit_f" pos="7:0" rst="128">
      </bits>
    </reg>
    <reg protect="rw" name="rxflt_cal_setting2">
      <bits access="r" name="rxflt_cal_setting2_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_inter_en" pos="29" rst="0">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_loop_en" pos="28" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_inter_en" pos="27" rst="0">
      </bits>
      <bits access="rw" name="wf_chn_md" pos="26:23" rst="7">
      </bits>
      <bits access="rw" name="bt_chn_md" pos="22:16" rst="39">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_inter_coef_lo" pos="15:8" rst="43">
      </bits>
      <bits access="rw" name="wf_rxflt_cal_inter_coef_hi" pos="7:0" rst="43">
      </bits>
    </reg>
    <reg protect="rw" name="rxflt_cal_setting3">
      <bits access="r" name="rxflt_cal_setting3_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_inter_coef_lo" pos="30:16" rst="840">
      </bits>
      <bits access="r" name="rxflt_cal_setting3_reserved_1" pos="15" rst="0">
      </bits>
      <bits access="rw" name="bt_rxflt_cal_inter_coef_hi" pos="14:0" rst="840">
      </bits>
    </reg>
    <reg protect="rw" name="reserved_reg0">
      <bits access="rw" name="ana_rsvd" pos="31:0" rst="4294901760">
      </bits>
    </reg>
    <reg protect="rw" name="reserved_reg1">
      <bits access="r" name="reserved_reg1_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="dig_rsvd" pos="15:8" rst="240">
      </bits>
      <bits access="r" name="rf_rsvd_in" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="reserved_reg2">
      <bits access="r" name="reserved_reg2_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="adpll_rsvd" pos="23:16" rst="240">
      </bits>
      <bits access="rw" name="fm_rsvd" pos="15:0" rst="65280">
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_sys_ctrl.xml">
  <module name="bt_sys_ctrl" category="WCN">
    <reg protect="rw" name="soft_reset">
      <bits access="rw" name="reg_sys_resetb" pos="31" rst="1">
        <comment>
           Global reset. 
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="r" name="soft_reset_reserved_0" pos="30:15" rst="0">
      </bits>
      <bits access="rw" name="reg_pulp_dbg_rstb" pos="14" rst="1">
        <comment>
          riscv debug unit rstb. Active low.
        </comment>
      </bits>
      <bits access="rw" name="reg_wdt_rst_sys_en" pos="13" rst="1">
        <comment>
          watch dog reset wcn system enable, 1 enable the reset, else no.
        </comment>
      </bits>
      <bits access="rw" name="reg_wakeup_ctrl_rstb" pos="12" rst="1">
        <comment>
          wake up logic reset.
        </comment>
      </bits>
      <bits access="rw" name="reg_bt_hresetn" pos="11" rst="1">
        <comment>
          for bt hclk reset. 
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_low_power_rstb" pos="10" rst="1">
        <comment>
          for bt 32k clock reset. 
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_uart_clk_rstb" pos="9" rst="1">
        <comment>
          uart clock domain reset. 
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_wdt_clk_rstb" pos="8" rst="1">
        <comment>
          watch dog clock domain reset, 32k actually.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_bt_master_rstb" pos="7" rst="1">
        <comment>
          bt master clock reset.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_bt_dbm_hresetn" pos="6" rst="1">
        <comment>
          bt core's debug master bus reset.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_aud_ifc_hresetn" pos="5" rst="1">
        <comment>
          AUDIFC function reset. Active low.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_sys_ifc_hresetn" pos="4" rst="1">
        <comment>
          sys_ifc module bus reset.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_jtag_hresetn" pos="3" rst="1">
        <comment>
          riscv jtag-&gt; ahb protocol bus reset.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_pulp_mcu_hresetn" pos="2" rst="0">
        <comment>
          riscv reset.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_mem_hresetn" pos="1" rst="1">
        <comment>
          bt_dig memory datapath reset.
1:: unreset
0:: reset
        </comment>
      </bits>
      <bits access="rw" name="reg_apb_presetn" pos="0" rst="1">
        <comment>
          not used, reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_cfg">
      <bits access="rw" name="reg_bus_clk_sel" pos="31:29" rst="0">
        <comment>
          bus clock selection: 0 sel hclk, 1 sel 26m, 2 sel 52m, 3 sel 32k
        </comment>
      </bits>
      <bits access="rw" name="reg_wakeup_ctrl_clk_en" pos="28" rst="1">
        <comment>
          wake up logic clock enable
        </comment>
      </bits>
      <bits access="rw" name="bt_clksel" pos="27:22" rst="13">
        <comment>
          bt core master clock indicator, 13M as default.
        </comment>
      </bits>
      <bits access="rw" name="reg_bt_master_clk_denom" pos="21:18" rst="4">
        <comment>
          bt master clock divider's denom,  bt_master_clk = bus_clk/reg_bt_master_clk_denom
        </comment>
      </bits>
      <bits access="rs" name="reg_bt_master_clk_ld" pos="17" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          load the bt_master_clk_denom into the clock divider.
        </comment>
      </bits>
      <bits access="rw" name="reg_master_clk_en" pos="16" rst="1">
        <comment>
          bt master clock divider enable
        </comment>
      </bits>
      <bits access="rw" name="reg_low_power_clk_en" pos="15" rst="1">
        <comment>
          low power clock enable for bt
        </comment>
      </bits>
      <bits access="rw" name="reg_jtag_hclk_en" pos="14" rst="1">
        <comment>
          jtag bus clock enable
        </comment>
      </bits>
      <bits access="rw" name="reg_sys_ifc_hclk_force_on" pos="13" rst="0">
        <comment>
          manually to set the sys_ifc bus clock to be open always.
        </comment>
      </bits>
      <bits access="rw" name="reg_sys_ifc_ch_hclk_force_on" pos="12:11" rst="0">
        <comment>
          manually to set the sys_ifc channels' clock to be open always.
        </comment>
      </bits>
      <bits access="rw" name="reg_aud_ifc_hclk_force_on" pos="10" rst="0">
        <comment>
          manually to set the aud_ifc bus clock to be open always.
        </comment>
      </bits>
      <bits access="rw" name="reg_aud_ifc_ch2_hclk_force_on" pos="9" rst="0">
        <comment>
          manually to set the aud_ifc channel 0' clock to be open always.
        </comment>
      </bits>
      <bits access="rw" name="reg_mem_hclk_en" pos="8" rst="1">
        <comment>
          bt_dig memory module's bus clock enable
        </comment>
      </bits>
      <bits access="rw" name="reg_bt_hclk_en" pos="7" rst="1">
        <comment>
          bt core's bus clock enable
        </comment>
      </bits>
      <bits access="rw" name="reg_bt_dbm_hclk_en" pos="6" rst="0">
        <comment>
          debug master bus clock enable
        </comment>
      </bits>
      <bits access="rw" name="reg_uart_clk_force_on" pos="5" rst="0">
        <comment>
          manually to set the uart clock to be open always.
        </comment>
      </bits>
      <bits access="rw" name="reg_uart_sys_clk_force_on" pos="4" rst="0">
        <comment>
          manually to set the uart sys(function) clock to be open always.
        </comment>
      </bits>
      <bits access="rw" name="reg_wdt_clk_en" pos="3" rst="1">
        <comment>
          watch dog clock enable
        </comment>
      </bits>
      <bits access="rw" name="reg_pulp_mcu_hclk_en" pos="2" rst="1">
        <comment>
          riscv bus clock enable
        </comment>
      </bits>
      <bits access="rw" name="reg_apb_reg_clk_force_on" pos="1" rst="0">
        <comment>
          apb bus clock to be open always.
        </comment>
      </bits>
      <bits access="rw" name="reg_mem_auto_ckg" pos="0" rst="1">
        <comment>
          memory access with clock enable.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="uart_clk_cfg">
      <bits access="r" name="uart_clk_cfg_reserved_0" pos="31:15" rst="0">
      </bits>
      <bits access="rs" name="reg_uart_clk_div_ld_cfg" pos="14" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          use new div parameters for divider.
        </comment>
      </bits>
      <bits access="rw" name="reg_uart_clk_div_en" pos="13" rst="1">
        <comment>
          uart clock divider enable.
        </comment>
      </bits>
      <bits access="rw" name="reg_uart_clk_denom" pos="12:0" rst="1">
        <comment>
          uart clock divider denom's configuration
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_208m_cfg">
      <bits access="r" name="clk_208m_cfg_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="rs" name="reg_clk_208m_div_ld_cfg" pos="9" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          use new div parameters for divider.
        </comment>
      </bits>
      <bits access="rw" name="reg_clk_208m_div_en" pos="8" rst="1">
        <comment>
          clock 208m divider enable.
        </comment>
      </bits>
      <bits access="rw" name="reg_clk_208m_num" pos="7:4" rst="1">
        <comment>
          clock 208m divider num's configuration
        </comment>
      </bits>
      <bits access="rw" name="reg_clk_208m_denom" pos="3:0" rst="2">
        <comment>
          clock 208m divider denom's configuration
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_conn">
      <bits access="r" name="sys_conn_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="r" name="sys2bt_irq" pos="3" rst="0">
        <comment>
          sys to bt irq, read only for check
        </comment>
      </bits>
      <bits access="rw" name="reg_wdt_gen_irq2sys_en" pos="2" rst="1">
        <comment>
          wdt gen irq to system enable control, 1 indicates enable.
        </comment>
      </bits>
      <bits access="rw" name="bt2sys_wakeup" pos="1" rst="0">
        <comment>
          reserved for future use, the wakeup to sys now use comregs's.
        </comment>
      </bits>
      <bits access="rw" name="bt2sys_soft_int" pos="0" rst="0">
        <comment>
          generate interrupt to system
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="riscv_boot_addr">
      <bits access="rw" name="pulp_mcu_boot_addr" pos="31:0" rst="0">
        <comment>
          the start address for riscv
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rf_cfg">
      <bits access="r" name="rf_cfg_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="rw" name="rf_reg_src_sel" pos="0" rst="0">
        <comment>
          RF Register Interface Selection
1:: SPI
0:: APB
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lvds_cfg">
      <bits access="r" name="lvds_cfg_reserved_0" pos="31:7" rst="0">
      </bits>
      <bits access="rw" name="sdm_clk_div_sel" pos="6" rst="0">
        <comment>
          tx clk sel
1'b1::selected sdm div clk as tx clk
        </comment>
      </bits>
      <bits access="rw" name="sdm_clk_sel" pos="5" rst="0">
        <comment>
          tx clk sel
1'b1::selected sdm ref clk as tx clk
        </comment>
      </bits>
      <bits access="rw" name="reg_lvds_rx_mode" pos="4:3" rst="0">
        <comment>
          RX Mode
0:: BT
1:: FM
2:: WLAN
        </comment>
      </bits>
      <bits access="rw" name="reg_lvds_out_sel" pos="2" rst="0">
        <comment>
          Data Source for LVDS Output
1:: internal DFE TX
0:: internal ADC
        </comment>
      </bits>
      <bits access="rw" name="reg_lvds_dac" pos="1" rst="0">
        <comment>
          Data Source for Internal DAC
1:: external DFE TX
0:: internal DFE TX
        </comment>
      </bits>
      <bits access="rw" name="reg_lvds_adc" pos="0" rst="0">
        <comment>
          Data Source for Internal DFE RX
1:: external ADC
0:: internal ADC
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="debug_config">
      <bits access="rw" name="reg_dbg_trig_sel" pos="31:28" rst="0">
        <comment>
          Debug trigger selection
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_trig_en" pos="27" rst="0">
        <comment>
          The triger is forced to 0 when disabled.
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_clk_sel" pos="26:23" rst="0">
        <comment>
          Debug clock selection
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_clk_en" pos="22" rst="0">
        <comment>
          The debug clock is forced to 0 when disabled.
        </comment>
      </bits>
      <bits access="r" name="debug_config_reserved_0" pos="21:9" rst="0">
      </bits>
      <bits access="rw" name="reg_dbg_out_nibble_shift_mode" pos="8" rst="0">
        <comment>
          nibble shift mode
0:: nibble_shift_mode0   
Ouptut is {dbg_out[11::0], dbg_out[15::12]}
1:: nibble_shift_mode1   
Ouptut is {dbg_out[15::12], dbg_out[7::4], dbg_out[11::8], dbg_out[3::0]}
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_out_nibble_shift" pos="7" rst="0">
        <comment>
          nibble shift enable
0:: nibble_shift_disable
Output is dbg_out[15::0]
1:: nibble_shift_en
Output is prcoess according dbg_out_nibble_mode
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_out_byte_swap" pos="6" rst="0">
        <comment>
          Byte swap of dbg_out
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_out_nibble_swap" pos="5" rst="0">
        <comment>
          Half Byte swap of dbg_out
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_out_en" pos="4" rst="0">
        <comment>
          when 0, all the mux data is forced to be 0.
        </comment>
      </bits>
      <bits access="rw" name="reg_dbg_out_sel" pos="3:0" rst="0">
        <comment>
          Debug out selection
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wakeup_ctrl_0">
      <bits access="r" name="wakeup_ctrl_0_reserved_0" pos="31:14" rst="0">
      </bits>
      <bits access="rw" name="host2bt_ext_wakeup_en" pos="13" rst="0">
        <comment>
          enable external wakeup request
        </comment>
      </bits>
      <bits access="rw" name="host2bt_hci_break_wakeup_en" pos="12" rst="0">
        <comment>
          enable hci uart break wakeup request
        </comment>
      </bits>
      <bits access="rw" name="host2bt_hci_activity_wakeup_en" pos="11" rst="0">
        <comment>
          enable hci activity wakeup request
        </comment>
      </bits>
      <bits access="rw" name="bt2host_wakeup_mode" pos="10" rst="1">
        <comment>
          bt2host wakeup mode
1::level mode
0::pulse mode
        </comment>
      </bits>
      <bits access="rw" name="bt2host_wakeup_period" pos="9:0" rst="255">
        <comment>
          bt2host wakeup level mode active cycle
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wakeup_ctrl_1">
      <bits access="r" name="wakeup_ctrl_1_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="s" name="bt2host_wakeup_trig" pos="0" rst="1">
        <comment>
        bit type is changed from wos to s.

          bt2host wakeup trigger
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="wakeup_status">
      <bits access="r" name="wakeup_status_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="r" name="bt2host_wakeup_status" pos="0" rst="0">
        <comment>
          bt2host wakeup status
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="extmem_offset">
      <bits access="rw" name="reg_extmem_offset_addr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="wcn2sys_offset">
      <bits access="rw" name="reg_wcn2sys_offset_addr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="audio_out_cfg">
      <bits access="r" name="audio_out_cfg_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="rw" name="reg_i2s_sel" pos="0" rst="0">
        <comment>
          i2s_sel when 1, select the i2s output, else select the pcm.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pulp_tag_mem_cfg">
      <bits access="r" name="pulp_tag_mem_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="tag_mem_cfg_shrink" pos="11:0" rst="162">
        <comment>
          LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pulp_data_mem_cfg">
      <bits access="r" name="pulp_data_mem_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="data_mem_cfg_shrink" pos="11:0" rst="162">
        <comment>
          LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wcn_rom_mem_cfg">
      <bits access="r" name="wcn_rom_mem_cfg_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="rw" name="rom_mem_cfg_shrink" pos="10:0" rst="74">
        <comment>
          LS+RME+RM(4Bits) + PGEN +KEN +EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wcn_dram_mem_cfg">
      <bits access="r" name="wcn_dram_mem_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="dram_mem_cfg_shrink" pos="11:0" rst="162">
        <comment>
          LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wcn_bram_mem_cfg">
      <bits access="r" name="wcn_bram_mem_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="bram_mem_cfg_shrink" pos="11:0" rst="162">
        <comment>
          LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_link_mem_cfg">
      <bits access="r" name="bt_link_mem_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="bt_link_mem_cfg_shrink" pos="11:0" rst="162">
        <comment>
          LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bt_modem_mem_cfg">
      <bits access="r" name="bt_modem_mem_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="bt_modem_mem_cfg_shrink" pos="11:0" rst="162">
        <comment>
          LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wlan_mem_cfg">
      <bits access="r" name="wlan_mem_cfg_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="rw" name="wlan_mem_cfg_shrink" pos="16:0" rst="2090">
        <comment>
          dual port: LS + RMEB + TEST1B + RMB(4Bits)+RMEA+TEST1A+RMA(4Bits)+RET1N+EMAA/EMB(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="plc_mem_cfg">
      <bits access="r" name="plc_mem_cfg_reserved_0" pos="31:12" rst="0">
      </bits>
      <bits access="rw" name="plc_mem_cfg_shrink" pos="11:0" rst="162">
        <comment>
          LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="hclk_freq">
      <bits access="r" name="hclk_freq_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="rw" name="wcn_hclk_freq" pos="7:0" rst="52">
        <comment>
          the unit is 1M, 52M in 8909 as default.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="branch_addr">
      <bits access="rw" name="risc_branch_addr" pos="31:0" rst="570425344">
        <comment>
          the address for riscv branch from rom, configured by ap
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="revision_id">
      <bits access="r" name="revision_id_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="r" name="wcn_id" pos="7:0" rst="0">
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_sys_ifc.xml">
  <module name="bt_sys_ifc" category="WCN">
    <reg protect="" name="get_ch">
      <bits access="r" name="get_ch_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="r" name="ch_to_use" pos="3:0" rst="0">
        <comment>
          This field indicates which standard channel to use. 
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy. 
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable_ in the control register of the channel to release the channel. 
4'h0::use_ch0:   use Channel0
4'h1::use_ch1:   use Channel1
4'h2::use_ch2:   use Channel2
4'h3::use_ch3:   use Channel3
4'h4::use_ch4:   use Channel4
4'h5::use_ch5:   use Channel5
4'h6::use_ch6:   use Channel6
4'h7::use_ch7:   use Channel7
4'hf::all_busy:       all channels are busy
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="dma_status">
      <bits access="r" name="dma_status_reserved_0" pos="31:23" rst="0">
      </bits>
      <bits access="r" name="ch_busy" pos="22:16" rst="0">
        <comment>
          This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is eNonebled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel
        </comment>
      </bits>
      <bits access="r" name="dma_status_reserved_1" pos="15:8" rst="0">
      </bits>
      <bits access="r" name="ch_enable" pos="7:0" rst="0">
        <comment>
          This register indicates which channel is eNonebled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:: 
8'h00::all_ch_disabled:      all channel disabled
8'h01::ch0_enabled:          Ch0 enabled 
8'h02::ch1_enabled:           Ch1 enabled 
8'h04::ch2_enabled:           Ch2 enabled 
8'h05::ch_0_2_enabled:     Ch0 and Ch2 enabled 
8'h07::ch_0_1_2_enabled: Ch0, Ch1 and Ch2 enabled 
8'hff::ch_all_enabled:          all channels eNonebled
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="debug_status">
      <bits access="r" name="debug_status_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="r" name="dbg_status" pos="0" rst="1">
        <comment>
          Debug Channel Status .
0:: dbg_ch_run: The debug channel is running (not idle) 
1::dbg_ch_idle: The debug channel is in idle mode
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="std_ch_0__std_ch_ctrl">
      <bits access="r" name="std_ch_ctrl_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="rw" name="flush" pos="16" rst="0">
        <comment>
          When one, flush the interNonel FIFO channel. 
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. 
Before writting back this bit to zero the interNonel fifo must empty.
        </comment>
      </bits>
      <bits access="r" name="std_ch_ctrl_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="req_src" pos="10:8" rst="7">
        <comment>
          Select DMA Request source
0:: SYS_ID_TX_UART  
1:: SYS_ID_RX_UART  
2:: SYS_ID_TX_SDMMC  
3:: SYS_ID_RX_SDMMC  
4:: SYS_ID_TX_SPI1  
5:: SYS_ID_RX_SPI1  
6:: SYS_ID_TX_DEBUG_UART  
7:: SYS_ID_RX_DEBUG_UART  
        </comment>
      </bits>
      <bits access="r" name="std_ch_ctrl_reserved_2" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="size" pos="5" rst="0">
        <comment>
          Peripheral Size 
0::per_size_8:   8-bit peripheral 
1::per_size_32: 32-bit peripheral
        </comment>
      </bits>
      <bits access="rw" name="autodisable" pos="4" rst="1">
        <comment>
          Set Auto-disable_ mode
0::auto_disable_close:  when TC reach zero the channel is not automatically released.
1::auto_disable_open:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.
        </comment>
      </bits>
      <bits access="rw" name="ch_wr_hw_exch" pos="3" rst="0">
        <comment>
          Set Auto-disable_ mode
0:: auto_dis_mode0:  when TC reach zero the channel is not automatically released.
1:: auto_dis_mode1:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.
        </comment>
      </bits>
      <bits access="rw" name="ch_rd_hw_exch" pos="2" rst="0">
        <comment>
          Read FIFO data exchange high 8-bit and low 8-bit. 
0:: Exchange   
1:: No_exchange
        </comment>
      </bits>
      <bits access="rc" name="disable" pos="1" rst="0">
        <comment>
        bit type is changed from wrc to rc.

          Channel Disable, write one in this bit disable_ the channel. 
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d.
        </comment>
      </bits>
      <bits access="rc" name="enable" pos="0" rst="0">
        <comment>
        bit type is changed from wrc to rc.

          Channel Enable, write one in this bit eNoneble the channel. 
When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="std_ch_0__std_ch_status">
      <bits access="r" name="std_ch_status_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>
          The internal channel fifo is empty
        </comment>
      </bits>
      <bits access="r" name="std_ch_status_reserved_1" pos="3:1" rst="0">
      </bits>
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>
          Enable bit, when '1' the channel is running
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="std_ch_0__std_ch_start_addr">
      <bits access="rw" name="start_addr" pos="31:0" rst="4294967295">
        <comment>
          AHB Address. This field represent the start address of the transfer. 
For a 32-bit peripheral, this address must be aligned 32-bit.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="std_ch_0__std_ch_tc">
      <bits access="r" name="std_ch_tc_reserved_0" pos="31:23" rst="0">
      </bits>
      <bits access="rw" name="tc" pos="22:0" rst="8388607">
        <comment>
          Transfer Count, this field indicated the transfer size_ in bytes to perform. 
During a transfer a write in this register add the new value to the current TC. 
A read of this register return the current current transfer count.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="std_ch_1__std_ch_ctrl">
      <bits access="r" name="std_ch_ctrl_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="rw" name="flush" pos="16" rst="0">
        <comment>
          When one, flush the interNonel FIFO channel. 
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. 
Before writting back this bit to zero the interNonel fifo must empty.
        </comment>
      </bits>
      <bits access="r" name="std_ch_ctrl_reserved_1" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="req_src" pos="10:8" rst="7">
        <comment>
          Select DMA Request source
0:: SYS_ID_TX_UART  
1:: SYS_ID_RX_UART  
2:: SYS_ID_TX_SDMMC  
3:: SYS_ID_RX_SDMMC  
4:: SYS_ID_TX_SPI1  
5:: SYS_ID_RX_SPI1  
6:: SYS_ID_TX_DEBUG_UART  
7:: SYS_ID_RX_DEBUG_UART  
        </comment>
      </bits>
      <bits access="r" name="std_ch_ctrl_reserved_2" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="size" pos="5" rst="0">
        <comment>
          Peripheral Size 
0::per_size_8:   8-bit peripheral 
1::per_size_32: 32-bit peripheral
        </comment>
      </bits>
      <bits access="rw" name="autodisable" pos="4" rst="1">
        <comment>
          Set Auto-disable_ mode
0::auto_disable_close:  when TC reach zero the channel is not automatically released.
1::auto_disable_open:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.
        </comment>
      </bits>
      <bits access="rw" name="ch_wr_hw_exch" pos="3" rst="0">
        <comment>
          Set Auto-disable_ mode
0:: auto_dis_mode0:  when TC reach zero the channel is not automatically released.
1:: auto_dis_mode1:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.
        </comment>
      </bits>
      <bits access="rw" name="ch_rd_hw_exch" pos="2" rst="0">
        <comment>
          Read FIFO data exchange high 8-bit and low 8-bit. 
0:: Exchange   
1:: No_exchange
        </comment>
      </bits>
      <bits access="rc" name="disable" pos="1" rst="0">
        <comment>
        bit type is changed from wrc to rc.

          Channel Disable, write one in this bit disable_ the channel. 
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d.
        </comment>
      </bits>
      <bits access="rc" name="enable" pos="0" rst="0">
        <comment>
        bit type is changed from wrc to rc.

          Channel Enable, write one in this bit eNoneble the channel. 
When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="std_ch_1__std_ch_status">
      <bits access="r" name="std_ch_status_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>
          The internal channel fifo is empty
        </comment>
      </bits>
      <bits access="r" name="std_ch_status_reserved_1" pos="3:1" rst="0">
      </bits>
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>
          Enable bit, when '1' the channel is running
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="std_ch_1__std_ch_start_addr">
      <bits access="rw" name="start_addr" pos="31:0" rst="4294967295">
        <comment>
          AHB Address. This field represent the start address of the transfer. 
For a 32-bit peripheral, this address must be aligned 32-bit.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="std_ch_1__std_ch_tc">
      <bits access="r" name="std_ch_tc_reserved_0" pos="31:23" rst="0">
      </bits>
      <bits access="rw" name="tc" pos="22:0" rst="8388607">
        <comment>
          Transfer Count, this field indicated the transfer size_ in bytes to perform. 
During a transfer a write in this register add the new value to the current TC. 
A read of this register return the current current transfer count.
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_systick.xml">
  <module name="bt_systick" category="WCN">
    <reg protect="rw" name="csr">
      <bits access="r" name="csr_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="r" name="countflag" pos="16" rst="0">
        <comment>
          indicates the counter decreasing to 0.
        </comment>
      </bits>
      <bits access="r" name="csr_reserved_1" pos="15:3" rst="0">
      </bits>
      <bits access="rw" name="clksrc" pos="2" rst="1">
        <comment>
          indicates clock source, 0 is reference clock, 1 is mcu clk.
        </comment>
      </bits>
      <bits access="rw" name="tickint" pos="1" rst="0">
        <comment>
          interrupte enable
        </comment>
      </bits>
      <bits access="rw" name="enable" pos="0" rst="0">
        <comment>
          systick counter enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rvr">
      <bits access="r" name="rvr_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="val" pos="23:0" rst="0">
        <comment>
          the value to load into cvr when counter decreases to 0.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="cvr">
      <bits access="r" name="cvr_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="r" name="val" pos="23:0" rst="0">
        <comment>
          the current cvr value.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="calib">
      <bits access="rw" name="noref" pos="31" rst="0">
        <comment>
          indicates whether ref clk is implemented. 0 means implemented.
        </comment>
      </bits>
      <bits access="rw" name="skew" pos="30" rst="0">
        <comment>
          indicates whether 10ms calibration value is exact.
        </comment>
      </bits>
      <bits access="r" name="calib_reserved_0" pos="29:24" rst="0">
      </bits>
      <bits access="rw" name="tenms" pos="23:0" rst="0">
        <comment>
          calibration value of the reload value to be used for 10ms timing
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clr">
      <bits access="r" name="clr_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="w" name="en" pos="0" rst="0">
        <comment>
          clear the interrupte.
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_trap.xml">
  <module name="bt_trap" category="WCN">
    <reg protect="rw" name="addr_in_0">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_1">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_2">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_3">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_4">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_5">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_6">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_7">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_8">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_9">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_10">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_11">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_12">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_13">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_14">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_15">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_16">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_17">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_18">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_19">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_20">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_21">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_22">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_23">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_24">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_25">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_26">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_27">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_28">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_29">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_30">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_in_31">
      <bits access="r" name="addr_in_reserved_0" pos="31:18" rst="0">
      </bits>
      <bits access="rw" name="addr_in" pos="17:0" rst="0">
        <comment>
          address to be trapped. Range 0x00000000~0x0003fffc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="trap_en">
      <bits access="rw" name="en" pos="31:0" rst="0">
        <comment>
          trap enable for 32 channels
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="addr_out">
      <bits access="rw" name="addr_out_base" pos="31:0" rst="0">
        <comment>
          base address to trapped to. Should be 32 words aligned (such as 0x00053e80 or 0x0004ff00).For the nth patch, the actual address is trap_out_base+4n
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_uart.xml">
  <module name="bt_uart" category="WCN">
    <reg protect="rw" name="ctrl">
      <bits access="rw" name="rx_break_length" pos="31:28" rst="15">
        <comment>
          Length of a break, in number of bits.
        </comment>
      </bits>
      <bits access="r" name="ctrl_reserved_0" pos="27:26" rst="0">
      </bits>
      <bits access="rw" name="rx_lock_err" pos="25" rst="0">
        <comment>
          Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept.
        </comment>
      </bits>
      <bits access="rw" name="loop_back_mode" pos="24" rst="0">
        <comment>
          When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support).
        </comment>
      </bits>
      <bits access="rw" name="auto_flow_control" pos="23" rst="0">
        <comment>
          Enables the auto flow control. Uart_RTS is controlled by the Rx RTS bit and the UART Auto Control Flow System. If Uart_CTS become inactive high, the Tx data flow is stopped.
1::ENABLE
0:: DISABLE

        </comment>
      </bits>
      <bits access="rw" name="dma_mode" pos="22" rst="0">
        <comment>
          Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC.
0:: DISABLE
1::ENABLE

        </comment>
      </bits>
      <bits access="rw" name="irda_enable" pos="21" rst="0">
        <comment>
          When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details).
        </comment>
      </bits>
      <bits access="rw" name="divisor_mode" pos="20" rst="0">
        <comment>
          Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16.
0 = (BCLK = SCLK / 4)
1 = (BCLK = SCLK / 16)
0:div_4
1:div_16
        </comment>
      </bits>
      <bits access="r" name="ctrl_reserved_1" pos="19:6" rst="0">
      </bits>
      <bits access="rw" name="parity_select" pos="5:4" rst="0">
        <comment>
          Controls the parity format when parity is enabled:
0::odd: an odd number of received 1 bits is checked, or transmitted (the parity bit is included).
1::even: an even number of received 1 bits is checked or transmitted (the parity bit is included).
2::space: space a space is generated and received as parity bit.
3::mark: a mark is generated and received as parity bit.
        </comment>
      </bits>
      <bits access="rw" name="parity_enable" pos="3" rst="0">
        <comment>
          Parity is enabled when this bit is set.
0::NO
1:: YES

        </comment>
      </bits>
      <bits access="rw" name="tx_stop_bits" pos="2" rst="0">
        <comment>
          Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0).
0::1_bit :one stop bit is transmitted in the serial data.
1:: 2_bits:two stop bits are generated and transmitted in the serial data out.
        </comment>
      </bits>
      <bits access="rw" name="data_bits" pos="1" rst="0">
        <comment>
          Number of data bits per character (least significant bit first):
0::7_bits
1::8_bits
        </comment>
      </bits>
      <bits access="rw" name="enable" pos="0" rst="0">
        <comment>
          Allows to turn off the UART:
0:: Disable
1::Enable
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="status">
      <bits access="r" name="clk_enabled" pos="31" rst="0">
        <comment>
          This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling RTS too early.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_0" pos="30:29" rst="0">
      </bits>
      <bits access="r" name="dtr" pos="28" rst="0">
        <comment>
          Current value of the DTR line.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_1" pos="27:26" rst="0">
      </bits>
      <bits access="r" name="cts" pos="25" rst="1">
        <comment>
          current value of the Uart_CTS line. 
1::Tx_allow_n:Tx not allowed. 
0::Tx_alllow:Tx allowed.
        </comment>
      </bits>
      <bits access="r" name="dcts" pos="24" rst="0">
        <comment>
          This bit is set when the Uart_CTS line changed since the last time this register has been written. This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_2" pos="23:21" rst="0">
      </bits>
      <bits access="r" name="rx_break_int" pos="20" rst="0">
        <comment>
          This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
      <bits access="r" name="rx_framing_err" pos="19" rst="0">
        <comment>
          This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
      <bits access="r" name="rx_parity_err" pos="18" rst="0">
        <comment>
          This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
      <bits access="r" name="tx_overflow_err" pos="17" rst="0">
        <comment>
          This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
      <bits access="r" name="rx_overflow_err" pos="16" rst="0">
        <comment>
          This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
      <bits access="r" name="rx_active" pos="15" rst="0">
        <comment>
          This bit indicates that the UART is receiving a byte.
        </comment>
      </bits>
      <bits access="r" name="tx_active" pos="14" rst="0">
        <comment>
          This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface.
        </comment>
      </bits>
      <bits access="r" name="reserved_4" pos="13" rst="0">
      </bits>
      <bits access="r" name="tx_fifo_space" pos="12:8" rst="0">
        <comment>
          Those bits indicate the number of space available in the Tx Fifo.
        </comment>
      </bits>
      <bits access="r" name="status_reserved_3" pos="7" rst="0">
      </bits>
      <bits access="r" name="rx_fifo_level" pos="6:0" rst="0">
        <comment>
          Those bits indicate the number of data available in the Rx Fifo. Those data can be read.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxtx_buffer">
      <bits access="r" name="reserved_23" pos="31" rst="0">
      </bits>
      <bits access="r" name="reserved_22" pos="30" rst="0">
      </bits>
      <bits access="r" name="reserved_21" pos="29" rst="0">
      </bits>
      <bits access="r" name="reserved_20" pos="28" rst="0">
      </bits>
      <bits access="r" name="reserved_19" pos="27" rst="0">
      </bits>
      <bits access="r" name="reserved_18" pos="26" rst="0">
      </bits>
      <bits access="r" name="reserved_17" pos="25" rst="0">
      </bits>
      <bits access="r" name="reserved_16" pos="24" rst="0">
      </bits>
      <bits access="r" name="reserved_15" pos="23" rst="0">
      </bits>
      <bits access="r" name="reserved_14" pos="22" rst="0">
      </bits>
      <bits access="r" name="reserved_13" pos="21" rst="0">
      </bits>
      <bits access="r" name="reserved_12" pos="20" rst="0">
      </bits>
      <bits access="r" name="reserved_11" pos="19" rst="0">
      </bits>
      <bits access="r" name="reserved_10" pos="18" rst="0">
      </bits>
      <bits access="r" name="reserved_9" pos="17" rst="0">
      </bits>
      <bits access="r" name="reserved_8" pos="16" rst="0">
      </bits>
      <bits access="r" name="reserved_7" pos="15" rst="0">
      </bits>
      <bits access="r" name="reserved_6" pos="14" rst="0">
      </bits>
      <bits access="r" name="reserved_5" pos="13" rst="0">
      </bits>
      <bits access="r" name="reserved_4" pos="12" rst="0">
      </bits>
      <bits access="r" name="reserved_3" pos="11" rst="0">
      </bits>
      <bits access="r" name="reserved_2" pos="10" rst="0">
      </bits>
      <bits access="r" name="reserved_1" pos="9" rst="0">
      </bits>
      <bits access="r" name="reserved_0" pos="8" rst="0">
      </bits>
      <bits access="rw" name="data" pos="7:0" rst="0">
        <comment>
          The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="irq_mask">
      <bits access="r" name="irq_mask_reserved_0" pos="31:10" rst="0">
      </bits>
      <bits access="rw" name="dtr_fall" pos="9" rst="0">
        <comment>
          Falling edge detected on the UART_DTR signal.
        </comment>
      </bits>
      <bits access="rw" name="dtr_rise" pos="8" rst="0">
        <comment>
          Rising edge detected on the UART_DTR signal.
        </comment>
      </bits>
      <bits access="rw" name="rx_dma_timeout" pos="7" rst="0">
        <comment>
          In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times.
        </comment>
      </bits>
      <bits access="rw" name="rx_dma_done" pos="6" rst="0">
        <comment>
          Pulse detected on Uart_Dma_Rx_Done_H signal
        </comment>
      </bits>
      <bits access="rw" name="tx_dma_done" pos="5" rst="0">
        <comment>
          Pulse detected on Uart_Dma_Tx_Done_H signal.
        </comment>
      </bits>
      <bits access="rw" name="rx_line_err" pos="4" rst="0">
        <comment>
          Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt.
        </comment>
      </bits>
      <bits access="rw" name="rx_timeout" pos="3" rst="0">
        <comment>
          No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time.
        </comment>
      </bits>
      <bits access="rw" name="tx_data_needed" pos="2" rst="0">
        <comment>
          Tx Fifo at or below threshold level (current level &lt;= Tx Fifo trigger level).
        </comment>
      </bits>
      <bits access="rw" name="rx_data_available" pos="1" rst="0">
        <comment>
          Rx Fifo at or upper threshold level (current level &gt;= Rx Fifo trigger level).
        </comment>
      </bits>
      <bits access="rw" name="tx_modem_status" pos="0" rst="0">
        <comment>
          Clear to send signal change detected.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="irq_cause">
      <bits access="r" name="irq_cause_reserved_0" pos="31:26" rst="0">
      </bits>
      <bits access="r" name="dtr_fall_u" pos="25" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="dtr_rise_u" pos="24" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="rx_dma_timeout_u" pos="23" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="rx_dma_done_u" pos="22" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="tx_dma_done_u" pos="21" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="rx_line_err_u" pos="20" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="rx_timeout_u" pos="19" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="tx_data_needed_u" pos="18" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="rx_data_available_u" pos="17" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="tx_modem_status_u" pos="16" rst="0">
        <comment>
          Same as previous, not masked.
        </comment>
      </bits>
      <bits access="r" name="irq_cause_reserved_1" pos="15:10" rst="0">
      </bits>
      <bits access="r" name="dtr_fall" pos="9" rst="0">
        <comment>
          This interrupt is generated when a falling edge is detected on the UART_DTR signal. Reset control: Write one in this register.
        </comment>
      </bits>
      <bits access="r" name="dtr_rise" pos="8" rst="0">
        <comment>
          This interrupt is generated when a rising edge is detected on the UART_DTR signal. Reset control: Write one in this register.
        </comment>
      </bits>
      <bits access="r" name="rx_dma_timeout" pos="7" rst="0">
        <comment>
          In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times.
        </comment>
      </bits>
      <bits access="r" name="rx_dma_done" pos="6" rst="0">
        <comment>
          This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register.
        </comment>
      </bits>
      <bits access="r" name="tx_dma_done" pos="5" rst="0">
        <comment>
          This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register.
        </comment>
      </bits>
      <bits access="r" name="rx_line_err" pos="4" rst="0">
        <comment>
          Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
      <bits access="r" name="rx_timeout" pos="3" rst="0">
        <comment>
          No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register.
        </comment>
      </bits>
      <bits access="r" name="tx_data_needed" pos="2" rst="0">
        <comment>
          Tx Fifo at or below threshold level (current level &lt;= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level.
        </comment>
      </bits>
      <bits access="r" name="rx_data_available" pos="1" rst="0">
        <comment>
          Rx Fifo at or upper threshold level (current level &gt;= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level.
        </comment>
      </bits>
      <bits access="r" name="tx_modem_status" pos="0" rst="0">
        <comment>
          Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="triggers">
      <bits access="r" name="triggers_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="rw" name="afc_level" pos="21:16" rst="0">
        <comment>
          Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC).
The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo &gt; AFC Level.
        </comment>
      </bits>
      <bits access="r" name="triggers_reserved_1" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="tx_trigger" pos="11:8" rst="0">
        <comment>
          Defines the empty threshold level at which the Data Needed Interrupt will be generated.
The Data Needed Interrupt is generated when quantity of data in Tx Fifo &lt;= Tx Trigger.
        </comment>
      </bits>
      <bits access="r" name="triggers_reserved_2" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="rx_trigger" pos="5:0" rst="0">
        <comment>
          Defines the empty threshold level at which the Data Available Interrupt will be generated. 
The Data Available interrupt is generated when quantity of data in Rx Fifo &gt; Rx Trigger.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="cmd_set">
      <bits access="r" name="cmd_set_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="w" name="tx_fifo_reset" pos="7" rst="0">
        <comment>
          Writing a 1 to this bit resets and flushes the Transmit Fifo. This bit does not need to be cleared.
        </comment>
      </bits>
      <bits access="w" name="rx_fifo_reset" pos="6" rst="0">
        <comment>
          Writing a 1 to this bit resets and flushes the Receive Fifo. This bit does not need to be cleared.
        </comment>
      </bits>
      <bits access="rs" name="rx_rts" pos="5" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          this bit is set to 1 when writing 1, cleared to 0 when corresponding filed is cleared in UART_CMD_CLR
        </comment>
      </bits>
      <bits access="rs" name="tx_finish_n_wait" pos="4" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rs" name="tx_break_control" pos="3" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rs" name="dsr" pos="2" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rs" name="dcd" pos="1" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rs" name="ri" pos="0" rst="0">
        <comment>
        bit type is changed from w1s to rs.

          refer to bit [5]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="cmd_clr">
      <bits access="r" name="cmd_clr_reserved_0" pos="31:6" rst="0">
      </bits>
      <bits access="rc" name="rx_cpu_rts" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          this bit is cleared to 0 when writing 1, set to 1 when corresponding filed is set in UART_CMD_SET
        </comment>
      </bits>
      <bits access="rc" name="tx_finish_n_wait" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rc" name="tx_break_control" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rc" name="dsr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rc" name="dcr" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          refer to bit [5]
        </comment>
      </bits>
      <bits access="rc" name="ri" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

          refer to bit [5]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="auto_baud">
      <bits access="r" name="auto_baud_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="verify_char1" pos="23:16" rst="84">
      </bits>
      <bits access="rw" name="verify_char0" pos="15:8" rst="65">
      </bits>
      <bits access="r" name="auto_baud_reserved_1" pos="7:3" rst="0">
      </bits>
      <bits access="rw" name="verify_2byte" pos="2" rst="0">
      </bits>
      <bits access="rw" name="auto_tracking" pos="1" rst="0">
      </bits>
      <bits access="rw" name="auto_enable" pos="0" rst="0">
      </bits>
    </reg>
  </module>
</archive>
<archive relative="bt_wdt.xml">
  <module name="bt_wdt" category="WCN">
    <reg protect="rw" name="wdt_cvr0">
      <bits access="r" name="wdt_cvr0_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="count_vaule_0" pos="23:0" rst="16777215">
        <comment>
          wdt_cvr0_count_value_0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wdt_cvr1">
      <bits access="r" name="wdt_cvr1_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="count_vaule_1" pos="23:0" rst="16777215">
        <comment>
          wdt_cvr1_count_value_1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wdt_cr">
      <bits access="r" name="wdt_cr_reserved_0" pos="31:5" rst="0">
      </bits>
      <bits access="rw" name="cr_mode" pos="4" rst="1">
        <comment>
          1: generate interrupt when counter down from count_value_0 to zero,
    and generate reset when counter down from count_value_1 to zero.
0: generate reset when counter down from count_value_0 to zero
        </comment>
      </bits>
      <bits access="r" name="wdt_cr_reserved_1" pos="3" rst="0">
      </bits>
      <bits access="rw" name="cr_reset_length" pos="2:0" rst="0">
        <comment>
          reset length
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wdt_cmd">
      <bits access="r" name="wdt_cmd_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="w" name="cmd_cmd" pos="7:0" rst="0">
        <comment>
          command
8'h76 : restart
8'h34 : stop
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="wdt_icr">
      <bits access="r" name="wdt_icr_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="w" name="int_clr" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="wdt_sr">
      <bits access="r" name="wdt_sr_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="wdt_active" pos="1" rst="0">
      </bits>
      <bits access="r" name="int_assert" pos="0" rst="0">
      </bits>
    </reg>
  </module>
</archive>
<archive relative="cache_ctrl.xml">
  <module name="cache_ctrl" category="WCN">
    <reg protect="rw" name="bus_cfg0">
      <bits access="r" name="bus_cfg0_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_prot_en7" pos="23" rst="0">
        <comment>
          0: block7, protect disabled or access permitted
1: block7, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_prot_en6" pos="22" rst="0">
        <comment>
          0: block6, protect disabled or access permitted
1: block6, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_prot_en5" pos="21" rst="0">
        <comment>
          0: block5, protect disabled or access permitted
1: block5, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_prot_en4" pos="20" rst="0">
        <comment>
          0: block4, protect disabled or access permitted
1: block4, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_prot_en3" pos="19" rst="0">
        <comment>
          0: block3, protect disabled or access permitted
1: block3, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_prot_en2" pos="18" rst="0">
        <comment>
          0: block2, protect disabled or access permitted
1: block2, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_prot_en1" pos="17" rst="0">
        <comment>
          0: block1, protect disabled or access permitted
1: block1, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_prot_en0" pos="16" rst="0">
        <comment>
          0: block0, protect disabled or access permitted
1: block0, protect enabled or access forbidden
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en7" pos="15" rst="0">
        <comment>
          0: block7, cache remap disabled
1: block7, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en6" pos="14" rst="0">
        <comment>
          0: block6, cache remap disabled
1: block6, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en5" pos="13" rst="0">
        <comment>
          0: block5, cache remap disabled
1: block5, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en4" pos="12" rst="0">
        <comment>
          0: block4, cache remap disabled
1: block4, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en3" pos="11" rst="0">
        <comment>
          0: block3, cache remap disabled
1: block3, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en2" pos="10" rst="0">
        <comment>
          0: block2, cache remap disabled
1: block2, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en1" pos="9" rst="0">
        <comment>
          0: block1, cache remap disabled
1: block1, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_remap_en0" pos="8" rst="0">
        <comment>
          0: block0, cache remap disabled
1: block0, cache remap enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en7" pos="7" rst="0">
        <comment>
          0: block7, cache disabled
1: block7, cache enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en6" pos="6" rst="0">
        <comment>
          0: block6, cache disabled
1: block6, cache enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en5" pos="5" rst="0">
        <comment>
          0: block5, cache disabled
1: block5, cache enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en4" pos="4" rst="0">
        <comment>
          0: block4, cache disabled
1: block4, cache enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en3" pos="3" rst="0">
        <comment>
          0: block3, cache disabled
1: block3, cache enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en2" pos="2" rst="0">
        <comment>
          0: block2, cache disabled
1: block2, cache enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en1" pos="1" rst="0">
        <comment>
          0: block1, cache disabled
1: block1, cache enabled
        </comment>
      </bits>
      <bits access="rw" name="rf_blk_cache_en0" pos="0" rst="0">
        <comment>
          0: block0, cache disabled
1: block0, cache enabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bus_cfg1">
      <bits access="r" name="bus_cfg1_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_base_addr1" pos="27:12" rst="0">
        <comment>
          block 1 start address
        </comment>
      </bits>
      <bits access="r" name="bus_cfg1_reserved_1" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_cfg2">
      <bits access="r" name="bus_cfg2_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_base_addr2" pos="27:12" rst="0">
        <comment>
          block 2 start address
        </comment>
      </bits>
      <bits access="r" name="bus_cfg2_reserved_1" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_cfg3">
      <bits access="r" name="bus_cfg3_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_base_addr3" pos="27:12" rst="0">
        <comment>
          block 3 start address
        </comment>
      </bits>
      <bits access="r" name="bus_cfg3_reserved_1" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_cfg4">
      <bits access="r" name="bus_cfg4_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_base_addr4" pos="27:12" rst="0">
        <comment>
          block 4 start address
        </comment>
      </bits>
      <bits access="r" name="bus_cfg4_reserved_1" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_cfg5">
      <bits access="r" name="bus_cfg5_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_base_addr5" pos="27:12" rst="0">
        <comment>
          block 5 start address
        </comment>
      </bits>
      <bits access="r" name="bus_cfg5_reserved_1" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_cfg6">
      <bits access="r" name="bus_cfg6_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_base_addr6" pos="27:12" rst="0">
        <comment>
          block 6 start address
        </comment>
      </bits>
      <bits access="r" name="bus_cfg6_reserved_1" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_cfg7">
      <bits access="r" name="bus_cfg7_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_blk_base_addr7" pos="27:12" rst="0">
        <comment>
          block 7 start address
        </comment>
      </bits>
      <bits access="r" name="bus_cfg7_reserved_1" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap0">
      <bits access="rw" name="rf_blk0_remap_offset0" pos="31:12" rst="0">
        <comment>
          block 0 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk0_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap0_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap1">
      <bits access="rw" name="rf_blk1_remap_offset1" pos="31:12" rst="0">
        <comment>
          block 1 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk1_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap1_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap2">
      <bits access="rw" name="rf_blk2_remap_offset2" pos="31:12" rst="0">
        <comment>
          block 2 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk2_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap2_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap3">
      <bits access="rw" name="rf_blk3_remap_offset3" pos="31:12" rst="0">
        <comment>
          block 3 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk3_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap3_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap4">
      <bits access="rw" name="rf_blk4_remap_offset4" pos="31:12" rst="0">
        <comment>
          block 4 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk4_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap4_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap5">
      <bits access="rw" name="rf_blk5_remap_offset5" pos="31:12" rst="0">
        <comment>
          block 5 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk5_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap5_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap6">
      <bits access="rw" name="rf_blk6_remap_offset6" pos="31:12" rst="0">
        <comment>
          block 6 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk6_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap6_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="bus_remap7">
      <bits access="rw" name="rf_blk7_remap_offset7" pos="31:12" rst="0">
        <comment>
          block 7 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk7_remap_offset
        </comment>
      </bits>
      <bits access="r" name="bus_remap7_reserved_0" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="cache_cfg0">
      <bits access="rw" name="rf_debug_en" pos="31" rst="0">
        <comment>
          cache debug mode enable: 
0: normal mode
1: debug mode
This bit MUST always be cleared during cache operating 
        </comment>
      </bits>
      <bits access="rw" name="rf_cmd_exec_mode" pos="30" rst="0">
        <comment>
          0: (recommended) software can run in cacheable region during software command processing
1: software cannot run in cacheable region during software command processing
        </comment>
      </bits>
      <bits access="rw" name="rf_cache_size_sel" pos="29:28" rst="0">
        <comment>
          cache size selection: 
0: 4K Byte
1: 8K Byte
2: 16K Byte
3: 32K Byte
        </comment>
      </bits>
      <bits access="r" name="cache_cfg0_reserved_0" pos="27:14" rst="0">
      </bits>
      <bits access="rw" name="rf_hprot_cache_reg" pos="13:10" rst="11">
        <comment>
          hprot control register which provide 4bit hprot for cache ctrl AHB?
        </comment>
      </bits>
      <bits access="rw" name="rf_hprot_bus_reg" pos="9:6" rst="3">
        <comment>
          hprot control register which provide 4bit hprot for cache bus AHB
        </comment>
      </bits>
      <bits access="rw" name="rf_hprot_byp" pos="5:2" rst="0">
        <comment>
          Bit [5]: 
1'b1: hprot[3] from CM4 go through cache controller without modification
1'b0: hprot[3] is provided by cache controller register
Bit [4]: 
1'b1: hprot[2] from CM4 go through cache controller without modification
1'b0: hprot[2] is provided by cache controller register
Bit [3]: 
1'b1: hprot[1] from CM4 go through cache controller without modification
1'b0: hprot[1] is provided by cache controller register
Bit [2]: 
1'b1: hprot[0] from CM4 go through cache controller without modification
1'b0: hprot[0] is provided by cache controller register
        </comment>
      </bits>
      <bits access="rw" name="rf_write_mode" pos="1:0" rst="0">
        <comment>
          cache write operation mode
2'b00: write through
2'b01: write back, no write allocate
2'b10: write back, write allocate
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="bus_sts0">
      <bits access="r" name="bus_sts0_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="r" name="rf_prot_detect_addr" pos="27:0" rst="0">
        <comment>
          trigging address for protect block?
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="cache_sts0">
      <bits access="r" name="cache_sts0_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="r" name="rf_write_ongoing" pos="7" rst="0">
        <comment>
          rf_write_ongoing, this is a status register for write through mode to avoid potential coherence issue.
1'b1: the cache is still doing AHB write transaction to the main memory and the data is not written into the main memory.
1'b0: the cache has finished AHB write transaction and the data is written into the main memory. 
        </comment>
      </bits>
      <bits access="r" name="rf_cmd_st" pos="6:4" rst="0">
        <comment>
          rf_cmd_st
        </comment>
      </bits>
      <bits access="r" name="rf_cache_st" pos="3:0" rst="0">
        <comment>
          rf_cache_st
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="cmd_cfg0">
      <bits access="r" name="cmd_cfg0_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_cmd_str_addr" pos="27:0" rst="0">
        <comment>
          cmd_all : not used
cmd_range : start address
cmd_entry : entry address
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="cmd_cfg1">
      <bits access="r" name="cmd_cfg1_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="rf_cmd_end_addr" pos="27:0" rst="0">
        <comment>
          cmd_all : not used
cmd_range : start address
cmd_entry : entry address
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="cmd_cfg2">
      <bits access="w" name="rf_cmd_str" pos="31" rst="0">
        <comment>
          software command start: 
write 1 to this bit to issue one command 
        </comment>
      </bits>
      <bits access="r" name="cmd_cfg2_reserved_0" pos="30:6" rst="0">
      </bits>
      <bits access="rw" name="rf_cmd_type" pos="5:0" rst="0">
        <comment>
          software command type:
6'h0 : clean all
6'h1 : clean range
6'h2 : clean entry
6'h3 : reserved
6'h4 : invalid all
6'h5 : invalid range
6'h6 : invalid entry
6'h7 : reserved
6'h8 : clean and invalid all
6'h9 : clean and invalid range
6'hA : clean and invalid entry
6'hB : reserved 
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="int_en">
      <bits access="r" name="int_en_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="rw" name="rf_prot_irq_en" pos="1" rst="0">
        <comment>
          interrupt enable for protect block trigging?
        </comment>
      </bits>
      <bits access="rw" name="rf_cmd_irq_en" pos="0" rst="0">
        <comment>
           interrupt enable for software command done
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="int_raw">
      <bits access="r" name="int_raw_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="rf_prot_irq_raw" pos="1" rst="0">
        <comment>
          interrupt raw status for protect block trigging
        </comment>
      </bits>
      <bits access="r" name="rf_cmd_irq_raw" pos="0" rst="0">
        <comment>
          interrupt raw status for software command done?
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="int_mask">
      <bits access="r" name="int_mask_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="rf_prot_irq_mask" pos="1" rst="0">
        <comment>
          interrupt masked status for protect block trigging
        </comment>
      </bits>
      <bits access="r" name="rf_cmd_irq_mask" pos="0" rst="0">
        <comment>
          interrupt masked status for software command done?
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="int_clr">
      <bits access="r" name="int_clr_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="w" name="rf_prot_irq_clr" pos="1" rst="0">
        <comment>
          interrupt clear for protect block trigging
        </comment>
      </bits>
      <bits access="w" name="rf_cmd_irq_clr" pos="0" rst="0">
        <comment>
          interrupt clear for software command done?
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="cache_write_hit_cnt">
      <bits access="r" name="rf_write_hit_cnt" pos="31:0" rst="0">
        <comment>
          Cache write hit times. When cache write hit, the counter value increment by 1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="cache_write_miss_cnt">
      <bits access="w" name="rf_write_cnt_clr" pos="31" rst="0">
        <comment>
          clear write counter values to zero?
        </comment>
      </bits>
      <bits access="rw" name="rf_write_cnt_run" pos="30" rst="0">
        <comment>
          1: write hit/miss counter will run
0: write hit/miss counter will stop 
        </comment>
      </bits>
      <bits access="r" name="rf_write_miss_cnt" pos="29:0" rst="0">
        <comment>
          Cache write hit times. When cache write hit, the counter value increment by 1
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="cache_read_hit_cnt">
      <bits access="r" name="rf_read_hit_cnt" pos="31:0" rst="0">
        <comment>
          Cache read hit times. When cache read hit, the counter value increment by 1?
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="cache_read_miss_cnt">
      <bits access="w" name="rf_read_cnt_clr" pos="31" rst="0">
        <comment>
          clear read counter values to zero?
        </comment>
      </bits>
      <bits access="rw" name="rf_read_cnt_run" pos="30" rst="0">
        <comment>
          1: read hit/miss counter will run
0: read hit/miss counter will stop 
        </comment>
      </bits>
      <bits access="r" name="rf_read_miss_cnt" pos="29:0" rst="0">
        <comment>
          Cache read miss times. When cache read miss, the counter value increment by 1
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="cache_hact_cnt">
      <bits access="r" name="rf_hact_cnt" pos="31:0" rst="0">
        <comment>
          Cache master AHB active cycles in total. When master AHB is active (hsel and htrans[1]), the counter value increment by 1?
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="cache_hrdy_cnt">
      <bits access="w" name="rf_hact_hrdy_clr" pos="31" rst="0">
        <comment>
          clear HACT and HRDY counter values to zero
        </comment>
      </bits>
      <bits access="rw" name="rf_hact_hrdy_run" pos="30" rst="0">
        <comment>
          1: HACT and HRDY counters will run
0: HACT and HRDY counters will stop 
        </comment>
      </bits>
      <bits access="r" name="rf_hrdys_cnt" pos="29:0" rst="0">
        <comment>
          The HRDY counter counts the valid cycles of HREADY signal from the cache controller to the master when the master AHB is active. When HREADY signal to the master is high and the master AHB is active, the counter value increment by 1?
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="fm_dsp.xml">
  <module name="fm_dsp" category="WCN">
    <reg protect="r" name="tx_fifo_rdata">
      <bits access="r" name="tx_data_i" pos="31:16" rst="0">
        <comment>
          TX data I. Everytime this register is read, the data will be popped out of the tx_data_fifo.
        </comment>
      </bits>
      <bits access="r" name="tx_data_q" pos="15:0" rst="0">
        <comment>
          TX data Q. Everytime this register is read, the data will be popped out of the tx_data_fifo.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="revision">
      <bits access="r" name="revision_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="r" name="rev_id" pos="3:0" rst="1">
        <comment>
          revision id.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ctrl">
      <bits access="rw" name="output_sel" pos="31" rst="0">
        <comment>
          output to codec selection.
1'h0:: 84K
1'h1:: 48K
        </comment>
      </bits>
      <bits access="rw" name="dbg_out_sel" pos="30:29" rst="0">
        <comment>
          debug output selection.
2'h0:: sinc1
2'd1:: stereo_baseband
2'd2:: lrout
3'd3:: lr_rcout
        </comment>
      </bits>
      <bits access="rw" name="dbg_out_en" pos="28" rst="0">
        <comment>
          debug output enable.
        </comment>
      </bits>
      <bits access="rw" name="adc_data_format" pos="27" rst="0">
        <comment>
          1'h0:: unsigned
1'd1:: 2s_complementary
        </comment>
      </bits>
      <bits access="rw" name="force_clk_on" pos="26" rst="0">
        <comment>
          force clock on.
        </comment>
      </bits>
      <bits access="rw" name="tx_en" pos="25" rst="0">
        <comment>
          tx data enable.
1'h0:: disable
1'd1:: enable
        </comment>
      </bits>
      <bits access="rw" name="i2s_delay_1t" pos="24" rst="0">
        <comment>
          i2s delay 1t enable.
        </comment>
      </bits>
      <bits access="rw" name="i2s_en" pos="23" rst="0">
        <comment>
          i2s enable.
1'h0:: disable
1'd1:: enable
        </comment>
      </bits>
      <bits access="rw" name="fmdem_src_sel" pos="22" rst="1">
        <comment>
          coherent fmdemsource selection.
1'h0:: output_lpfil
1'd1:: output_dig_gain
        </comment>
      </bits>
      <bits access="rw" name="seek_offset_src_sel" pos="21" rst="0">
        <comment>
          offset source selection.
1'h0:: output_afc
1'd1:: output_offset_filter
        </comment>
      </bits>
      <bits access="rw" name="seek_rssi_src_sel" pos="20" rst="1">
        <comment>
          rssi source during seek seelction.
1'h0:: rssi_db1
1'd1:: signal_db1
        </comment>
      </bits>
      <bits access="rw" name="noise_cancel_src_sel" pos="19" rst="0">
        <comment>
          noise cancel source source selection.
1'h0:: noise_db2
1'd1:: rssi_db2
        </comment>
      </bits>
      <bits access="rw" name="noise_src_sel" pos="18:17" rst="2">
        <comment>
          noise source selection.
2'h0:: dangle0
2'd1:: dangle1
2'd2:: dangle 2
        </comment>
      </bits>
      <bits access="rw" name="adc_clk_invert" pos="16" rst="1">
        <comment>
          adc clock invert.
        </comment>
      </bits>
      <bits access="rw" name="pilot_cosine" pos="15" rst="0">
        <comment>
          pilot phase.
1'h0:: sin
1'd1:: cos
        </comment>
      </bits>
      <bits access="rw" name="deemph_bypass" pos="14" rst="0">
        <comment>
          bypass deemphasis.
        </comment>
      </bits>
      <bits access="rw" name="lpf_bypass" pos="13" rst="0">
        <comment>
          bypass 15KHz LPF.
        </comment>
      </bits>
      <bits access="rw" name="fircut_bypass_sk" pos="12" rst="0">
        <comment>
          bypass fircut during seeking.
        </comment>
      </bits>
      <bits access="rw" name="fircut_bypass" pos="11" rst="0">
        <comment>
          bypass fircut.
        </comment>
      </bits>
      <bits access="rw" name="lr_swap" pos="10" rst="0">
        <comment>
          LR swap.
        </comment>
      </bits>
      <bits access="rw" name="plldem_swap" pos="9" rst="0">
        <comment>
          IQ swap for fmdem.
        </comment>
      </bits>
      <bits access="rw" name="iq_swap" pos="8" rst="0">
        <comment>
          IQ swap after 125KHz mixer.
        </comment>
      </bits>
      <bits access="rw" name="imgrej_dsp" pos="7" rst="0">
        <comment>
          IQ swap before 125KHz mixer.
        </comment>
      </bits>
      <bits access="rw" name="imgrej" pos="6" rst="0">
        <comment>
          lo selection.
1'h0:: low
low if; Default is +125KHz.
1'd1:: high
high if. Default is -125KHz
        </comment>
      </bits>
      <bits access="rw" name="afc_disable" pos="5" rst="0">
        <comment>
          AFC disable.
1'h0:: enable
1'd1:: disable
        </comment>
      </bits>
      <bits access="rw" name="softblend_off" pos="4" rst="0">
        <comment>
          soft blend off.
1'h0:: enable
1'd1:: disable
        </comment>
      </bits>
      <bits access="rw" name="softmute_en" pos="3" rst="0">
        <comment>
          soft mute enable.
1'h0:: disable
1'd1:: enable
        </comment>
      </bits>
      <bits access="rw" name="deemph_mode" pos="2" rst="0">
        <comment>
          de-emphasis.
1'h0:: 75us
1'd1:: 50us
        </comment>
      </bits>
      <bits access="rw" name="stereo_in" pos="1" rst="1">
        <comment>
          mono select.
1'h0:: force : mono
1'd1:: stereo
        </comment>
      </bits>
      <bits access="rw" name="mute" pos="0" rst="1">
        <comment>
          mute.
1'h0:: normal
1'd1:: mute
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="tx_ctrl">
      <bits access="r" name="tx_ctrl_reserved_0" pos="31:11" rst="0">
      </bits>
      <bits access="r" name="tx_fifo_usedw" pos="10:8" rst="0">
        <comment>
          the number of data words in tx fifowhich are valid for read.
        </comment>
      </bits>
      <bits access="r" name="tx_fifo_underflow" pos="7" rst="0">
        <comment>
          tx fifo underflow. User reads tx_fifo_rdata while no data valid in it.
        </comment>
      </bits>
      <bits access="r" name="tx_fifo_overflow" pos="6" rst="0">
        <comment>
          tx fifo overflow. User is not able to read tx_fifo_rdata in time so that fm_dsp discard valid data.
        </comment>
      </bits>
      <bits access="rw" name="tx_fifo_clr" pos="5" rst="0">
        <comment>
          clear tx fifo.
        </comment>
      </bits>
      <bits access="rw" name="tx_sel" pos="4:0" rst="0">
        <comment>
          tx data selection.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="seek_ctrl0">
      <bits access="r" name="seek_ctrl0_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="snr_cnt_th" pos="29:26" rst="5">
        <comment>
          SNR counter threshold.
        </comment>
      </bits>
      <bits access="rw" name="delta_rssi_th" pos="25:20" rst="12">
        <comment>
          delta rssi threshold during UPPER/LOWER seeking. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="snr_th" pos="19:14" rst="18">
        <comment>
          threshold for SNR. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="seek_range" pos="13:9" rst="20">
        <comment>
          seek upper/lower adjacent freq setting. Unit is 5.12KHz.
        </comment>
      </bits>
      <bits access="rw" name="seek_afc_on" pos="8" rst="1">
        <comment>
          1'h0:: disable
disable afc during seeking;
1'd1:: enable
enable afc during seeking.
        </comment>
      </bits>
      <bits access="rw" name="seek_mode" pos="7:5" rst="0">
        <comment>
          seek mode.
3'h0:: seek_current_only
3'd1:: seek_current_or_adjacent
success when either current or adjacent freq is successful;
3'd2:: seek_current_and_adjacent
success when both current and adjacent freq are successful;
3'd3:: snr_st
test mode. stop at SNR_ST;
3'd4:: center_st
test mode. stop at CENTER_ST;
3'h5:: upper_st
test mode. stop at UPPER_ST;
3'd6:: lower_st
testmode. stop at LOWER_ST;
3'd7:: seek_bypass
        </comment>
      </bits>
      <bits access="rw" name="sk_cmp_grp_en" pos="4:0" rst="27">
        <comment>
          1'h0: disable
1'd1: enable
[4]: seek with  pilot;
[3]: seek with offset;
[2]: seek with snr;
[1]: seek with rssi;
[0]: seek with noise.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="seek_ctrl1">
      <bits access="rw" name="pilot_cnt_th" pos="31:24" rst="50">
        <comment>
          pilot counter threshold.
        </comment>
      </bits>
      <bits access="rw" name="rssi_cnt_th" pos="23:16" rst="50">
        <comment>
          rssi counter threshold.
        </comment>
      </bits>
      <bits access="rw" name="noise_cnt_th" pos="15:8" rst="50">
        <comment>
          noise counter threshold.
        </comment>
      </bits>
      <bits access="rw" name="offset_cnt_th" pos="7:0" rst="50">
        <comment>
          offset counter threshold.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="seek_ctrl2">
      <bits access="r" name="seek_ctrl2_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="noise_l_th" pos="27:21" rst="70">
        <comment>
          noise low threshold. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="noise_h_th" pos="20:14" rst="70">
        <comment>
          noise high threshold. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="rssi_l_th" pos="13:7" rst="15">
        <comment>
          RSSI low threshold. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="rssi_h_th" pos="6:0" rst="20">
        <comment>
          RSSI high threshold. Unit is db.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="seek_ctrl3">
      <bits access="r" name="seek_ctrl3_reserved_0" pos="31:28" rst="0">
      </bits>
      <bits access="rw" name="offset_l_th" pos="27:21" rst="16">
        <comment>
          offset low threshold. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="offset_h_th" pos="20:14" rst="25">
        <comment>
          offset high threshold. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="pilot_l_th" pos="13:7" rst="6">
        <comment>
          pilot low threshold. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="pilot_h_th" pos="6:0" rst="10">
        <comment>
          pilot high threshold. Unit is db.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="seek_ctrl4">
      <bits access="r" name="seek_ctrl4_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="rw" name="sk_timer4" pos="21:16" rst="40">
        <comment>
          seek time for SNR detect. Unit is 0.75ms.
        </comment>
      </bits>
      <bits access="rw" name="sk_timer3" pos="15:10" rst="5">
        <comment>
          seek time for upper/lower adjacent freq. Unit is 0.75ms.
        </comment>
      </bits>
      <bits access="rw" name="sk_timer2" pos="9:4" rst="7">
        <comment>
          seek time for current freq. Unit is 0.75ms.
        </comment>
      </bits>
      <bits access="rw" name="sk_timer1" pos="3:0" rst="2">
        <comment>
          seek time for agc/afc stable. Unit is 0.75ms.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="afc_ctrl">
      <bits access="r" name="afc_ctrl_reserved_0" pos="31:19" rst="0">
      </bits>
      <bits access="rw" name="afc_ct_sk" pos="18:13" rst="18">
        <comment>
          [5:3]: afc dc filter bandwidth setting during seeking.
[2:0]: afc acc step setting during seeking.
        </comment>
      </bits>
      <bits access="rw" name="afc_ct" pos="12:7" rst="38">
        <comment>
          [5:3]: afc dc filter bandwidth setting during seek is ready.
[2:0]: afc acc step setting during seek is ready.
        </comment>
      </bits>
      <bits access="rw" name="afc_range" pos="6:1" rst="7">
        <comment>
          afc following range. Unit is 2.5KHz.
        </comment>
      </bits>
      <bits access="rw" name="afc_inv" pos="0" rst="1">
        <comment>
          inverse afc adjust value.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_ctrl0">
      <bits access="r" name="agc_ctrl0_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="agc_target_pwr" pos="30:25" rst="38">
        <comment>
          agc target power. Unit is 2db.
        </comment>
      </bits>
      <bits access="rw" name="agc_test" pos="24" rst="0">
        <comment>
          agc test mode. Fix gain.
        </comment>
      </bits>
      <bits access="rw" name="agc_loop_gain1" pos="23:21" rst="4">
        <comment>
          agc loop gain during normal.
        </comment>
      </bits>
      <bits access="rw" name="agc_loop_gain0" pos="20:18" rst="7">
        <comment>
          agc loop gian during seeking.
        </comment>
      </bits>
      <bits access="rw" name="agc_update1" pos="17:15" rst="4">
        <comment>
          agc update time during normal.
        </comment>
      </bits>
      <bits access="rw" name="agc_update0" pos="14:12" rst="0">
        <comment>
          agc update time during seeking.
        </comment>
      </bits>
      <bits access="rw" name="agc_thd" pos="11:7" rst="16">
        <comment>
          agc digital gain threshold. Unit is 2db.
        </comment>
      </bits>
      <bits access="rw" name="agc_index_in" pos="6:3" rst="15">
        <comment>
          agc initial index.
        </comment>
      </bits>
      <bits access="rw" name="ct_endelay" pos="2:0" rst="4">
        <comment>
          agc enable delay time after reset.
3'h0:: 0 : 0.375us
3'd1:: 1 : 3us
3'd2:: 2 : 6us
3'd3:: 3 : 9.74us
3'd4:: 4 : 13.875us
3'd5:: 5 : 18us
3'd6:: 6 : 21us
3'd7: 7 : 24us
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="agc_ctrl1">
      <bits access="r" name="agc_ctrl1_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="rw" name="dig_gain_in" pos="19:15" rst="0">
        <comment>
          basic dig gain. Unit is db.
        </comment>
      </bits>
      <bits access="rw" name="agc_ct_u" pos="14:13" rst="1">
        <comment>
          agc IIR bandwidth.
        </comment>
      </bits>
      <bits access="rw" name="over_step" pos="12:7" rst="34">
        <comment>
          [5:3]: agc loop sub step when sinc_over or log_agc&gt;log_agc_th
[2:0]: agc loop sub step when acc I saturation.
        </comment>
      </bits>
      <bits access="rw" name="log_agc_th" pos="6:1" rst="60">
        <comment>
          threshold for agc lopp adjust. Unit is 1db.
        </comment>
      </bits>
      <bits access="rw" name="log_over_sel" pos="0" rst="1">
        <comment>
          if 1, adjust agc_index sub step when log_agc&gt;log_agc_th
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ana_gain_rssi_tb0">
      <bits access="rw" name="ana_gain_rssi_3" pos="31:24" rst="234">
        <comment>
          ana gain rssi for agc_index=3
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_2" pos="23:16" rst="244">
        <comment>
          ana gain rssi for agc_index=2
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_1" pos="15:8" rst="0">
        <comment>
          ana gain rssi for agc_index=1
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_0" pos="7:0" rst="0">
        <comment>
          ana gain rssi for agc_index=0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ana_gain_rssi_tb1">
      <bits access="rw" name="ana_gain_rssi_7" pos="31:24" rst="18">
        <comment>
          ana gain rssi for agc_index=7
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_6" pos="23:16" rst="12">
        <comment>
          ana gain rssi for agc_index=6
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_5" pos="15:8" rst="6">
        <comment>
          ana gain rssi for agc_index=5
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_4" pos="7:0" rst="0">
        <comment>
          ana gain rssi for agc_index=4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ana_gain_rssi_tb2">
      <bits access="rw" name="ana_gain_rssi_b" pos="31:24" rst="42">
        <comment>
          ana gain rssi for agc_index=b
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_a" pos="23:16" rst="36">
        <comment>
          ana gain rssi for agc_index=a
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_9" pos="15:8" rst="30">
        <comment>
          ana gain rssi for agc_index=9
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_8" pos="7:0" rst="24">
        <comment>
          ana gain rssi for agc_index=8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="ana_gain_rssi_tb3">
      <bits access="rw" name="ana_gain_rssi_f" pos="31:24" rst="66">
        <comment>
          ana gain rssi for agc_index=f
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_e" pos="23:16" rst="60">
        <comment>
          ana gain rssi for agc_index=e
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_d" pos="15:8" rst="54">
        <comment>
          ana gain rssi for agc_index=d
        </comment>
      </bits>
      <bits access="rw" name="ana_gain_rssi_c" pos="7:0" rst="48">
        <comment>
          ana gain rssi for agc_index=c
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="noise_cancel_ctrl0">
      <bits access="r" name="noise_cancel_ctrl0_reserved_0" pos="31:29" rst="0">
      </bits>
      <bits access="rw" name="th_min_bw" pos="28:22" rst="16">
        <comment>
          fircut/gain38k change low threshold for RSSI. Unit is 1db.
        </comment>
      </bits>
      <bits access="rw" name="th_max_bw" pos="21:15" rst="24">
        <comment>
          fircut/gain38k change high threshold for RSSI. Unit is 1db.
        </comment>
      </bits>
      <bits access="rw" name="plldem_th_min" pos="14:9" rst="31">
        <comment>
          threshold. Unit is 2db.
        </comment>
      </bits>
      <bits access="rw" name="plldem_th_max" pos="8:3" rst="34">
        <comment>
          threshold. Unit is 2db.
        </comment>
      </bits>
      <bits access="rw" name="fmdem_sel_grp" pos="2:0" rst="0">
        <comment>
          1'h0: select cordic fmdem
1'd1: select dpll fmdem.
[2]: for seeing;
[1]: for nosie&lt;th_min;
[0]: for noise&gt;th_max.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="noise_cancel_ctrl1">
      <bits access="r" name="noise_cancel_ctrl1_reserved_0" pos="31:22" rst="0">
      </bits>
      <bits access="rw" name="fircut_sel_force_on" pos="21" rst="0">
        <comment>
          fircut/gain38k change force on
        </comment>
      </bits>
      <bits access="rw" name="sel_fircut_sk" pos="20:15" rst="9">
        <comment>
          fircut bandwidth select during seeking UPPER/LOWER[2:0] and CENTER[5:3]. [40KHz:20KHz:180KHz]
        </comment>
      </bits>
      <bits access="rw" name="sel_fircut3" pos="14:12" rst="4">
        <comment>
          fircut bandwidth select during seeready and bad conditiong. Offset is over th. CENTER. [40KHz:20KHz:180KHz]
        </comment>
      </bits>
      <bits access="rw" name="sel_fircut2" pos="11:9" rst="4">
        <comment>
          fircut bandwidth select during seek ready and bad condition.  Offset is under th. [40KHz:20KHz:180KHz]
        </comment>
      </bits>
      <bits access="rw" name="sel_fircut1" pos="8:6" rst="7">
        <comment>
          fircut bandwidth select during seek ready and good condition. [40KHz:20KHz:180KHz]
        </comment>
      </bits>
      <bits access="rw" name="th_min_hcc" pos="5:0" rst="32">
        <comment>
          bandwidth threshold. Unit is 2db
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="noise_cancel_ctrl2">
      <bits access="rw" name="gain_38k2" pos="31:16" rst="20045">
        <comment>
          gain for L-R base band signal. U1.15
        </comment>
      </bits>
      <bits access="rw" name="gain_38k1" pos="15:0" rst="20045">
        <comment>
          gain for L-R base band signal. U1.15
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="datapath_ctrl0">
      <bits access="r" name="datapath_ctrl0_reserved_0" pos="31:29" rst="0">
      </bits>
      <bits access="rw" name="sinc1_bit_shift" pos="28:26" rst="0">
      </bits>
      <bits access="rw" name="hbf1_bypass" pos="25" rst="0">
      </bits>
      <bits access="rw" name="hbf2_bypass" pos="24" rst="0">
      </bits>
      <bits access="rw" name="mpx_gain" pos="23:21" rst="2">
        <comment>
          gain for mpx signal.
        </comment>
      </bits>
      <bits access="rw" name="stereo_gain" pos="20:15" rst="6">
        <comment>
          gain for stereo. [5:3]:6db;[2:1]:2db;[0]:1db.
        </comment>
      </bits>
      <bits access="rw" name="dig_delayct" pos="14:10" rst="10">
        <comment>
          dig gain change delay setting. Unit is 0.375us
        </comment>
      </bits>
      <bits access="rw" name="sinc_limit_gain" pos="9:8" rst="0">
        <comment>
          dig gain for signal before 125KHz mixer. 
2'h0:: 0db
2'd1:: 6db
2'd2:: 12db
3'd3:: 18db
        </comment>
      </bits>
      <bits access="rw" name="over_th_sel" pos="7:5" rst="4">
        <comment>
          [2]: enable over threshold detection.
[1:0]: over threshold selection.
2'h0:: 0 : 0.75
2'd1:: 1 : 0.9
2'd2:: 2 : 0.95
2'd3:: 3 : 1
        </comment>
      </bits>
      <bits access="rw" name="limit_sel" pos="4" rst="1">
        <comment>
          1'h0: *0.75
1'd1: *1
for sinc_limit.
        </comment>
      </bits>
      <bits access="rw" name="dc_ct" pos="3:0" rst="11">
        <comment>
          dc cancel control.
[3]: dccancel mode. 1'h0: bypass; 1'd1: enable
[2:0]: bandwidth.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="datapath_ctrl1">
      <bits access="r" name="datapath_ctrl1_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="nco_ct_u_dt" pos="30:28" rst="6">
        <comment>
          19kHz tone detect bandwidthduring normal.
        </comment>
      </bits>
      <bits access="rw" name="nco_ct_u_dt_sk" pos="27:25" rst="3">
        <comment>
          19kHz tone detect bandwidth during seeking.
        </comment>
      </bits>
      <bits access="rw" name="nco_ct_bw" pos="24:21" rst="10">
        <comment>
          nco 2ord bandwidth.
        </comment>
      </bits>
      <bits access="rw" name="nco_ct_u" pos="20:18" rst="2">
        <comment>
          nco dc bandwidth.
        </comment>
      </bits>
      <bits access="rw" name="softmute_th1" pos="17:12" rst="34">
        <comment>
          softmute threshold for RSSI.
        </comment>
      </bits>
      <bits access="rw" name="softmute_th2" pos="11:6" rst="20">
        <comment>
          softmute threshold for noise.
        </comment>
      </bits>
      <bits access="rw" name="softmute_th3" pos="5:0" rst="5">
        <comment>
          softmute threshold for SNR.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="datapath_ctrl2">
      <bits access="rw" name="softmute_th4" pos="31:26" rst="52">
        <comment>
          softmute threshold for offset.
        </comment>
      </bits>
      <bits access="rw" name="sm_rate" pos="25:24" rst="1">
        <comment>
          softmute rate. Fast-&gt;slow.
        </comment>
      </bits>
      <bits access="rw" name="sm_attenu" pos="23:20" rst="15">
        <comment>
          softmute attenu setting.
        </comment>
      </bits>
      <bits access="rw" name="th_softblend1" pos="19:14" rst="20">
        <comment>
          softblend threshold for RSSI.
        </comment>
      </bits>
      <bits access="rw" name="th_softblend2" pos="13:8" rst="34">
        <comment>
          softblend threshold for noise.
        </comment>
      </bits>
      <bits access="rw" name="offset_flt_ct_u" pos="7:6" rst="2">
        <comment>
          offset filter bandwidth.
        </comment>
      </bits>
      <bits access="rw" name="lpf_bw_dr" pos="5" rst="0">
      </bits>
      <bits access="rw" name="lpf_bw_reg" pos="4:2" rst="0">
      </bits>
      <bits access="rw" name="deemph_hcc" pos="1:0" rst="3">
        <comment>
          direct deemphasis hcc reg.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="datapath_ctrl3">
      <bits access="r" name="datapath_ctrl3_reserved_0" pos="31" rst="0">
      </bits>
      <bits access="rw" name="step19k_reg" pos="30:16" rst="14942">
        <comment>
          step 19k value
        </comment>
      </bits>
      <bits access="rw" name="interval_reg" pos="15:0" rst="12288">
        <comment>
          interval value
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="datapath_ctrl4">
      <bits access="r" name="datapath_ctrl4_reserved_0" pos="31:23" rst="0">
      </bits>
      <bits access="rw" name="notch_flt_bypass" pos="22" rst="1">
      </bits>
      <bits access="rw" name="notch_flt_ka" pos="21:20" rst="3">
      </bits>
      <bits access="rw" name="notch_flt_z0_i" pos="19:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="datapath_ctrl5">
      <bits access="r" name="datapath_ctrl5_reserved_0" pos="31:20" rst="0">
      </bits>
      <bits access="rw" name="notch_flt_z0_q" pos="19:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="log_ctrl0">
      <bits access="r" name="log_ctrl0_reserved_0" pos="31:24" rst="0">
      </bits>
      <bits access="rw" name="ct_u_noise" pos="23:18" rst="28">
        <comment>
          [5:3]: noise_db1 bandwidth
[2:0]: noise_db2 bandwidth
        </comment>
      </bits>
      <bits access="rw" name="ct_u_signal" pos="17:12" rst="28">
        <comment>
          [5:3]: signal_db1 bandwidth
[2:0]: signal_db2 bandwidth
        </comment>
      </bits>
      <bits access="rw" name="ct_u_rssi" pos="11:6" rst="28">
        <comment>
          [5:3]: rssi_db1 bandwidth
[2:0]: rssi_db2 bandwidth
        </comment>
      </bits>
      <bits access="rw" name="ct_u_pilot" pos="5:0" rst="28">
        <comment>
          [5:3]: pilot_db1 bandwidth
[2:0]: pilot_db2 bandwitdh
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="status0">
      <bits access="r" name="status0_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="r" name="seek_ready" pos="29" rst="0">
      </bits>
      <bits access="r" name="seek_done" pos="28" rst="0">
      </bits>
      <bits access="r" name="rssi_db2" pos="27:21" rst="0">
        <comment>
          rssi. Unit is db.
        </comment>
      </bits>
      <bits access="r" name="snr_out" pos="20:15" rst="0">
        <comment>
          snr. Unit is db.
        </comment>
      </bits>
      <bits access="r" name="signal_db2" pos="14:8" rst="0">
        <comment>
          signal. Unit is db.
        </comment>
      </bits>
      <bits access="r" name="offset2" pos="7:0" rst="0">
        <comment>
          frequency offset. Unit is db.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="status1">
      <bits access="r" name="status1_reserved_0" pos="31:29" rst="0">
      </bits>
      <bits access="r" name="noise_db2" pos="28:22" rst="0">
      </bits>
      <bits access="r" name="snr19k_out" pos="21:16" rst="0">
      </bits>
      <bits access="r" name="pilot_db2" pos="15:9" rst="0">
      </bits>
      <bits access="r" name="sk_cmp_grp_flag" pos="8:4" rst="0">
        <comment>
          [4]: 19k pilot flag
[3]: offset flag
[2]: snr flag
[1]: rssi flag
[0]: noise flag
        </comment>
      </bits>
      <bits access="r" name="snr_cnt" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="status2">
      <bits access="r" name="rssi_cnt" pos="31:24" rst="0">
      </bits>
      <bits access="r" name="noise_cnt" pos="23:16" rst="0">
      </bits>
      <bits access="r" name="pilot_cnt" pos="15:8" rst="0">
      </bits>
      <bits access="r" name="offset_cnt" pos="7:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="status3">
      <bits access="r" name="status3_reserved_0" pos="31:19" rst="0">
      </bits>
      <bits access="r" name="ct_hcc" pos="18:16" rst="0">
      </bits>
      <bits access="r" name="fircut_bw" pos="15:13" rst="1">
      </bits>
      <bits access="r" name="fmdem_sel" pos="12" rst="0">
      </bits>
      <bits access="r" name="dig_gainct" pos="11:4" rst="0">
      </bits>
      <bits access="r" name="agc_index" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="rsvd_reg">
      <bits access="r" name="rsvd_in" pos="31:16" rst="0">
      </bits>
      <bits access="rw" name="rsvd_out" pos="15:0" rst="65280">
      </bits>
    </reg>
  </module>
</archive>
<archive relative="wlan.xml">
  <module name="wlan" category="WCN">
    <hole size="32"/>
    <reg protect="rw" name="phy_reg_bank_addr">
      <bits access="rw" name="phy_reg_bank_addr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="phy_reg_offset_addr">
      <bits access="rw" name="phy_reg_offset_addr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="phy_reg_write_data">
      <bits access="rw" name="phy_reg_write_data" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="phy_reg_read_data">
      <bits access="rw" name="phy_reg_read_data" pos="31:0" rst="135">
      </bits>
    </reg>
    <reg protect="r" name="protocol_version">
      <bits access="r" name="protocol_version_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="protocol_version" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="type">
      <bits access="r" name="type_reserved_0" pos="31:2" rst="0">
      </bits>
      <bits access="r" name="tp" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="sub_type">
      <bits access="r" name="sub_type_reserved_0" pos="31:4" rst="0">
      </bits>
      <bits access="r" name="sub_type" pos="3:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="desaddr_l">
      <bits access="r" name="desaddr_l" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="desaddr_h">
      <bits access="r" name="desaddr_h_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="desaddr_h" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="srcaddr_l">
      <bits access="r" name="srcaddr_l" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="srcaddr_h">
      <bits access="r" name="srcaddr_h_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="srcaddr_h" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="bssidaddr_l">
      <bits access="r" name="bssidaddr_l" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="bssidaddr_h">
      <bits access="r" name="bssidaddr_h_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="desaddr_h" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="seqcontrol">
      <bits access="r" name="seqcontrol_reserved_0" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="seqcontrol" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="rssival">
      <bits access="r" name="rssival_reserved_0" pos="31:8" rst="0">
      </bits>
      <bits access="r" name="rssival" pos="7:0" rst="0">
      </bits>
    </reg>
    <hole size="512"/>
    <reg protect="rw" name="config_reg">
      <bits access="rw" name="config_reg_reserved_0" pos="31:17" rst="0">
      </bits>
      <bits access="rw" name="phyrx_en_b" pos="16" rst="1">
        <comment>
          0: enalbe, 1: disable
        </comment>
      </bits>
      <bits access="rw" name="config_reg_reserved_1" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="type_config_reg" pos="13:12" rst="0">
      </bits>
      <bits access="rw" name="subtype_config_reg" pos="11:8" rst="8">
      </bits>
      <bits access="rw" name="config_reg_reserved_2" pos="7:2" rst="0">
      </bits>
      <bits access="rw" name="apb_hold" pos="1" rst="1">
      </bits>
      <bits access="rw" name="apb_clear" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="r" name="datardyint">
      <bits access="r" name="datardyint_reserved_0" pos="31:1" rst="0">
      </bits>
      <bits access="r" name="datardyint" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set0">
      <bits access="r" name="phy_sel_set0_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_3_reg" pos="29:24" rst="3">
      </bits>
      <bits access="r" name="phy_sel_set0_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_2_reg" pos="21:16" rst="2">
      </bits>
      <bits access="r" name="phy_sel_set0_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_1_reg" pos="13:8" rst="1">
      </bits>
      <bits access="r" name="phy_sel_set0_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_0_reg" pos="5:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set2">
      <bits access="r" name="phy_sel_set2_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_7_reg" pos="29:24" rst="7">
      </bits>
      <bits access="r" name="phy_sel_set2_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_6_reg" pos="21:16" rst="6">
      </bits>
      <bits access="r" name="phy_sel_set2_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_5_reg" pos="13:8" rst="5">
      </bits>
      <bits access="r" name="phy_sel_set2_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_4_reg" pos="5:0" rst="4">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set3">
      <bits access="r" name="phy_sel_set3_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_11_reg" pos="29:24" rst="11">
      </bits>
      <bits access="r" name="phy_sel_set3_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_10_reg" pos="21:16" rst="10">
      </bits>
      <bits access="r" name="phy_sel_set3_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_9_reg" pos="13:8" rst="9">
      </bits>
      <bits access="r" name="phy_sel_set3_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_8_reg" pos="5:0" rst="8">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set4">
      <bits access="r" name="phy_sel_set4_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_15_reg" pos="29:24" rst="15">
      </bits>
      <bits access="r" name="phy_sel_set4_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_14_reg" pos="21:16" rst="14">
      </bits>
      <bits access="r" name="phy_sel_set4_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_13_reg" pos="13:8" rst="13">
      </bits>
      <bits access="r" name="phy_sel_set4_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_12_reg" pos="5:0" rst="12">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set5">
      <bits access="r" name="phy_sel_set5_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_19_reg" pos="29:24" rst="19">
      </bits>
      <bits access="r" name="phy_sel_set5_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_18_reg" pos="21:16" rst="18">
      </bits>
      <bits access="r" name="phy_sel_set5_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_17_reg" pos="13:8" rst="17">
      </bits>
      <bits access="r" name="phy_sel_set5_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_16_reg" pos="5:0" rst="16">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set6">
      <bits access="r" name="phy_sel_set6_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_23_reg" pos="29:24" rst="23">
      </bits>
      <bits access="r" name="phy_sel_set6_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_22_reg" pos="21:16" rst="22">
      </bits>
      <bits access="r" name="phy_sel_set6_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_21_reg" pos="13:8" rst="21">
      </bits>
      <bits access="r" name="phy_sel_set6_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_20_reg" pos="5:0" rst="20">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set7">
      <bits access="r" name="phy_sel_set7_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_27_reg" pos="29:24" rst="27">
      </bits>
      <bits access="r" name="phy_sel_set7_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_26_reg" pos="21:16" rst="26">
      </bits>
      <bits access="r" name="phy_sel_set7_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_25_reg" pos="13:8" rst="25">
      </bits>
      <bits access="r" name="phy_sel_set7_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_24_reg" pos="5:0" rst="24">
      </bits>
    </reg>
    <reg protect="rw" name="phy_sel_set8">
      <bits access="r" name="phy_sel_set8_reserved_0" pos="31:30" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_31_reg" pos="29:24" rst="31">
      </bits>
      <bits access="r" name="phy_sel_set8_reserved_1" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_30_reg" pos="21:16" rst="30">
      </bits>
      <bits access="r" name="phy_sel_set8_reserved_2" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_29_reg" pos="13:8" rst="29">
      </bits>
      <bits access="r" name="phy_sel_set8_reserved_3" pos="7:6" rst="0">
      </bits>
      <bits access="rw" name="phy_sel_28_reg" pos="5:0" rst="28">
      </bits>
    </reg>
  </module>
</archive>

<archive relative="dfe.xml">
  <module name="dfe" category="RF_Dig">
    <reg protect="rw" name="generalmode">
      <bits access="r" name="generalmode_reserved_0" pos="15:11" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dfe_dump_sel" pos="10:8" rst="0">
        <comment>
          Dump source selection.
0: dump RX data from DFE
1: dump TX data from BB
2: dump DFE internal RX path data. It works with rxdp_test_dac_sel_rg register 
3: dump DFE internal TX path data. It works with txdp_test_dac_sel_rg register
others: dump data from LVDS
        </comment>
      </bits>
      <bits access="rw" name="sw_resetn" pos="7:7" rst="1">
        <comment>
          SW controlled reset for RXDP, active low. It takes effect when reset_mode is 0
0: assert reset
1: not reset
        </comment>
      </bits>
      <bits access="rw" name="reset_mode" pos="6:6" rst="0">
        <comment>
          Reset source for RXDP.
0: reset from BB TCU event signal with precise timing control
1: reset from control register
        </comment>
      </bits>
      <bits access="rw" name="bypass_mode" pos="5:5" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="clk_fbc_en_mode" pos="4:4" rst="0">
        <comment>
          PolarIQ mode enable for NB/WT TX
0: PolarIQ disabled
1: PolarIQ enabled
        </comment>
      </bits>
      <bits access="rw" name="tx_mode" pos="3:2" rst="0">
        <comment>
          DFE TX mode.
0: GGE mode
1: NB mode
2: WT mode
        </comment>
      </bits>
      <bits access="rw" name="rx_mode" pos="1:0" rst="0">
        <comment>
          DFE RX mode.
0: GGE mode
1: NB mode
2: WT mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clockgateenable">
      <bits access="r" name="clockgateenable_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="clk_dac_inv_mode" pos="9" rst="0">
        <comment>
          Invert DAC clock or not.
0: clk_dac is not inverted
1: clk_dac is inverted
        </comment>
      </bits>
      <bits access="rw" name="clk_adc_inv_mode" pos="8" rst="0">
        <comment>
          Invert ADC clock or not.
0: clk_adc is not inverted
1: clk_adc is inverted
        </comment>
      </bits>
      <bits access="rw" name="clk_rate_convert_rg" pos="7" rst="0">
        <comment>
          DFE clock shift control.
0: clock shift disabled
1: clock shift enabled. When it is enabled, all DFE clocks except GSM TX clock are working in 17/16 normal frequency
        </comment>
      </bits>
      <bits access="rw" name="clk_26m_en" pos="6" rst="1">
        <comment>
          clock enable for BB GGE 26MHz
        </comment>
      </bits>
      <bits access="rw" name="clk_61p44m_en" pos="5" rst="1">
        <comment>
          clock enable for BB NB/WT 61.44MHz
        </comment>
      </bits>
      <bits access="rw" name="txdp_nb_dfe_clk_en" pos="4" rst="0">
        <comment>
          clock enable for DFE NB/WT TX
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_dfe_clk_en" pos="3" rst="0">
        <comment>
          clock enable for DFE GSM TX
        </comment>
      </bits>
      <bits access="rw" name="rxdp_dfe_clk_en" pos="2" rst="0">
        <comment>
          clock enable for DFE RX
        </comment>
      </bits>
      <bits access="rw" name="txdp_clk_dac_en" pos="1" rst="0">
        <comment>
          clock enable for DFE DAC
        </comment>
      </bits>
      <bits access="rw" name="rxdp_adc_clk_en" pos="0" rst="0">
        <comment>
          clock enable for DFE ADC.
0: clock disabled
1: clock enabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_dcc">
      <bits access="r" name="rxdp_dcc_reserved_0" pos="15:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_dcc_load" pos="6" rst="0">
        <comment>
          Start to load DC value, active high. Before next load, set it low firstly
        </comment>
      </bits>
      <bits access="rw" name="dcc_imgrej_rg" pos="5" rst="0">
        <comment>
          IQ swap in DC module
0: no swap
1. swap
        </comment>
      </bits>
      <bits access="rw" name="dcc_hold_en_rg" pos="4" rst="0">
        <comment>
          Hold DC accumulator calculation in DC calibration mode
        </comment>
      </bits>
      <bits access="rw" name="dcc_bypass_rg" pos="3" rst="0">
        <comment>
          This register is not used. But DC module bypass is actrually controlled by register rxdp_bypass_dcc and rxdp_bypass_mode_dcc
        </comment>
      </bits>
      <bits access="rw" name="dcc_dc_delta_ld_st_rg" pos="2" rst="0">
        <comment>
          Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode.
        </comment>
      </bits>
      <bits access="rw" name="dcc_dc_calib_en_rg" pos="1" rst="0">
        <comment>
          Load DC value in calibration mode to debug port, only used for debug purpose
        </comment>
      </bits>
      <bits access="rw" name="dcc_rx_calib_sel_rg" pos="0" rst="0">
        <comment>
          DC module work mode.
0: DC calibration mode
1: DC cancel mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_dc_calib_re">
      <bits access="rw" name="rxdp_dc_calib_re_rg" pos="15:0" rst="0">
        <comment>
          DC real part value used in cancel mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_dc_calib_im">
      <bits access="rw" name="rxdp_dc_calib_im_rg" pos="15:0" rst="0">
        <comment>
          DC image part value used in cancel mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_dc_delta_re">
      <bits access="rw" name="rxdp_dc_delta_re_rg" pos="15:0" rst="0">
        <comment>
          Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_dc_delta_im">
      <bits access="rw" name="rxdp_dc_delta_im_rg" pos="15:0" rst="0">
        <comment>
          Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_dc_cr">
      <bits access="r" name="rxdp_dc_cr_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="conv_slow_bw_ct_rg" pos="11:9" rst="0">
        <comment>
          Slow convergence control, work with conv_mode_ct_rg register
        </comment>
      </bits>
      <bits access="rw" name="conv_fast_bw_ct_rg" pos="8:6" rst="0">
        <comment>
          Fast convergence control, work with conv_mode_ct_rg register
        </comment>
      </bits>
      <bits access="rw" name="conv_tmr_ct_rg" pos="5:2" rst="0">
        <comment>
          Duration time of DC calibration, which is based on sample unit
        </comment>
      </bits>
      <bits access="rw" name="conv_mode_ct_rg" pos="1:0" rst="0">
        <comment>
          DC convergence loop mode selection.
0: fast
1: slow
2: fast-&gt;slow
3: fast-&gt;hold
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gain_ct_reg">
      <bits access="r" name="rxdp_gain_ct_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_gain_ct" pos="9:0" rst="0">
        <comment>
          Gain BB control. [-24db, 57.875db], step=0.125db
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_rc_strech">
      <bits access="r" name="rxdp_rc_strech_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rc_bypass_rg" pos="11" rst="0">
        <comment>
          This register is not used.
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rc_strech_rg" pos="10:0" rst="32">
        <comment>
          Number of output clock cycles between 2 samples after RX RC
11'h010: GGE
11'h020: NB
11'h140: WT with rxdp_cic2_mode being 2/3
11'h280: WT with rxdp_cic2_mode being 1
11'h500: WT with rxdp_cic2_mode being 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_rc_rate_ofs_period">
      <bits access="r" name="rxdp_rc_rate_ofs_period_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rc_rate_ofs_period_rg" pos="7:0" rst="16">
        <comment>
          Number of output samples, used with clock shift enabled or not.
8'h10: clock shift enable
8'h01: clock shift disable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_rc_rate_ofs_hi">
      <bits access="r" name="rxdp_rc_rate_ofs_hi_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rc_rate_ofs_hi_rg" pos="7:0" rst="128">
        <comment>
          Bit [23:16] of the offset on the downconversion rate, used with clock shift enabled or not.
8'h90: clock shift enable
8'h80: clock shift disable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_rc_rate_ofs_lo">
      <bits access="rw" name="rxdp_rc_rate_ofs_lo_rg" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of the offset on the downconversion rate, used with clock shift enabled or not.
16'h0000: clock shift enable
16'h0000: clock shift disable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_rc_rate_ofs_rest">
      <bits access="r" name="rxdp_rc_rate_ofs_rest_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rc_rate_ofs_rest_rg" pos="7:0" rst="0">
        <comment>
          Correction value for the rate offset, used with clock shift enabled or not.
8'h00: clock shift enable
8'h00: clock shift disable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef0_rg_1">
      <bits access="rw" name="rxdp_gdeq_coef0_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of RX group delay coefficient 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef0_rg_2">
      <bits access="r" name="rxdp_gdeq_coef0_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_gdeq_coef0_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of RX group delay coefficient 0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef1_rg_1">
      <bits access="rw" name="rxdp_gdeq_coef1_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of RX group delay coefficient 1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef1_rg_2">
      <bits access="r" name="rxdp_gdeq_coef1_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_gdeq_coef1_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of RX group delay coefficient 1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef2_rg_1">
      <bits access="rw" name="rxdp_gdeq_coef2_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of RX group delay coefficient 2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef2_rg_2">
      <bits access="r" name="rxdp_gdeq_coef2_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_gdeq_coef2_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of RX group delay coefficient 2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef3_rg_1">
      <bits access="rw" name="rxdp_gdeq_coef3_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of RX group delay coefficient 2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_coef3_rg_2">
      <bits access="r" name="rxdp_gdeq_coef3_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_gdeq_coef3_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of RX group delay coefficient 2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gdeq_bypass">
      <bits access="r" name="rxdp_gdeq_bypass_reserved_0" pos="15:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_zf_if_sel" pos="1" rst="0">
        <comment>
          RF data type.
0: IF
1: ZF
        </comment>
      </bits>
      <bits access="rw" name="rxdp_gdeq_bp_lp_sel" pos="0" rst="0">
        <comment>
          RF filter type.
0: BP
1: LP
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_adc_rd_buf_fifo">
      <bits access="r" name="rxdp_adc_rd_buf_fifo_reserved_0" pos="15:6" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_adc_rd_clr_rg" pos="5" rst="0">
        <comment>
          Read clear of DFE ADC FIFO, active high
        </comment>
      </bits>
      <bits access="rw" name="rxdp_adc_rd_clr_val_rg" pos="4:0" rst="0">
        <comment>
          Intial value of read point when FIFO read clear assert
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_adc_wr_buf_fifo">
      <bits access="r" name="rxdp_adc_wr_buf_fifo_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_adc_smp_rate_rg" pos="11:7" rst="0">
        <comment>
          Read rate of DFE ADC FIFO, which depends on RX mode.
5'h00: GGE
5'h01: NB/WT
        </comment>
      </bits>
      <bits access="rw" name="rxdp_adc_wr_clr_rg" pos="6" rst="0">
        <comment>
          Write clear of DFE ADC FIFO, active high
        </comment>
      </bits>
      <bits access="rw" name="rxdp_adc_wr_clr_val_rg" pos="5:1" rst="0">
        <comment>
          Intial value of write point when FIFO write clear assert
        </comment>
      </bits>
      <bits access="rw" name="rxdp_adc_wr_en_rg" pos="0" rst="1">
        <comment>
          Write enable of DFE ADC FIFO, active high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rxdp_dcc_valid_o_reg">
      <bits access="r" name="rxdp_dcc_valid_o_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rxdp_dcc_val_reg" pos="0" rst="0">
        <comment>
          Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rxdp_dcc_re_o_reg">
      <bits access="r" name="rxdp_dcc_re_o" pos="15:0" rst="0">
        <comment>
          Real part of DC value, it is stable when rxdp_dcc_val_reg is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rxdp_dcc_im_o_reg">
      <bits access="r" name="rxdp_dcc_im_o" pos="15:0" rst="0">
        <comment>
          Image part of DC value, it is stable when rxdp_dcc_val_reg is high
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="rxdp_notch_ct">
      <bits access="r" name="rxdp_notch_ct_reserved_0" pos="15:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch_dataen0" pos="1" rst="1">
        <comment>
          Data enable of Notch DC
0: disable
1: enable
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch_dataen1" pos="0" rst="1">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch_a0_i_reg">
      <bits access="r" name="rxdp_notch_a0_i_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch_a0_i" pos="11:0" rst="0">
        <comment>
          Coefficient a for real part of Notch DC
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch_a0_q_reg">
      <bits access="r" name="rxdp_notch_a0_q_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch_a0_q" pos="11:0" rst="0">
        <comment>
          Coefficient a for image part of Notch DC
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="rxdp_notch_k_reg">
      <bits access="r" name="rxdp_notch_k_reg_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch_k0" pos="3:0" rst="0">
        <comment>
          Coefficient k of Notch DC
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch2_ct">
      <bits access="r" name="rxdp_notch2_ct_reserved_0" pos="15:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_dataen0" pos="1" rst="1">
        <comment>
          Data enable of Notch H 1st core
0: disable
1: enable
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_dataen1" pos="0" rst="1">
        <comment>
          Data enable of Notch H 2nd core
0: disable
1: enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch2_a0_i_reg">
      <bits access="r" name="rxdp_notch2_a0_i_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_a0_i" pos="11:0" rst="0">
        <comment>
          Coefficient a for real part of Notch H 1st core
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch2_a0_q_reg">
      <bits access="r" name="rxdp_notch2_a0_q_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_a0_q" pos="11:0" rst="0">
        <comment>
          Coefficient a for image part of Notch H 1st core
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch2_a1_i_reg">
      <bits access="r" name="rxdp_notch2_a1_i_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_a1_i" pos="11:0" rst="0">
        <comment>
          Coefficient a for real part of Notch H 2nd core
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch2_a1_q_reg">
      <bits access="r" name="rxdp_notch2_a1_q_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_a1_q" pos="11:0" rst="0">
        <comment>
          Coefficient a for image part of Notch H 2nd core
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_notch2_k_reg">
      <bits access="r" name="rxdp_notch2_k_reg_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_k0" pos="7:4" rst="0">
        <comment>
          Coefficient k of Notch H 1st core
        </comment>
      </bits>
      <bits access="rw" name="rxdp_notch2_k1" pos="3:0" rst="0">
        <comment>
          Coefficient k of Notch H 2nd core
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef0_reg">
      <bits access="rw" name="rxdp_aci_fir_coef0" pos="15:0" rst="0">
        <comment>
          Coefficient COEF0 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef1_reg">
      <bits access="rw" name="rxdp_aci_fir_coef1" pos="15:0" rst="0">
        <comment>
          Coefficient COEF1 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef2_reg">
      <bits access="rw" name="rxdp_aci_fir_coef2" pos="15:0" rst="0">
        <comment>
          Coefficient COEF2 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef3_reg">
      <bits access="rw" name="rxdp_aci_fir_coef3" pos="15:0" rst="0">
        <comment>
          Coefficient COEF3 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef4_reg">
      <bits access="rw" name="rxdp_aci_fir_coef4" pos="15:0" rst="0">
        <comment>
          Coefficient COEF4 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef5_reg">
      <bits access="rw" name="rxdp_aci_fir_coef5" pos="15:0" rst="0">
        <comment>
          Coefficient COEF5 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef6_reg">
      <bits access="rw" name="rxdp_aci_fir_coef6" pos="15:0" rst="0">
        <comment>
          Coefficient COEF6 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef7_reg">
      <bits access="rw" name="rxdp_aci_fir_coef7" pos="15:0" rst="0">
        <comment>
          Coefficient COEF7 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef8_reg">
      <bits access="rw" name="rxdp_aci_fir_coef8" pos="15:0" rst="0">
        <comment>
          Coefficient COEF8 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef9_reg">
      <bits access="rw" name="rxdp_aci_fir_coef9" pos="15:0" rst="0">
        <comment>
          Coefficient COEF9 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef10_reg">
      <bits access="rw" name="rxdp_aci_fir_coef10" pos="15:0" rst="0">
        <comment>
          Coefficient COEF10 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef11_reg">
      <bits access="rw" name="rxdp_aci_fir_coef11" pos="15:0" rst="0">
        <comment>
          Coefficient COEF11 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef12_reg">
      <bits access="rw" name="rxdp_aci_fir_coef12" pos="15:0" rst="0">
        <comment>
          Coefficient COEF12 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef13_reg">
      <bits access="rw" name="rxdp_aci_fir_coef13" pos="15:0" rst="0">
        <comment>
          Coefficient COEF13 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef14_reg">
      <bits access="rw" name="rxdp_aci_fir_coef14" pos="15:0" rst="0">
        <comment>
          Coefficient COEF14 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef15_reg">
      <bits access="rw" name="rxdp_aci_fir_coef15" pos="15:0" rst="0">
        <comment>
          Coefficient COEF15 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef16_reg">
      <bits access="rw" name="rxdp_aci_fir_coef16" pos="15:0" rst="0">
        <comment>
          Coefficient COEF16 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef17_reg">
      <bits access="rw" name="rxdp_aci_fir_coef17" pos="15:0" rst="0">
        <comment>
          Coefficient COEF17 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef18_reg">
      <bits access="rw" name="rxdp_aci_fir_coef18" pos="15:0" rst="0">
        <comment>
          Coefficient COEF18 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef19_reg">
      <bits access="rw" name="rxdp_aci_fir_coef19" pos="15:0" rst="0">
        <comment>
          Coefficient COEF19 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef20_reg">
      <bits access="rw" name="rxdp_aci_fir_coef20" pos="15:0" rst="0">
        <comment>
          Coefficient COEF20 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef21_reg">
      <bits access="rw" name="rxdp_aci_fir_coef21" pos="15:0" rst="0">
        <comment>
          Coefficient COEF21 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef22_reg">
      <bits access="rw" name="rxdp_aci_fir_coef22" pos="15:0" rst="0">
        <comment>
          Coefficient COEF22 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_aci_filter_coef23_reg">
      <bits access="rw" name="rxdp_aci_fir_coef23" pos="15:0" rst="0">
        <comment>
          Coefficient COEF23 of ACI filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_mixer_freq_in_reg0">
      <bits access="rw" name="rxdp_mixer_freq_p0" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of frequency offset for Mixer
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_mixer_freq_in_reg1">
      <bits access="r" name="rxdp_mixer_freq_in_reg1_reserved_0" pos="15:8" rst="0">
      </bits>
      <bits access="rw" name="rxdp_mixer_freq_p1" pos="7:0" rst="0">
        <comment>
          Bit [23:16] of frequency offset for Mixer
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_rssi_reg">
      <bits access="r" name="rxdp_rssi_reg_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rssi_ob_enable" pos="7" rst="0">
        <comment>
          Outband RSSI enable
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rssi_ib_enable" pos="6" rst="0">
        <comment>
          Inband RSSI enable
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rssi_ob_ushift" pos="5:3" rst="0">
        <comment>
          Outband RSSI ushift value
        </comment>
      </bits>
      <bits access="rw" name="rxdp_rssi_ib_ushift" pos="2:0" rst="0">
        <comment>
          Inband RSSI ushift value
        </comment>
      </bits>
    </reg>
    <hole size="96"/>
    <reg protect="rw" name="rxdpdecimatefordigrf">
      <bits access="r" name="rxdpdecimatefordigrf_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_deci_gge_delay_rg" pos="11:4" rst="0">
        <comment>
          delay count to discard some initial samples
        </comment>
      </bits>
      <bits access="rw" name="rxdp_deci_gge_deci_select" pos="3:1" rst="0">
        <comment>
          sample select in 12x data rate for GGE mode
        </comment>
      </bits>
      <bits access="rw" name="rxdp_deci_gge_sample_mode" pos="0" rst="0">
        <comment>
          sample number per symbol for GGE mode
0: 541K, 2x
1: 1.08M, 4x
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdpmt_param">
      <bits access="r" name="rxdpmt_param_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_deci_wt_deci_select" pos="9:6" rst="0">
        <comment>
          sample select in 192K data rate for WT mode
        </comment>
      </bits>
      <bits access="rw" name="rxdp_deci_wt_sample_mode" pos="5:2" rst="0">
        <comment>
          0: 192K
1: 96K=192K/2
2: 64K=192K/3
....
15: 12K=192K/16
        </comment>
      </bits>
      <bits access="rw" name="rxdp_cic2_mode" pos="1:0" rst="0">
        <comment>
          select data rate for CIC2 module used by WT mode
0: mode0, CIC2 decimated by 40, i.e., from 3.84M to 96K
1: mode1, CIC2 decimated by 20, i.e., from 3.84M to 192K
2/3: mode2,  CIC2 decimated by 10, i.e., from 3.84M to 384K
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_gain_ct_rf_reg">
      <bits access="r" name="rxdp_gain_ct_rf_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_gain_ct_rf" pos="9:0" rst="0">
        <comment>
          Gain RF control. [-24db, 57.875db], step=0.125db
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="start_max_min_ib_rssi_reg">
      <bits access="r" name="start_max_min_ib_rssi_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="start_max_min_ib_rssi" pos="0" rst="0">
        <comment>
          start inband RSSI max and min measurement
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="count_16lsb_ib_rssi_reg">
      <bits access="rw" name="count_16lsb_ib_rssi" pos="15:0" rst="30720">
        <comment>
          timer count [15:0] for max and min measurement report after start
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="count_16msb_ib_rssi_reg">
      <bits access="rw" name="count_16msb_ib_rssi" pos="15:0" rst="0">
        <comment>
          timer count [31:16] for max and min measurement report after start
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="load_max_min_ib_rssi_reg">
      <bits access="r" name="load_max_min_ib_rssi_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="load_max_min_ib_rssi" pos="0" rst="0">
        <comment>
          start to load max and min measurement report. Before next load, set it low firstly
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_max_min_val_ib_rssi">
      <bits access="r" name="rssi_max_min_val_ib_rssi_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_max_min_val_reg_ib_rssi" pos="0" rst="0">
        <comment>
          valid indication of max and min measurement report after assert load_max_min_ib_rssi to avoid metastability. rssi_min_reg_ib_rssi and rssi_max_reg_ib_rssi are stable when this register is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_min_ib_rssi">
      <bits access="r" name="rssi_min_ib_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_min_reg_ib_rssi" pos="9:0" rst="0">
        <comment>
          inband RSSI min value, it is stable when rssi_max_min_val_reg_ib_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_max_ib_rssi">
      <bits access="r" name="rssi_max_ib_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_max_reg_ib_rssi" pos="9:0" rst="0">
        <comment>
          inband RSSI max value, it is stable when rssi_max_min_val_reg_ib_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="int_ib_rssi">
      <bits access="r" name="int_ib_rssi_reserved_0" pos="15:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_int_ib_rssi" pos="2" rst="0">
        <comment>
          interrupt status to be able to start to load max and min measurement report
        </comment>
      </bits>
      <bits access="rw" name="int_mask_ib_rssi" pos="1" rst="0">
        <comment>
          interrupt mask
        </comment>
      </bits>
      <bits access="rw" name="int_clear_ib_rssi" pos="0" rst="0">
        <comment>
          interrupt clear
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="load_ib_rssi_reg">
      <bits access="r" name="load_ib_rssi_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="load_ib_rssi" pos="0" rst="0">
        <comment>
          start to load instant measurement report. Before next load, set it low firstly
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_val_ib_rssi">
      <bits access="r" name="rssi_val_ib_rssi_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_val_reg_ib_rssi" pos="0" rst="0">
        <comment>
          valid indication of instant measurement report after assert load_ib_rssi to avoid metastability. rssi_reg_ib_rssi is stable when this register is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_ib_rssi">
      <bits access="r" name="rssi_ib_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_reg_ib_rssi" pos="9:0" rst="0">
        <comment>
          inband RSSI instant value, it is stable when rssi_val_reg_ib_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="start_max_min_ob_rssi_reg">
      <bits access="r" name="start_max_min_ob_rssi_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="start_max_min_ob_rssi" pos="0" rst="0">
        <comment>
          start outband RSSI max and min measurement
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="count_16lsb_ob_rssi_reg">
      <bits access="rw" name="count_16lsb_ob_rssi" pos="15:0" rst="30720">
        <comment>
          timer count [15:0] for max and min measurement report after start
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="count_16msb_ob_rssi_reg">
      <bits access="rw" name="count_16msb_ob_rssi" pos="15:0" rst="0">
        <comment>
          timer count [31:16] for max and min measurement report after start
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="load_max_min_ob_rssi_reg">
      <bits access="r" name="load_max_min_ob_rssi_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="load_max_min_ob_rssi" pos="0" rst="0">
        <comment>
          start to load max and min measurement report. Before next load, set it low firstly
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_max_min_val_ob_rssi">
      <bits access="r" name="rssi_max_min_val_ob_rssi_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_max_min_val_reg_ob_rssi" pos="0" rst="0">
        <comment>
          valid indication of max and min measurement report after assert load_max_min_ob_rssi to avoid metastability. rssi_min_reg_ob_rssi and rssi_max_reg_ob_rssi are stable when this register is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_min_ob_rssi">
      <bits access="r" name="rssi_min_ob_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_min_reg_ob_rssi" pos="9:0" rst="0">
        <comment>
          outband RSSI min value, it is stable when rssi_max_min_val_reg_ob_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_max_ob_rssi">
      <bits access="r" name="rssi_max_ob_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_max_reg_ob_rssi" pos="9:0" rst="0">
        <comment>
          outband RSSI max value, it is stable when rssi_max_min_val_reg_ob_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="int_ob_rssi">
      <bits access="r" name="int_ob_rssi_reserved_0" pos="15:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_int_ob_rssi" pos="2" rst="0">
        <comment>
          interrupt status to be able to start to load max and min measurement report
        </comment>
      </bits>
      <bits access="rw" name="int_mask_ob_rssi" pos="1" rst="0">
        <comment>
          interrupt mask
        </comment>
      </bits>
      <bits access="rw" name="int_clear_ob_rssi" pos="0" rst="0">
        <comment>
          interrupt clear
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="load_ob_rssi_reg">
      <bits access="r" name="load_ob_rssi_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="load_ob_rssi" pos="0" rst="0">
        <comment>
          start to load instant measurement report. Before next load, set it low firstly
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_val_ob_rssi">
      <bits access="r" name="rssi_val_ob_rssi_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_val_reg_ob_rssi" pos="0" rst="0">
        <comment>
          valid indication of instant measurement report after assert load_ob_rssi to avoid metastability
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_wd_ob_rssi">
      <bits access="r" name="rssi_wd_ob_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_reg_wd_ob_rssi" pos="9:0" rst="0">
        <comment>
          outband RSSI instant value for WB, it is stable when rssi_val_reg_ob_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_up_ob_rssi">
      <bits access="r" name="rssi_up_ob_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_reg_up_ob_rssi" pos="9:0" rst="0">
        <comment>
          outband RSSI instant value for UP, it is stable when rssi_val_reg_ob_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rssi_dn_ob_rssi">
      <bits access="r" name="rssi_dn_ob_rssi_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="rssi_reg_dn_ob_rssi" pos="9:0" rst="0">
        <comment>
          outband RSSI instant value for DN, it is stable when rssi_val_reg_ob_rssi is high
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="digrf_rx_ctrl_reg">
      <bits access="r" name="digrf_rx_ctrl_reg_reserved_0" pos="15:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="digrf_rx_rx_en_delay_counter" pos="6:3" rst="0">
        <comment>
          delay counter for rx_en
        </comment>
      </bits>
      <bits access="rw" name="digrf_rx_rx_iq_order" pos="2" rst="0">
        <comment>
          RX IQ swap
        </comment>
      </bits>
      <bits access="rw" name="digrf_rx_rxclk_polarity" pos="1" rst="0">
        <comment>
          RX clock invert or not
        </comment>
      </bits>
      <bits access="rw" name="digrf_rx_digrf_enable" pos="0" rst="1">
        <comment>
          enable digrf RX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="digrf_tx_ctrl_reg">
      <bits access="rw" name="digrf_tx_txdata_out_timer" pos="15:8" rst="0">
        <comment>
          delay counter for tx_data
        </comment>
      </bits>
      <bits access="r" name="digrf_tx_ctrl_reg_reserved_0" pos="7:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="digrf_tx_txclk_polarity" pos="1" rst="0">
        <comment>
          TX clock invert or not
        </comment>
      </bits>
      <bits access="rw" name="digrf_tx_digrf_stream_mode_enable" pos="0" rst="1">
        <comment>
          TX mode.
0: block mode
1: stream mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_bypass_control_reg1">
      <bits access="rw" name="rxdp_bypass_uphb1" pos="15" rst="0">
        <comment>
          Interp. HBF1
0: SW bypass disable
1: SW bypass enable
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_gainbb" pos="14" rst="0">
        <comment>
          Gain_BB
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_notch2_2" pos="13" rst="0">
        <comment>
          Notrch(H) 2nd core
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_notch2_1" pos="12" rst="0">
        <comment>
          Notrch(H) 1st core
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_dnbh1" pos="11" rst="0">
        <comment>
          Deci. HBF1
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_aci_lpf" pos="10" rst="0">
        <comment>
          ACI Filter
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_rssi_ob" pos="9" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_gainrf" pos="8" rst="0">
        <comment>
          Gain_RF
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_gdeq" pos="7" rst="0">
        <comment>
          Group Delay Equ
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_notch1_2" pos="6" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_notch1_1" pos="5" rst="0">
        <comment>
          Notch(DC)
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mixer" pos="4" rst="0">
        <comment>
          Mixer
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_rc" pos="3" rst="0">
        <comment>
          RC
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_cic2" pos="2" rst="0">
        <comment>
          Deci.CIC2
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_dcc" pos="1" rst="0">
        <comment>
          DC Calib.&amp;Cancel
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_cic1" pos="0" rst="0">
        <comment>
          Deci.CIC1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_bypass_control_reg2">
      <bits access="r" name="rxdp_bypass_control_reg2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_rssi_ib" pos="3" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_deci_digrf" pos="2" rst="0">
        <comment>
          Downsample
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_uphb3" pos="1" rst="0">
        <comment>
          Interp. HBF3
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_uphb2" pos="0" rst="0">
        <comment>
          Interp. HBF2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_bypass_mode_control_reg1">
      <bits access="rw" name="rxdp_bypass_mode_uphb1" pos="15" rst="0">
        <comment>
          Interp. HBF1
0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement
1: bypass controlled by SW. When it is set, rxdp_bypass_uphb1 will be used
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_gainbb" pos="14" rst="0">
        <comment>
          Gain_BB
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_notch2_2" pos="13" rst="0">
        <comment>
          Notrch(H) 2nd core
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_notch2_1" pos="12" rst="0">
        <comment>
          Notrch(H) 1st core
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_dnbh1" pos="11" rst="0">
        <comment>
          Deci. HBF1
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_aci_lpf" pos="10" rst="0">
        <comment>
          ACI Filter
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_rssi_ob" pos="9" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_gainrf" pos="8" rst="0">
        <comment>
          Gain_RF
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_gdeq" pos="7" rst="0">
        <comment>
          Group Delay Equ
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_notch1_2" pos="6" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_notch1_1" pos="5" rst="0">
        <comment>
          Notch(DC)
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_mixer" pos="4" rst="0">
        <comment>
          Mixer
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_rc" pos="3" rst="0">
        <comment>
          RC
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_cic2" pos="2" rst="0">
        <comment>
          Deci.CIC2
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_dcc" pos="1" rst="0">
        <comment>
          DC Calib.&amp;Cancel
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_cic1" pos="0" rst="0">
        <comment>
          Deci.CIC1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rxdp_bypass_mode_control_reg2">
      <bits access="r" name="rxdp_bypass_mode_control_reg2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_rssi_ib" pos="3" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_deci_digrf" pos="2" rst="0">
        <comment>
          Downsample
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_uphb3" pos="1" rst="0">
        <comment>
          Interp. HBF3
        </comment>
      </bits>
      <bits access="rw" name="rxdp_bypass_mode_uphb2" pos="0" rst="0">
        <comment>
          Interp. HBF2
        </comment>
      </bits>
    </reg>
    <hole size="768"/>
    <reg protect="rw" name="txdp_gsm_a1">
      <bits access="r" name="txdp_gsm_a1_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_a1_rg" pos="11:0" rst="0">
        <comment>
          Coefficient a1 for PLL Equ.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_a2">
      <bits access="r" name="txdp_gsm_a2_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_a2_rg" pos="11:0" rst="0">
        <comment>
          Coefficient a2 for PLL Equ.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_b1">
      <bits access="r" name="txdp_gsm_b1_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_b1_rg" pos="11:0" rst="0">
        <comment>
          Coefficient b1 for PLL Equ.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_b2">
      <bits access="r" name="txdp_gsm_b2_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_b2_rg" pos="11:0" rst="0">
        <comment>
          Coefficient b2 for PLL Equ.
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_g">
      <bits access="rw" name="txdp_gsm_g_rg" pos="15:0" rst="0">
        <comment>
          Bit [27:12] of gain for PLL Equ. It is valid when AFC adjustment is being enabled
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_equ_bypass_reg">
      <bits access="r" name="txdp_gsm_equ_bypass_reg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_equ_bypass" pos="0" rst="1">
        <comment>
          Bypass PLL Equ.
0: disable bypass
1: enable bypass
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_equ_tx_shift_ct">
      <bits access="r" name="txdp_gsm_equ_tx_shift_ct_reserved_0" pos="15:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_int_dec_sel_rg" pos="6:5" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_form_lsb_acc_en" pos="4" rst="0">
        <comment>
          4 LSB control
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_equ_tx_shift_ct_rg" pos="3:0" rst="0">
        <comment>
          Former output shift control
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_offset_value0_reg">
      <bits access="rw" name="txdp_gsm_offset_value0" pos="15:0" rst="43691">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_offset_value1_reg">
      <bits access="r" name="txdp_gsm_offset_value1_reg_reserved_0" pos="15:8" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_offset_value1" pos="7:0" rst="10">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_tx_rx">
      <bits access="r" name="txdp_gsm_tx_rx_reserved_0" pos="15:5" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_freq_rg2" pos="4:2" rst="0">
        <comment>
          Bit [34:32] for GSM TX frequency
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_edge_sel_rg" pos="1" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_tx_rx_rg" pos="0" rst="1">
        <comment>
          use former output or not
0: RX don't use
1: TX use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_freq0">
      <bits access="rw" name="txdp_gsm_freq_rg0" pos="15:0" rst="25200">
        <comment>
          Bit [15:0] for GSM TX frequency
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_freq1">
      <bits access="rw" name="txdp_gsm_freq_rg1" pos="15:0" rst="37415">
        <comment>
          Bit [31:16] for GSM TX frequency
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_freq_tx_offset">
      <bits access="rw" name="txdp_gsm_freq_tx_offset_rg" pos="15:0" rst="0">
        <comment>
          Offset add to GSM TX frequency
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="txdp_gsm_sdmpre_ct">
      <bits access="r" name="txdp_gsm_sdmpre_ct_reserved_0" pos="15:7" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_tri_wave_bypass_rg" pos="6" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_shift_more_rg" pos="5" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_offset_enable_rg" pos="4" rst="1">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_int_freq_sel_mode_rg" pos="3:1" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_form_bypass" pos="0" rst="0">
        <comment>
          GSM TX frequency control.
0: modulation signal act on GSM TX freqency
1: GSM TX freqency is fixed
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_misc_reg">
      <bits access="r" name="txdp_gsm_misc_reg_reserved_0" pos="15:4" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="gsm_freq_load_bypass_rg" pos="3" rst="0">
        <comment>
          GSM TX frequency load is at the same time of AFC adjustment or not
0: at the same time
1: not at the same time
        </comment>
      </bits>
      <bits access="rw" name="gsm_tx_fifo_rd_clr_rg" pos="2" rst="0">
        <comment>
          Clear bit for read point of GSM TX FIFO
        </comment>
      </bits>
      <bits access="rw" name="gsm_tx_fifo_wr_clr_rg" pos="1" rst="0">
        <comment>
          Clear bit for write point of GSM TX FIFO
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_pn_en" pos="0" rst="0">
        <comment>
          PN test enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_pn_switch_reg">
      <bits access="r" name="txdp_gsm_pn_switch_reg_reserved_0" pos="15:3" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_pn_switch" pos="2:0" rst="0">
        <comment>
          The mode of pseudo random polynomial
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_encode_en_reg">
      <bits access="r" name="txdp_gsm_encode_en_reg_reserved_0" pos="15:2" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_encode_pos_neg" pos="1" rst="0">
        <comment>
          The initial phase selection of differential encoding
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_encode_en" pos="0" rst="0">
        <comment>
          The differential encoding enable for GSM TX data
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_g_ext_reg">
      <bits access="r" name="txdp_gsm_g_ext_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gsm_g_ext" pos="11:0" rst="0">
        <comment>
          Bit [11:0] of gain for PLL Equ. It works with register txdp_gsm_g_rg
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_nb_ctrl_reg">
      <bits access="r" name="txdp_gsm_nb_ctrl_reg_reserved_0" pos="15:8" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="gsm_sw_ctrl_rg" pos="7" rst="0">
        <comment>
          enable delay control by software
        </comment>
      </bits>
      <bits access="rw" name="gsm_dly1_data_idx_rg" pos="6:2" rst="0">
        <comment>
          Delay1 index
        </comment>
      </bits>
      <bits access="rw" name="gsm_dly2_data_idx_rg" pos="1:0" rst="0">
        <comment>
          Delay2 index
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff1_reg_l">
      <bits access="rw" name="gsm_grp_dly_coff1_rg_l" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of gsm_grp_dly_coff1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff1_reg_m">
      <bits access="r" name="txdp_gsm_grp_dly_coff1_reg_m_reserved_0" pos="15:4" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="gsm_grp_dly_coff1_rg_m" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of gsm_grp_dly_coff1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff2_reg_l">
      <bits access="rw" name="gsm_grp_dly_coff2_rg_l" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of gsm_grp_dly_coff2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff2_reg_m">
      <bits access="r" name="txdp_gsm_grp_dly_coff2_reg_m_reserved_0" pos="15:4" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="gsm_grp_dly_coff2_rg_m" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of gsm_grp_dly_coff2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff3_reg_l">
      <bits access="rw" name="gsm_grp_dly_coff3_rg_l" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of gsm_grp_dly_coff3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff3_reg_m">
      <bits access="r" name="txdp_gsm_grp_dly_coff3_reg_m_reserved_0" pos="15:4" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="gsm_grp_dly_coff3_rg_m" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of gsm_grp_dly_coff3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff4_reg_l">
      <bits access="rw" name="gsm_grp_dly_coff4_rg_l" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of gsm_grp_dly_coff4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gsm_grp_dly_coff4_reg_m">
      <bits access="r" name="txdp_gsm_grp_dly_coff4_reg_m_reserved_0" pos="15:4" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="gsm_grp_dly_coff4_rg_m" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of gsm_grp_dly_coff4
        </comment>
      </bits>
    </reg>
    <hole size="1152"/>
    <reg protect="rw" name="txdp_wedge_gain_ct_reg">
      <bits access="r" name="txdp_wedge_gain_ct_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_gain_ct" pos="9:0" rst="0">
        <comment>
          Gain control of NB/WT TX. [-24db, 57.875db], step=0.125db
        </comment>
      </bits>
    </reg>
    <hole size="448"/>
    <reg protect="rw" name="txdp_wedge_rc_stretch_reg">
      <bits access="r" name="txdp_wedge_rc_stretch_reg_reserved_0" pos="15:11" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_rc_strech_rg" pos="10:0" rst="32">
        <comment>
          Number of output clock cycles between 2 samples after RC:
12'h004: GGE
12'h010: NB with PolarIQ
12'h020: NB without PolarIQ
12'h040: WT with PolarIQ
12'h080: WT without PolarIQ
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_rc_rate_ofs_period_rg_reg">
      <bits access="r" name="txdp_rc_rate_ofs_period_rg_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_rc_rate_ofs_period_rg" pos="9:0" rst="1">
        <comment>
          Number of output samples, used with clock shift enabled or not.
10'h001: clock shift disable without PolarIQ
10'h145: clock shift disable with PolarIQ
10'h011: clock shift enable without PoarrIQ
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_rc_rate_ofs_hi_rg_reg">
      <bits access="r" name="txdp_rc_rate_ofs_hi_rg_reg_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_rc_rate_ofs_hi_rg" pos="7:0" rst="128">
        <comment>
          Bit [23:16] of the offset on the downconversion rate, used with clock shift.
8'h80: clock shift disable without PolarIQ
8'hae: clock shift disable with PolarIQ
8'h70: clock shift enable without PolarIQ
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_rc_rate_ofs_lo_rg_reg">
      <bits access="rw" name="txdp_rc_rate_ofs_lo_rg" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of the offset on the downconversion rate, used with clock shift.
16'h0000: clock shift disable without PolarIQ
10'h794d: clock shift disable with PolarIQ
16'hf0f0: clock shift enable without PolarIQ
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_rc_rate_ofs_rest_rc_reg">
      <bits access="r" name="txdp_rc_rate_ofs_rest_rc_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_rc_rate_ofs_rest_rg" pos="9:0" rst="0">
        <comment>
          Correction value for the rate offset, used with clock shift enabled or not.
10'h000: clock shift disable without PolarIQ
10'h13f: clock shift disable with PolarIQ
10'h010: clock shift enable without PolarIQ
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="txdp_wedge_pm_split_mode_reg">
      <bits access="r" name="txdp_wedge_pm_split_mode_reg_reserved_0" pos="15:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_flow_en" pos="1" rst="0">
      </bits>
      <bits access="rw" name="txdp_wedge_split_mode" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_shrink_reg">
      <bits access="r" name="txdp_wedge_am_shrink_reg_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_shrink" pos="7:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="txdp_wedge_pm_shift_reg">
      <bits access="r" name="txdp_wedge_pm_shift_reg_reserved_0" pos="15:2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_shift" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p0_reg">
      <bits access="r" name="txdp_wedge_am_p0_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p0" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p1_reg">
      <bits access="r" name="txdp_wedge_am_p1_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p1" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p2_reg">
      <bits access="r" name="txdp_wedge_am_p2_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p2" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p3_reg">
      <bits access="r" name="txdp_wedge_am_p3_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p3" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p4_reg">
      <bits access="r" name="txdp_wedge_am_p4_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p4" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p5_reg">
      <bits access="r" name="txdp_wedge_am_p5_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p5" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p6_reg">
      <bits access="r" name="txdp_wedge_am_p6_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p6" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p7_reg">
      <bits access="r" name="txdp_wedge_am_p7_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p7" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p8_reg">
      <bits access="r" name="txdp_wedge_am_p8_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p8" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p9_reg">
      <bits access="r" name="txdp_wedge_am_p9_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p9" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p10_reg">
      <bits access="r" name="txdp_wedge_am_p10_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p10" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p11_reg">
      <bits access="r" name="txdp_wedge_am_p11_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p11" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p12_reg">
      <bits access="r" name="txdp_wedge_am_p12_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p12" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p13_reg">
      <bits access="r" name="txdp_wedge_am_p13_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p13" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p14_reg">
      <bits access="r" name="txdp_wedge_am_p14_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p14" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p15_reg">
      <bits access="r" name="txdp_wedge_am_p15_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p15" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_am_p16_reg">
      <bits access="r" name="txdp_wedge_am_p16_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_am_p16" pos="9:0" rst="0">
        <comment>
          Amplitude compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p0_reg">
      <bits access="r" name="txdp_wedge_pm_p0_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p0" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p1_reg">
      <bits access="r" name="txdp_wedge_pm_p1_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p1" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p2_reg">
      <bits access="r" name="txdp_wedge_pm_p2_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p2" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p3_reg">
      <bits access="r" name="txdp_wedge_pm_p3_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p3" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p4_reg">
      <bits access="r" name="txdp_wedge_pm_p4_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p4" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p5_reg">
      <bits access="r" name="txdp_wedge_pm_p5_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p5" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p6_reg">
      <bits access="r" name="txdp_wedge_pm_p6_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p6" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p7_reg">
      <bits access="r" name="txdp_wedge_pm_p7_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p7" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p8_reg">
      <bits access="r" name="txdp_wedge_pm_p8_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p8" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p9_reg">
      <bits access="r" name="txdp_wedge_pm_p9_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p9" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p10_reg">
      <bits access="r" name="txdp_wedge_pm_p10_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p10" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p11_reg">
      <bits access="r" name="txdp_wedge_pm_p11_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p11" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p12_reg">
      <bits access="r" name="txdp_wedge_pm_p12_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p12" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p13_reg">
      <bits access="r" name="txdp_wedge_pm_p13_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p13" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p14_reg">
      <bits access="r" name="txdp_wedge_pm_p14_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p14" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p15_reg">
      <bits access="r" name="txdp_wedge_pm_p15_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p15" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_wedge_pm_p16_reg">
      <bits access="r" name="txdp_wedge_pm_p16_reg_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_wedge_pm_p16" pos="9:0" rst="0">
        <comment>
          Phase compensation curve of DPD
        </comment>
      </bits>
    </reg>
    <hole size="192"/>
    <reg protect="rw" name="clk_dac_ctrl">
      <bits access="r" name="clk_dac_ctrl_reserved_0" pos="15:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="clk_dac_test_mode" pos="6:4" rst="0">
        <comment>
          divide resource of clk_dac when test mode.
000: divide by 1
001: divide by 2
010: divide by 4
011: divide by 8
100: divide by 16
101: divide by 32
110: divide by 64
default: divide by 1
        </comment>
      </bits>
      <bits access="rw" name="clk_dac_test_sel" pos="3:2" rst="0">
        <comment>
          resource of clk_dac when test mode.
00: clk_26m
01: clk_61.44m
10: clk_26m_fbc
11: clk_adc_gge_nb
        </comment>
      </bits>
      <bits access="rw" name="clk_dac_test_en" pos="1" rst="0">
        <comment>
          enable clk_dac when test mode
        </comment>
      </bits>
      <bits access="rw" name="clk_dac_sel" pos="0" rst="0">
        <comment>
          0: clk_dac is from function mode
1: clk_dac is from test mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_delay_reg">
      <bits access="r" name="txdp_delay_reg_reserved_0" pos="15:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="delay4_rg" pos="6:4" rst="0">
        <comment>
          Delay4 index
        </comment>
      </bits>
      <bits access="rw" name="delay5_rg" pos="3" rst="0">
        <comment>
          Delay5 index
        </comment>
      </bits>
      <bits access="rw" name="delay6_rg" pos="2" rst="0">
        <comment>
          Delay6 index
        </comment>
      </bits>
      <bits access="rw" name="delay7_rg" pos="1:0" rst="0">
        <comment>
          Delay7 index
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aclr_coef0">
      <bits access="r" name="aclr_coef0_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="aclr_coef00" pos="9:0" rst="0">
        <comment>
          Coefficient 0 of ACLR filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aclr_coef1">
      <bits access="r" name="aclr_coef1_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="aclr_coef01" pos="9:0" rst="0">
        <comment>
          Coefficient 1 of ACLR filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aclr_coef2">
      <bits access="r" name="aclr_coef2_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="aclr_coef02" pos="9:0" rst="0">
        <comment>
          Coefficient 2 of ACLR filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="aclr_coef3">
      <bits access="r" name="aclr_coef3_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="aclr_coef03" pos="9:0" rst="0">
        <comment>
          Coefficient 3 of ACLR filter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef0_rg_1">
      <bits access="rw" name="txdp_gdeq_coef0_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of coefficient 0 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef0_rg_2">
      <bits access="r" name="txdp_gdeq_coef0_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gdeq_coef0_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of coefficient 0 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef1_rg_1">
      <bits access="rw" name="txdp_gdeq_coef1_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of coefficient 1 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef1_rg_2">
      <bits access="r" name="txdp_gdeq_coef1_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gdeq_coef1_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of coefficient 1 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef2_rg_1">
      <bits access="rw" name="txdp_gdeq_coef2_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of coefficient 2 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef2_rg_2">
      <bits access="r" name="txdp_gdeq_coef2_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gdeq_coef2_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of coefficient 2 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef3_rg_1">
      <bits access="rw" name="txdp_gdeq_coef3_rg_lo" pos="15:0" rst="0">
        <comment>
          Bit [15:0] of coefficient 3 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_gdeq_coef3_rg_2">
      <bits access="r" name="txdp_gdeq_coef3_rg_2_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_gdeq_coef3_rg_hi" pos="3:0" rst="0">
        <comment>
          Bit [19:16] of coefficient 3 of group delay equ. for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef00">
      <bits access="r" name="txdp_polariq_fir_coef00_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef0" pos="11:0" rst="0">
        <comment>
          Coefficient 0 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef01">
      <bits access="r" name="txdp_polariq_fir_coef01_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef1" pos="11:0" rst="0">
        <comment>
          Coefficient 1 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef02">
      <bits access="r" name="txdp_polariq_fir_coef02_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef2" pos="11:0" rst="0">
        <comment>
          Coefficient 2 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef03">
      <bits access="r" name="txdp_polariq_fir_coef03_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef3" pos="11:0" rst="0">
        <comment>
          Coefficient 3 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef04">
      <bits access="r" name="txdp_polariq_fir_coef04_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef4" pos="11:0" rst="0">
        <comment>
          Coefficient 4 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef05">
      <bits access="r" name="txdp_polariq_fir_coef05_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef5" pos="11:0" rst="0">
        <comment>
          Coefficient 5 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef06">
      <bits access="r" name="txdp_polariq_fir_coef06_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef6" pos="11:0" rst="0">
        <comment>
          Coefficient 6 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef07">
      <bits access="r" name="txdp_polariq_fir_coef07_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef7" pos="11:0" rst="0">
        <comment>
          Coefficient 7 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef08">
      <bits access="r" name="txdp_polariq_fir_coef08_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef8" pos="11:0" rst="0">
        <comment>
          Coefficient 8 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef09">
      <bits access="r" name="txdp_polariq_fir_coef09_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef9" pos="11:0" rst="0">
        <comment>
          Coefficient 9 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef010">
      <bits access="r" name="txdp_polariq_fir_coef010_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef10" pos="11:0" rst="0">
        <comment>
          Coefficient 10 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_polariq_fir_coef011">
      <bits access="r" name="txdp_polariq_fir_coef011_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_polariq_fir_coef11" pos="11:0" rst="0">
        <comment>
          Coefficient 11 of PolarIQ LPF in DPD for NB/WT TX
        </comment>
      </bits>
    </reg>
    <hole size="128"/>
    <reg protect="rw" name="data_format_ctrl">
      <bits access="r" name="data_format_ctrl_reserved_0" pos="15:9" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="nb_tx_rx_loop" pos="8" rst="0">
        <comment>
          BB TX data loopback to BB RX
        </comment>
      </bits>
      <bits access="rw" name="rx_iq_swap" pos="7" rst="0">
        <comment>
          BB RX IQ swap. 
0: normal
1: swap
        </comment>
      </bits>
      <bits access="rw" name="tx_iq_swap" pos="6" rst="0">
        <comment>
          BB TX IQ swap. 
0: normal
1: swap
        </comment>
      </bits>
      <bits access="rw" name="adc_iq_swap" pos="5" rst="0">
        <comment>
          ADC IQ swap. 
0: normal
1: swap
        </comment>
      </bits>
      <bits access="rw" name="dac_iq_swap" pos="4" rst="0">
        <comment>
          DAC IQ swap. 
0: normal
1: swap
        </comment>
      </bits>
      <bits access="rw" name="rx_off_bin_en" pos="3" rst="0">
        <comment>
          BB RX. 
0: two's complement
1: offset binary
        </comment>
      </bits>
      <bits access="rw" name="tx_off_bin_en" pos="2" rst="0">
        <comment>
          BB TX.
0: two's complement
1: offset binary
        </comment>
      </bits>
      <bits access="rw" name="adc_off_bin_en" pos="1" rst="0">
        <comment>
          RF ADC.
0: two's complement
1: offset binary
        </comment>
      </bits>
      <bits access="rw" name="dac_off_bin_en" pos="0" rst="1">
        <comment>
          RF DAC. 
0: two's complement
1: offset binary
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="temper_ct">
      <bits access="r" name="temper_ct_reserved_0" pos="15:10" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="temper_pout_val_rg" pos="9" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="temper_pout_load" pos="8" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf3_bypass" pos="7" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="temper_ushift" pos="6:4" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="temper_bw_sel" pos="3:2" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf_bypass" pos="1" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="temper_hold_en" pos="0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="temper_dout_reg">
      <bits access="r" name="temper_dout" pos="15:0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="osc_temp_clk_ct">
      <bits access="r" name="osc_temp_clk_ct_reserved_0" pos="15:5" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temp_clk_phase_sel" pos="4" rst="0">
        <comment>
          No use
        </comment>
      </bits>
      <bits access="rw" name="osc_clk_en" pos="3" rst="0">
        <comment>
          clock enable for Temcomp
        </comment>
      </bits>
      <bits access="rw" name="osc_clk_freq_sel" pos="2:1" rst="0">
        <comment>
          divide mode of clock from analog for Temcomp
0: not divide
1: 1/2 divide
2: 1/4 divide
3: 1/8 divide
        </comment>
      </bits>
      <bits access="rw" name="osc_clk_phase_sel" pos="0" rst="0">
        <comment>
          clock invert for Temcomp
0: clock invert disable
1: clock invert enable
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sdm_fre_hi_reg">
      <bits access="r" name="sdm_fre_hi_reg_reserved_0" pos="15:12" rst="0">
      </bits>
      <bits access="rw" name="sdm_force_bypass" pos="11" rst="0">
        <comment>
          force bypass, high valid
        </comment>
      </bits>
      <bits access="rw" name="sdm_bypass" pos="10" rst="1">
        <comment>
          bypass, high valid
        </comment>
      </bits>
      <bits access="rw" name="sdm_dither_bypass" pos="9" rst="1">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="rw" name="sdm_fre_load" pos="8" rst="0">
        <comment>
          set sdm frequency value, high valid
        </comment>
      </bits>
      <bits access="rw" name="sdm_fre_hi" pos="7:0" rst="0">
        <comment>
          sdm frequency value, high 8 bits
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sdm_fre_lo_reg">
      <bits access="rw" name="sdm_fre_lo" pos="15:0" rst="0">
        <comment>
          sdm frequency value, low 16 bits
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temper_lpf_a11_rg">
      <bits access="r" name="temper_lpf_a11_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf_a11" pos="13:0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temper_lpf_a12_rg">
      <bits access="r" name="temper_lpf_a12_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf_a12" pos="13:0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temper_lpf_g1_rg">
      <bits access="r" name="temper_lpf_g1_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf_g1" pos="13:0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temper_lpf_a21_rg">
      <bits access="r" name="temper_lpf_a21_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf_a21" pos="13:0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temper_lpf_a22_rg">
      <bits access="r" name="temper_lpf_a22_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf_a22" pos="13:0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temper_lpf_g2_rg">
      <bits access="r" name="temper_lpf_g2_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temper_lpf_g2" pos="13:0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temcom_lpf_a11_rg">
      <bits access="r" name="temcom_lpf_a11_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temcom_lpf_a11" pos="13:0" rst="0">
        <comment>
          Coefficient a11 for Temcomp LPF
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temcom_lpf_a12_rg">
      <bits access="r" name="temcom_lpf_a12_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temcom_lpf_a12" pos="13:0" rst="0">
        <comment>
          Coefficient a12 for Temcomp LPF
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temcom_lpf_g1_rg">
      <bits access="r" name="temcom_lpf_g1_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temcom_lpf_g1" pos="13:0" rst="0">
        <comment>
          Coefficient g1 for Temcomp LPF
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temcom_lpf_a21_rg">
      <bits access="r" name="temcom_lpf_a21_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temcom_lpf_a21" pos="13:0" rst="0">
        <comment>
          Coefficient a21 for Temcomp LPF
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temcom_lpf_a22_rg">
      <bits access="r" name="temcom_lpf_a22_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temcom_lpf_a22" pos="13:0" rst="0">
        <comment>
          Coefficient a22 for Temcomp LPF
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temcom_lpf_g2_rg">
      <bits access="r" name="temcom_lpf_g2_rg_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="temcom_lpf_g2" pos="13:0" rst="0">
        <comment>
          Coefficient g2 for Temcomp LPF
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="temcom_temp_ct">
      <bits access="r" name="temcom_temp_ct_reserved_0" pos="15:10" rst="0">
      </bits>
      <bits access="r" name="temcom_pout_val_rg" pos="9" rst="0">
        <comment>
          valid indication of temcom_pwd_dout after assert temcom_pout_load to avoid metastability. The temcom_pwd_dout is stable when this register is high
        </comment>
      </bits>
      <bits access="rw" name="temcom_pout_load" pos="8" rst="0">
        <comment>
          start to load the result of thermometer. Before next load, set it low firstly
        </comment>
      </bits>
      <bits access="rw" name="temcom_temp_lpf3_bypass" pos="7" rst="0">
        <comment>
          temperature calibration LPF bypass, high valid
        </comment>
      </bits>
      <bits access="rw" name="temcom_temp_ushift" pos="6:4" rst="0">
        <comment>
          temperature calibration LPF shift value
0 : left shift by 7 bit
1 : left shift by 6 bit
2 : left shift by 5 bit
3 : left shift by 4 bit
4 : left shift by 3 bit
5 : left shift by 2 bit
6 : left shift by 1 bit
7 : left shift by 0 bit

        </comment>
      </bits>
      <bits access="rw" name="temcom_temp_bw_sel" pos="3:2" rst="0">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="rw" name="temcom_temp_lpf_bypass" pos="1" rst="0">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="rw" name="temcom_temp_hold_en" pos="0" rst="0">
        <comment>
          no use
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="temcom_dout_reg">
      <bits access="r" name="temcom_pwd_dout" pos="15:0" rst="32768">
        <comment>
          The result of thermometer
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_pcom_ct">
      <bits access="r" name="txdp_pcom_ct_reserved_0" pos="15:11" rst="0">
      </bits>
      <bits access="rw" name="txdp_pcom_bypass" pos="10" rst="0">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="rw" name="txdp_pcom_upd" pos="9" rst="0">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="rw" name="txdp_pcom_upd_timer" pos="8:1" rst="0">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="rw" name="txdp_pcom_zin_hi" pos="0" rst="0">
        <comment>
          no use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_pcom_zin_lo_rg">
      <bits access="rw" name="txdp_pcom_zin_lo" pos="15:0" rst="0">
        <comment>
          no use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dfe_sw_clkgate_en_rg">
      <bits access="r" name="dfe_sw_clkgate_en_rg_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dfe_sw_clkgate_en" pos="0" rst="0">
        <comment>
          Globle clock gating disable register
0: no use
1: enable clock on all clock gating cells
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="mon_ct">
      <bits access="r" name="mon_ct_reserved_0" pos="15:4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dfe_monitor_sel" pos="3:1" rst="0">
        <comment>
          Monitor output selection
        </comment>
      </bits>
      <bits access="rw" name="txbuf_mon_sel" pos="0" rst="0">
        <comment>
          No use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_offset_re_rg">
      <bits access="r" name="dac_offset_re_rg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dac_offset_re" pos="11:0" rst="0">
        <comment>
          The offset on DAC real part
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_offset_im_rg">
      <bits access="r" name="dac_offset_im_rg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dac_offset_im" pos="11:0" rst="0">
        <comment>
          The offset on DAC image part
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_tx_amp_re_rg">
      <bits access="r" name="dac_tx_amp_re_rg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dac_tx_amp_re" pos="11:0" rst="0">
        <comment>
          The DAC real part on test mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="dac_tx_amp_im_rg">
      <bits access="r" name="dac_tx_amp_im_rg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dac_tx_amp_im" pos="11:0" rst="0">
        <comment>
          The DAC image part on test mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_cic2_mode_rg">
      <bits access="r" name="txdp_cic2_mode_rg_reserved_0" pos="15:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="txdp_cic2_cfg_mode" pos="2:0" rst="0">
        <comment>
          Interp.CIC2 configuration mode for WT:
000: 60, 16K to 960K
001: 30, 32K to 960K
010: 25, 38.4K to 960K
011: 10, 96K to 960K
others: 5, 192K to 960K
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="data_dac_ctrl">
      <bits access="r" name="data_dac_ctrl_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="data_dac_sel" pos="13:12" rst="0">
        <comment>
          selection of function DAC data or test DAC data
00/01: select function DAC data including sine waveform
10: select test DAC data in RXDP path
11: select test DAC data in TXDP path
        </comment>
      </bits>
      <bits access="rw" name="sine_enable_rg" pos="11" rst="0">
        <comment>
          enable sine waveform generation module
        </comment>
      </bits>
      <bits access="rw" name="rxdp_test_dac_en_rg" pos="10" rst="0">
        <comment>
          enable test DAC data in RXDP path
        </comment>
      </bits>
      <bits access="rw" name="rxdp_test_dac_sel_rg" pos="9:5" rst="0">
        <comment>
          select test DAC data in RXDP path
        </comment>
      </bits>
      <bits access="rw" name="txdp_test_dac_en_rg" pos="4" rst="0">
        <comment>
          enable test DAC data in TXDP path
        </comment>
      </bits>
      <bits access="rw" name="txdp_test_dac_sel_rg" pos="3:0" rst="0">
        <comment>
          select test DAC data in TXDP path
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sincos_amp">
      <bits access="r" name="sincos_amp_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="sincos_amp_rg" pos="11:0" rst="511">
        <comment>
          sine waveform amplitude
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sincos_fre_lo">
      <bits access="rw" name="sincos_fre_rg_lo" pos="15:0" rst="54613">
        <comment>
          bit [15:0] of sine waveform frequence
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sincos_fre_hi">
      <bits access="r" name="sincos_fre_hi_reserved_0" pos="15:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="sincos_fre_rg_hi" pos="6:0" rst="0">
        <comment>
          bit [22:16] of sine waveform frequence
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_bypass_reg">
      <bits access="rw" name="txdp_bypass_cic1" pos="15" rst="0">
        <comment>
          Interp. CIC1
0: SW bypass disable
1: SW bypass enable
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_gsm_gdeq" pos="14" rst="0">
        <comment>
          Group Delay Equ. when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_uphb5" pos="13" rst="0">
        <comment>
          Interp.HBF5
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_uphb4" pos="12" rst="0">
        <comment>
          Interp. HBF4
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_gdeq" pos="11" rst="0">
        <comment>
          Group Delay Equ.
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_polariq_lpf" pos="10" rst="0">
        <comment>
          LPF of DPD only when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_polariq_ampm" pos="9" rst="0">
        <comment>
          AMPM of DPD
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_polariq_split" pos="8" rst="0">
        <comment>
          Split of DPD
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_polariq" pos="7" rst="0">
        <comment>
          Whole DPD
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_rc" pos="6" rst="0">
        <comment>
          RC
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_gain" pos="5" rst="0">
        <comment>
          Gain
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_uphb3" pos="4" rst="0">
        <comment>
          Interp.HBF3 when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_uphb2" pos="3" rst="0">
        <comment>
          Interp.HBF2 when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_uphb1" pos="2" rst="0">
        <comment>
          Interp.HBF1
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_aclr_lpf" pos="1" rst="0">
        <comment>
          ACLR LPF
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_cic2" pos="0" rst="0">
        <comment>
          Interp. CIC2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="txdp_bypass_mode_reg">
      <bits access="rw" name="txdp_bypass_mode_cic1" pos="15" rst="0">
        <comment>
          Interp. CIC1
0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement
1: bypass controlled by SW. When it is set, txdp_bypass_cic1 will be used
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_gsm_gdeq" pos="14" rst="0">
        <comment>
          Group Delay Equ. when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_uphb5" pos="13" rst="0">
        <comment>
          Interp.HBF5
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_uphb4" pos="12" rst="0">
        <comment>
          Interp.HBF4
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_gdeq" pos="11" rst="0">
        <comment>
          Group Delay Equ.
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_polariq_lpf" pos="10" rst="0">
        <comment>
          LPF of DPD only when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_polariq_ampm" pos="9" rst="0">
        <comment>
          AMPM of DPD
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_polariq_split" pos="8" rst="0">
        <comment>
          Split of DPD
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_polariq" pos="7" rst="0">
        <comment>
          Whole DPD
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_rc" pos="6" rst="0">
        <comment>
          RC
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_gain" pos="5" rst="0">
        <comment>
          Gain
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_uphb3" pos="4" rst="0">
        <comment>
          Interp.HBF3 when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_uphb2" pos="3" rst="0">
        <comment>
          Interp.HBF2 when PolarIQ
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_uphb1" pos="2" rst="0">
        <comment>
          Interp.HBF1
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_aclr_lpf" pos="1" rst="0">
        <comment>
          ACLR LPF
        </comment>
      </bits>
      <bits access="rw" name="txdp_bypass_mode_cic2" pos="0" rst="0">
        <comment>
          Interp. CIC2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lvds_mode_reg">
      <bits access="rw" name="lvds_in_wt" pos="15" rst="0">
        <comment>
          LVDS is in WT mode
        </comment>
      </bits>
      <bits access="rw" name="en_clk_lvds2dfe_bb_rx" pos="14" rst="0">
        <comment>
          clock enable for BB RX when adc-dfe-lvds-bb, enable when lvds_rx_mode is 3
        </comment>
      </bits>
      <bits access="rw" name="en_clk_lvds2dfe_dfe_tx" pos="13" rst="0">
        <comment>
          clock enable for DFE TX when bb-lvds-dfe-dac, enable when lvds_rx_mode is 2
        </comment>
      </bits>
      <bits access="rw" name="en_clk_lvds2dfe_dfe_rx" pos="12" rst="0">
        <comment>
          clock enable for DFE RX when adc-lvds-dfe-bb, enable when lvds_rx_mode is 1
        </comment>
      </bits>
      <bits access="rw" name="en_clk_lvds2dfe_rf_tx" pos="11" rst="0">
        <comment>
          clock enable for RF TX when bb-dfe-lvds-dac, enable when lvds_rx_mode is 0
        </comment>
      </bits>
      <bits access="rw" name="en_clk_dfe2lvds" pos="10" rst="0">
        <comment>
          clock enable for lvds_tx, enable when lvds_tx_mode is 0/1/2. Also used when lvds_in_wt is enabled
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_clk_mux_bb_rx" pos="9" rst="0">
        <comment>
          clock mux for BB RX when adc-dfe-lvds-bb, enable when lvds_rx_mode is 3
1: lvds enable
0: lvds disable
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_clk_mux_dfe_rx" pos="8" rst="0">
        <comment>
          clock mux for DFE RX when adc-lvds-dfe-bb, enable when lvds_rx_mode is 1
1: lvds enable
0: lvds disable
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_clk_mux_rf_tx" pos="7" rst="0">
        <comment>
          clock enable for RF TX when bb-dfe-lvds-dac, enable when lvds_rx_mode is 0
1: lvds enable
0: lvds disable
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_clk_mode" pos="6:5" rst="0">
        <comment>
          3: dfe2lvds_clk for adc-dfe-lvds-bb, i.e., lvds_tx_mode is 2. Also used when lvds_in_wt is enabled
2: dfe2lvds_clk for bb-dfe-lvds-dac, i.e., lvds_tx_mode is 1
1: dfe2lvds_clk for bb-lvds-dfe-dac, i.e., lvds_tx_mode is 2
0: dfe2lvds_clk for adc-lvds-dfe-bb, i.e., lvds_tx_mode is 0
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_mode" pos="4:3" rst="0">
        <comment>
          3: lvds_rx in test mode(adc-dferx-lvds-bb)
2: lvds_rx in test mode(bb-lvds-dfe-dac)
1: lvds_rx in BB mode(adc-lvds-dfe-bb)
0: lvds_rx in RF mode(bb-dfe-lvds-dac)
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_mode" pos="2:1" rst="0">
        <comment>
          3: rsv
2: lvds_tx in test mode(adc-dfe-lvds-bb/bb-lvds-dfe-dac determined by data_dac_sel)
1: lvds_tx in BB mode(bb-dfe-lvds-dac)
0: lvds_tx in RF mode(adc-lvds-dfe-bb)
        </comment>
      </bits>
      <bits access="rw" name="lvds_enable" pos="0" rst="0">
        <comment>
          enable LVDS
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="lvds_swap_reg">
      <bits access="r" name="lvds_swap_reg_reserved_0" pos="15:2" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="rw" name="lvds_rx_swap" pos="1" rst="0">
        <comment>
          iq swap on lvds2dfe_data
        </comment>
      </bits>
      <bits access="rw" name="lvds_tx_swap" pos="0" rst="0">
        <comment>
          iq swap on dfe2lvds_data
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reserved_all_zeros_reg">
      <bits access="rw" name="rsv_all_zero" pos="15:0" rst="0">
        <comment>
          all zero bits, reserved for ECO
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reserved_all_ones_reg">
      <bits access="rw" name="rsv_all_ones" pos="15:0" rst="65535">
        <comment>
          all one bits, reserved for ECO
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="rda8909nez_dfe_regbank.xml">
</archive>
<archive relative = "rf_dig_comregs.xml">
<module name="rf_dig_comregs" category="RF_Dig">
        
    <hole size="64" />

    <reg name="Cause" protect="r">
        <bits name="Irq0_Cause" pos="7:0" access="r" rst="0">
            <comment>When read from the X/Bcpu, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask.
                <br/>When read from the RISCV, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask.
            </comment>
            <options><mask/><shift/></options>
        </bits>
        <bits name="Irq1_Cause" pos="15:8" access="r" rst="0">
            <comment>When read from the X/Bcpu, this return the cause of interruption, basically the set/clear register X_Irq1 part masked with X_Irq1_Mask.
                <br/>When read from the RISCV, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask.
            </comment>
            <options><mask/><shift/></options>
        </bits>
    </reg>
    <reg name="Mask_Set" protect="rw">
        <bits name="Irq0_Mask_Set" pos="7:0" access="rs" rst="0">
            <comment>When read: returns the value of the Irq0_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq0_Mask masks the set/clear register to trigger interrupts on the CPU/RISCV using line 0.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="Irq1_Mask_Set" pos="15:8" access="rs" rst="0">
            <comment>When read: returns the value of the Irq1_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq1_Mask masks the set/clear register to trigger interrupts on the CPU/RISCV using line 1.
            </comment>
           <options><mask/><shift/><default/></options>
        </bits>
    </reg>
    <reg name="Mask_Clr" protect="rw">
        <bits name="Irq0_Mask_Clr" pos="7:0" access="rc" rst="0">
            <comment>When read: returns the value of the Irq0_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq0_Mask masks the set/clear register to trigger interrupts on the CPU/RISCV using line 0.
             </comment>
            <options><mask/><shift/><default/></options>
         </bits>
        <bits name="Irq1_Mask_Clr" pos="15:8" access="rc" rst="0">
            <comment>When read: returns the value of the Irq1_Mask register.
                <br/>When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                <br/>The Irq1_Mask masks the set/clear register to trigger interrupts on the CPU/RISCV using line 1.
             </comment>
             <options><mask/><shift/><default/></options>
        </bits>
    </reg>
    <reg name="ItReg_Set" protect="rw">
        <comment>If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously from both CPUs and affecting the same bits, the priority is given to set a bit.</comment>
        <bits name="Irq0_Set" pos="7:0" access="rs" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the CPU/RISCV if enabled.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="Irq1_Set" pos="15:8" access="rs" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the CPU/RISCV if enabled.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bitgroup name="Irq">
            <entry ref="Irq0_Set"/>
            <entry ref="Irq1_Set"/>
        </bitgroup>
    </reg>
    
    <reg name="ItReg_Clr" protect="rw">
        <comment>If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously from both CPUs and affecting the same bits, the priority is given to set a bit.</comment>
        <bits name="Irq0_Clr" pos="7:0" access="rc" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the CPU/RISCV if enabled.
            </comment>
        </bits>
        <bits name="Irq1_Clr" pos="15:8" access="rc" rst="0">
            <comment>When read, returns the value of the set/clear register.
                <br/>When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                <br/>These bits can also trigger interrupts on the CPU/RISCV if enabled.
            </comment>
        </bits>
    </reg>

</module>
</archive>
<archive relative = "rf_dig_ctrl.xml">

<module name="rf_dig_ctrl" category="RF_Dig">

  <reg name="cfg_clk_wdt" protect="rw">
    <bits access="rw" name="div_update" pos="15:15" rst="0x0">
    </bits>
    <bits access="rw" name="denom" pos="13:0" rst="0x400">
    </bits>
  </reg>

  <reg name="cfg_rst_1" protect="rw">
    <bits access="rw" name="dfe_txdp_rst" pos="15:15" rst="0x0">
        <comment>Dfe_txdp_rst(Default rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="dfe_rxdp_rst" pos="14:14" rst="0x0">
        <comment>Dfe_rxdp_rst(Default rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="dfe_cgu_rst" pos="13:13" rst="0x1">
        <comment>Dfe_cgu_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="dfe_reg_rst" pos="12:12" rst="0x1">
        <comment>Dfe_reg_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="intf_rst" pos="11:11" rst="0x1">
        <comment>Interface_module_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="intf_apbreg_rst" pos="10:10" rst="0x1">
        <comment>Interface_apbreg_module_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="intf_spireg_rst" pos="9:9" rst="0x1">
        <comment>Interface_spireg_module_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="mipi_rst" pos="8:8" rst="0x1">
        <comment>Mipi_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="uart_rst" pos="7:7" rst="0x1">
        <comment>Uart_module_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="comregs_rst" pos="6:6" rst="0x1">
        <comment>Comregs_module_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="wdt_rst" pos="5:5" rst="0x1">
        <comment>WatchDog_module_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="timer2_rst" pos="4:4" rst="0x1">
        <comment>Timer2_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="timer1_rst" pos="3:3" rst="0x1">
        <comment>Timer1_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="timer0_rst" pos="2:2" rst="0x1">
        <comment>Timer0_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="pulp_dbg_rst" pos="1:1" rst="0x1">
        <comment>PulpCore_Debug_Unit_rst(Default release rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
    <bits access="rw" name="pulp_rst" pos="0:0" rst="0x0">
        <comment>PulpCore_rst(Default rst state), 1: release module rst, 0: rst module
        </comment>
    </bits>
  </reg>

  <reg name="cfg_rst_2" protect="rw">
    <bits access="rw" name="cfg_rst_2" pos="15:0" rst="0xffff">
        <comment>Reserved For Future, Not Be Used
        </comment>
    </bits>
  </reg>

  <reg name="en_clk_1" protect="rw">
    <bits access="rw" name="en_clk_1" pos="15:0" rst="0xffff">
    </bits>
  </reg>

  <reg name="en_clk_2" protect="rw">
    <bits access="rw" name="en_clk_2" pos="15:0" rst="0xffff">
    </bits>
  </reg>

  <reg name="gpio_out" protect="rw">
    <bits access="rw" name="gpio_out" pos="6:0" rst="0x0">
    </bits>
  </reg>

  <reg name="gpio_oen" protect="rw">
    <bits access="rw" name="gpio_oen" pos="6:0" rst="0x7f">
    </bits>
  </reg>

  <reg name="gpio_in" protect="rw">
    <bits access="rw" name="gpio_dsel" pos="15:12" rst="0x0">
    </bits>
    <bits access="r" name="gpio_in" pos="6:0" rst="0x0">
    </bits>
  </reg>

  <reg name="gpio_ruen" protect="rw">
    <bits access="rw" name="gpio_ruen" pos="6:0" rst="0x0">
    </bits>
  </reg>

  <reg name="gpio_rden" protect="rw">
    <bits access="rw" name="gpio_rden" pos="6:0" rst="0x0">
    </bits>
  </reg>

  <reg name="gpio_pdn" protect="rw">
    <bits access="rw" name="gpio_pdn" pos="6:0" rst="0x0">
    </bits>
  </reg>

  <reg name="debug_reg" protect="rw">
    <bits access="rw" name="scratch" pos="15:0" rst="0x0">
    </bits>
  </reg>

  <reg name="io_ctrl" protect="rw">
    <bits access="rw" name="gpio_ibit" pos="13:0" rst="0x0">
    </bits>
  </reg>

  <reg name="misc_ctrl" protect="rw">
    <bits access="rw" name="mipi_sel" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw" name="mipi_clk_half_sel" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw" name="bypass_wdt_rst" pos="0:0" rst="0x1">
    </bits>
  </reg>

</module>
</archive>
<archive relative = "rf_dig_ram.xml">
  <var name="RFDIG_IRAM_SIZE"   value="20*1024" />      
  <var name="RFDIG_DRAM_SIZE"   value="4*1024" />       

  
  <module name="rf_dig_iram" category="RF_Dig">
    <memory name="ram_array" size="RFDIG_IRAM_SIZE">
      <comment>I-RAM Space
      </comment>
    </memory>
  </module>

  
  <module name="rf_dig_dram" category="RF_Dig">
    <memory name="ram_array" size="RFDIG_DRAM_SIZE">
      <comment>D-RAM Space
      </comment>
    </memory>
  </module>


</archive>
<archive relative = "rf_dig_timer.xml">

<module name="rf_dig_timer" category="RF_Dig">

    <reg name="CTRL" protect="rw">
        <bits name="IntEn" pos="3" access="rw" rst="0">
            <comment>Timer interrupt enable.
            </comment>
        </bits>
        <bits name="ExtClk" pos="2" access="rw" rst="0">
            <comment>Select external input as clock.
            </comment>
        </bits>
        <bits name="ExtEn" pos="1" access="rw" rst="0">
            <comment>Select external input as enable.
            </comment>
        </bits>
        <bits name="Enable" pos="0" access="rw" rst="0">
            <comment>Enable.
            </comment>
        </bits>
    </reg>

    <reg name="VALUE" protect="rw">
        <bits name="CurVal" pos="31:0" access="rw" rst="0">
            <comment>Current Value.
            </comment>
        </bits>
    </reg>

    <reg name="RELOAD" protect="rw">
        <bits name="ReLdVal" pos="31:0" access="rw" rst="0">
            <comment>Reload value. A write to this register sets the current value.
            </comment>
        </bits>
    </reg>
 
    <reg name="INT" protect="rw">
        <bits name="Timer_Int" pos="0" access="rw" rst="0">
            <comment>Timer interrupt. Write one to clear.
            </comment>
        </bits>
    </reg>
 
    <hole size="32256" />

    <reg name="PID4" protect="ro">
        <bits name="Block_cnt" pos="7:4" access="ro" rst="0x0">
            <comment>Block Count.
            </comment>
        </bits>
        <bits name="JepC" pos="3:0" access="ro" rst="0x4">
            <comment>jep106_c_code.
            </comment>
        </bits>
    </reg>

    <reg name="PID5" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 5.
            </comment>
        </bits>
    </reg>

    <reg name="PID6" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 6.
            </comment>
        </bits>
    </reg>

    <reg name="PID7" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 7.
            </comment>
        </bits>
    </reg>

    <reg name="PID0" protect="ro">
        <bits name="Part_numb_7_0" pos="7:0" access="ro" rst="0x22">
            <comment>Part number[7:0]
            </comment>
        </bits>
    </reg>

    <reg name="PID1" protect="ro">
        <bits name="jep106_id_3_0" pos="7:4" access="ro" rst="0xb">
            <comment>jep106_id_3_0
            </comment>
        </bits>
        <bits name="Part_numb_11_8" pos="3:0" access="ro" rst="0x8">
            <comment>Part number[11:8]
            </comment>
        </bits>
    </reg>

    <reg name="PID2" protect="ro">
        <bits name="Revision_7_4" pos="7:4" access="ro" rst="0x1">
            <comment>Revision
            </comment>
        </bits>
        <bits name="jedec_used" pos="3" access="ro" rst="0x1">
            <comment>jedec_used
            </comment>
        </bits>
        <bits name="jep106_id_6_4" pos="2:0" access="ro" rst="0">
            <comment>jep106_id_6_4
            </comment>
        </bits>
    </reg>

    <reg name="PID3" protect="ro">
        <bits name="ECO_VER" pos="7:4" access="ro" rst="0">
            <comment>ECO version number.
            </comment>
        </bits>
        <bits name="Cust_mod_numb" pos="3:0" access="ro" rst="0">
            <comment>Customer modification number.
            </comment>
        </bits>
    </reg>

    <reg name="CID0" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0x0d">
            <comment>Component ID register 0.
            </comment>
        </bits>
    </reg>

    <reg name="CID1" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0xf0">
            <comment>Component ID register 1.
            </comment>
        </bits>
    </reg>

    <reg name="CID2" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0x05">
            <comment>Component ID register 2.
            </comment>
        </bits>
    </reg>

    <reg name="CID3" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0xb1">
            <comment>Component ID register 3.
            </comment>
        </bits>
    </reg>

</module>

</archive>
<archive relative = "rf_dig_uart.xml">

<module name="rf_dig_uart" category="RF_Dig">

    <reg name="DATA" protect="rw">
        <bits name="Data_value" pos="7:0" access="rw" rst="-">
            <comment>Received data.
                     Transmit data.
            </comment>
        </bits>
    </reg>

    <reg name="STATE" protect="rw">
        <bits name="RX_overrun" pos="3" access="rw" rst="0">
            <comment>RX buffer overrun, write 1 to clear.
            </comment>
        </bits>
        <bits name="TX_overrun" pos="2" access="rw" rst="0">
            <comment>TX buffer overrun, write 1 to clear.
            </comment>
        </bits>
        <bits name="RX_Full" pos="1" access="ro" rst="0">
            <comment>RX buffer full, read-only.
            </comment>
        </bits>
        <bits name="TX_Full" pos="0" access="ro" rst="0">
            <comment>TX buffer full, read-only.
            </comment>
        </bits>
    </reg>

    <reg name="CTRL" protect="rw">
        <bits name="H_speed_tst" pos="6" access="rw" rst="0">
            <comment>High-speed test mode for TX only.
            </comment>
        </bits>
        <bits name="RX_overrun_int" pos="5" access="rw" rst="0">
            <comment>RX overrun interrupt enable.
            </comment>
        </bits>
        <bits name="TX_overrun_int" pos="4" access="rw" rst="0">
            <comment>TX overrun interrupt enable.
            </comment>
        </bits>
        <bits name="RX_int_en" pos="3" access="rw" rst="0">
            <comment>RX interrupt enable.
            </comment>
        </bits>
        <bits name="TX_int_en" pos="2" access="rw" rst="0">
            <comment>TX interrupt enable.
            </comment>
        </bits>
        <bits name="RX_En" pos="1" access="rw" rst="0">
            <comment>RX enable.
            </comment>
        </bits>
        <bits name="TX_En" pos="0" access="rw" rst="0">
            <comment>TX enable.
            </comment>
        </bits>
    </reg>
 
    <reg name="INT" protect="rw">
        <bits name="RX_int_en" pos="3" access="rw" rst="0">
            <comment>RX overrun interrupt. Write 1 to clear.
            </comment>
        </bits>
        <bits name="TX_int_en" pos="2" access="rw" rst="0">
            <comment>TX overrun interrupt. Write 1 to clear.
            </comment>
        </bits>
        <bits name="RX_En" pos="1" access="rw" rst="0">
            <comment>RX interrupt. Write 1 to clear.
            </comment>
        </bits>
        <bits name="TX_En" pos="0" access="rw" rst="0">
            <comment>TX interrupt. Write 1 to clear.
            </comment>
        </bits>
    </reg>
 
    <reg name="BAUDDIV" protect="rw">
        <bits name="Baud_rate_div" pos="19:0" access="rw" rst="0">
            <comment>Baud rate divider. The minimum number is 16.
            </comment>
        </bits>
    </reg>
 
    <hole size="32224" />

    <reg name="PID4" protect="ro">
        <bits name="Block_cnt" pos="7:4" access="ro" rst="0x0">
            <comment>Block Count.
            </comment>
        </bits>
        <bits name="JepC" pos="3:0" access="ro" rst="0x4">
            <comment>jep106_c_code.
            </comment>
        </bits>
    </reg>

    <reg name="PID5" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 5.
            </comment>
        </bits>
    </reg>

    <reg name="PID6" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 6.
            </comment>
        </bits>
    </reg>

    <reg name="PID7" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 7.
            </comment>
        </bits>
    </reg>

    <reg name="PID0" protect="ro">
        <bits name="Part_numb_7_0" pos="7:0" access="ro" rst="0x22">
            <comment>Part number[7:0]
            </comment>
        </bits>
    </reg>

    <reg name="PID1" protect="ro">
        <bits name="jep106_id_3_0" pos="7:4" access="ro" rst="0xb">
            <comment>jep106_id_3_0
            </comment>
        </bits>
        <bits name="Part_numb_11_8" pos="3:0" access="ro" rst="0x8">
            <comment>Part number[11:8]
            </comment>
        </bits>
    </reg>

    <reg name="PID2" protect="ro">
        <bits name="Revision_7_4" pos="7:4" access="ro" rst="0x1">
            <comment>Revision
            </comment>
        </bits>
        <bits name="jedec_used" pos="3" access="ro" rst="0x1">
            <comment>jedec_used
            </comment>
        </bits>
        <bits name="jep106_id_6_4" pos="2:0" access="ro" rst="0">
            <comment>jep106_id_6_4
            </comment>
        </bits>
    </reg>

    <reg name="PID3" protect="ro">
        <bits name="ECO_VER" pos="7:4" access="ro" rst="0">
            <comment>ECO version number.
            </comment>
        </bits>
        <bits name="Cust_mod_numb" pos="3:0" access="ro" rst="0">
            <comment>Customer modification number.
            </comment>
        </bits>
    </reg>

    <reg name="CID0" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0x0d">
            <comment>Component ID register 0.
            </comment>
        </bits>
    </reg>

    <reg name="CID1" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0xf0">
            <comment>Component ID register 1.
            </comment>
        </bits>
    </reg>

    <reg name="CID2" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0x05">
            <comment>Component ID register 2.
            </comment>
        </bits>
    </reg>

    <reg name="CID3" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0xb1">
            <comment>Component ID register 3.
            </comment>
        </bits>
    </reg>

</module>

</archive>
<archive relative = "rf_dig_watchdog.xml">

<module name="rf_dig_watchdog" category="RF_Dig">

    <reg name="LOAD" protect="rw">
        <bits name="Wdt_Load" pos="31:0" access="rw" rst="0xffffffff">
            <comment>The WDOGLOAD Register contains the value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value. The minimum valid value for WDOGLOAD is 1.
            </comment>
        </bits>
    </reg>

    <reg name="Value" protect="ro">
        <bits name="Wdt_Val" pos="31:0" access="ro" rst="0xffffffff">
            <comment>The WDOGVALUE Register gives the current value of the decrementing counter.
            </comment>
        </bits>
    </reg>

    <reg name="CTRL" protect="wo">
        <bits name="RESEN" pos="1" access="wo" rst="0">
            <comment>Enable watchdog reset output, WDOGRES. Acts as a mask for the reset output. Set HIGH to enable the reset, or LOW to disable the reset.
            </comment>
        </bits>
        <bits name="INTEN" pos="0" access="wo" rst="0">
            <comment>Enable the interrupt event, WDOGINT. Set HIGH to enable the counter and the interrupt, or LOW to disable the counter and interrupt. Reloads the counter from the value in WDOGLOAD when the interrupt is enabled, after previously being disabled.
            </comment>
        </bits>
    </reg>
 
    <reg name="INTCLR" protect="wo">
        <bits name="INTCLR" pos="0" access="wo" rst="0">
            <comment>A write of any value to the WDOGINTCLR Register clears the watchdog interrupt, and reloads the counter from the value in WDOGLOAD.
            </comment>
        </bits>
    </reg>
 
    <reg name="RIS" protect="ro">
        <bits name="RIS" pos="0" access="ro" rst="0">
            <comment>Raw interrupt status from the counter
            </comment>
        </bits>
    </reg>
 
    <reg name="MIS" protect="ro">
        <bits name="MIS" pos="0" access="ro" rst="0">
            <comment>Enabled interrupt status from the counter
            </comment>
        </bits>
    </reg>
 
    <hole size="24384" />

    <reg name="LCK" protect="ro">
        <bits name="En_reg" pos="31:1" access="rw" rst="0x1acce551">
            <comment>Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value.
            </comment>
        </bits>
        <bits name="En_status" pos="0" access="ro" rst="0">
            <comment>
0: Write access to all other registers is enabled. This is the default.
1: Write access to all other registers is disabled.
            </comment>
        </bits>
    </reg>
 
    <hole size="6112" />

    <reg name="TST" protect="rw">
        <bits name="test_mode" pos="0" access="rw" rst="0">
            <comment>When set HIGH, places the watchdog into integration test mode
            </comment>
        </bits>
    </reg>
 
    <reg name="TSTO" protect="rw">
        <bits name="WDOGINT" pos="1" access="rw" rst="0">
            <comment>Value output on WDOGINT when in Integration Test Mode
            </comment>
        </bits>
        <bits name="WDOGRES" pos="0" access="rw" rst="0">
            <comment>Value output on WDOGRES when in Integration Test Mode
            </comment>
        </bits>
    </reg>
 
    <hole size="1600" />

    <reg name="PID4" protect="ro">
        <bits name="Block_cnt" pos="7:4" access="ro" rst="0x0">
            <comment>Block Count.
            </comment>
        </bits>
        <bits name="JepC" pos="3:0" access="ro" rst="0x4">
            <comment>jep106_c_code.
            </comment>
        </bits>
    </reg>

    <reg name="PID5" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 5.
            </comment>
        </bits>
    </reg>

    <reg name="PID6" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 6.
            </comment>
        </bits>
    </reg>

    <reg name="PID7" protect="ro">
        <bits name="PerID" pos="7:0" access="ro" rst="0">
            <comment>Peripheral ID register 7.
            </comment>
        </bits>
    </reg>

    <reg name="PID0" protect="ro">
        <bits name="Part_numb_7_0" pos="7:0" access="ro" rst="0x22">
            <comment>Part number[7:0]
            </comment>
        </bits>
    </reg>

    <reg name="PID1" protect="ro">
        <bits name="jep106_id_3_0" pos="7:4" access="ro" rst="0xb">
            <comment>jep106_id_3_0
            </comment>
        </bits>
        <bits name="Part_numb_11_8" pos="3:0" access="ro" rst="0x8">
            <comment>Part number[11:8]
            </comment>
        </bits>
    </reg>

    <reg name="PID2" protect="ro">
        <bits name="Revision_7_4" pos="7:4" access="ro" rst="0x1">
            <comment>Revision
            </comment>
        </bits>
        <bits name="jedec_used" pos="3" access="ro" rst="0x1">
            <comment>jedec_used
            </comment>
        </bits>
        <bits name="jep106_id_6_4" pos="2:0" access="ro" rst="0">
            <comment>jep106_id_6_4
            </comment>
        </bits>
    </reg>

    <reg name="PID3" protect="ro">
        <bits name="ECO_VER" pos="7:4" access="ro" rst="0">
            <comment>ECO version number.
            </comment>
        </bits>
        <bits name="Cust_mod_numb" pos="3:0" access="ro" rst="0">
            <comment>Customer modification number.
            </comment>
        </bits>
    </reg>

    <reg name="CID0" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0x0d">
            <comment>Component ID register 0.
            </comment>
        </bits>
    </reg>

    <reg name="CID1" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0xf0">
            <comment>Component ID register 1.
            </comment>
        </bits>
    </reg>

    <reg name="CID2" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0x05">
            <comment>Component ID register 2.
            </comment>
        </bits>
    </reg>

    <reg name="CID3" protect="ro">
        <bits name="CompID" pos="7:0" access="ro" rst="0xb1">
            <comment>Component ID register 3.
            </comment>
        </bits>
    </reg>

</module>

</archive>
<archive relative = "rf_if.xml">
<module name="rf_if" category="Baseband">
  
   
   <reg protect="rw" name="Buffer">
    <bits access="rw" name="Rx_Tx data" pos="31:0" rst="no">
      <comment>In read mode this register contains the sample received on the Rx chain. I component is located on bit[15:0] and Q component is located on bit[31:16].
      <br />This register accesses to the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data sample arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur.
      <br />The data written[29:0] into this register is the data transmitted. Any attempt to write data when the FIFO is full results in the write data being lost.
      </comment>
    </bits>
  </reg>

  <reg protect="rw" name="Ctrl">
    <bits access="rw" name="Enable" pos="0" rst="0">
      <options>
        <option name="Disable" value="0" />
        <option name="Enable" value="1" />
      </options>
      <comment>Turn on/off the rf_if interface</comment>
    </bits>
    
    <bits access="rw" name="DigRF Enable" pos="1" rst="0">
      <options>
        <option name="Disable" value="0"><comment>Analog more selected</comment></option>
        <option name="Enable" value="1"><comment>DigRF mode selected</comment></option>
      </options>
      <comment>Turn on/off the DigRF mode</comment>
    </bits>
    
    <bits access="rw" name="Rx overflow Enable" pos="4" rst="1">
      <options>
        <option name="Disable" value="0"><comment>Disable (mask) Rx fifo overflow interrupt</comment></option>
        <option name="Enable" value="1"><comment>Enable Rx fifo overflow interrupt</comment></option>
      </options>
      <comment>Rx Fifo Overflow interrupt Enable</comment>
    </bits>
    
    <bits access="rw" name="Rx Cal Bypass" pos="5" rst="1">
      <options>
        <option name="Enabled" value="0" />
        <option name="Bypassed" value="1" />
      </options>
      <comment>Calibration bypass</comment>
    </bits>
    
    <bits access="rw" name="Rx Swap I_Q" pos="6" rst="0">
      <options>
        <option name="NO" value="0"><comment>No Swap</comment></option>
        <option name="YES" value="1"><comment>Swap I/Q</comment></option>
      </options>
      <comment>Rx swap I/Q</comment>
    </bits>
    
    <bits access="rw" name="Rx Force ADC On" pos="7" rst="0">
      <options>
        <option name="NO" value="0"><comment>No forced, Rx_On output controlled by TCO_RX_ON signal from the TCU</comment></option>
        <option name="YES" value="1"><comment>Forced ADC on;Rx_On output always high</comment></option>
      </options>
      <comment>Force Rx On. This bit is used only with the analog option.</comment>
    </bits>

    <bits access="rw" name="Rx Force Dec On" pos="8" rst="0">
      <options>
        <option name="NO" value="0"><comment>No forced, decimator controlled by Rx_dec_on signal from the TCU</comment></option>
        <option name="YES" value="1"><comment>Forced; decimator always on</comment></option>
      </options>
      <comment>Force Decimator On</comment>
    </bits>
    
    <bits access="w" name="Rx Force SOC" pos="9" rst="no">
      <comment>Force start of calibation in receive mode
        <br />Writing a 1 to this bit launch the calibration phase. Write only bit, this bit doesn't need to be cleared.
      </comment>
    </bits>
    
    <bits access="w" name="Rx Fifo Reset" pos="10" rst="no">
      <comment>Writing a 1 to this bit resets and flush the receive Fifo. 
        <br />Write only bit, this bit doesn't need to be cleared.
      </comment>
    </bits>
    
  
    <bits access="rw" name="Tx overflow Enable" pos="16" rst="1">
      <options>
        <option name="Disable" value="0"><comment>Disable (mask) Tx fifo overflow interrupt</comment></option>
        <option name="Enable" value="1"><comment>Enable Tx fifo overflow interrupt</comment></option>
      </options>
      <comment>Tx Fifo Overflow interrupt Enable</comment>
    </bits>
    
    <bits access="rw" name="Tx underflow Enable" pos="17" rst="1">
      <options>
        <option name="Disable" value="0"><comment>Disable (mask) Tx fifo undeflow interrupt</comment></option>
        <option name="Enable" value="1"><comment>Enable Tx fifo underflow interrupt</comment></option>
      </options>
      <comment>Tx Fifo Underflow interrupt Enable:</comment>
    </bits>
    
    <bits access="rw" name="Tx Force DAC On" pos="18" rst="0">
      <options>
        <option name="NO" value="0"><comment>No forced, Tx_On output controlled by TCO_TX_ON signal from the TCU</comment></option>
        <option name="YES" value="1"><comment>Forced DAC on; Tx_On output always high</comment></option>
      </options>
      <comment>Force DAC On. This bit is used only with the analog option.</comment>
    </bits>
    
    <bits access="rw" name="Tx Force DAC Off" pos="19" rst="0">
      <options>
        <option name="NO" value="0"><comment>No forced, Tx_On output controlled by TCO_TX_ON signal from the TCU</comment></option>
        <option name="YES" value="1"><comment>Forced DAC Off; Tx_On output always low</comment></option>
      </options>
      <comment>Force DAC Off. This bit is used only with the analog option.</comment>
    </bits>


    <bits access="rw" name="Tx Force oen" pos="20" rst="0">
      <options>
        <option name="NO" value="0"><comment>No forced, Tx_Oen controlled by TCO_TX_OEN signal from the TCU</comment></option>
        <option name="YES" value="1"><comment>Forced; Tx_Oen always high, Low pass output in HZ</comment></option>
      </options>
      <comment>Force Tx Oen. This bit is used only with the analog option.</comment>
    </bits>
  
    <bits access="rw" name="Tx Force GMSK On" pos="21" rst="0">
      <options>
        <option name="NO" value="0"><comment>No forced, transmit serial interface controlled by TCO_GMSK_ON signal from the TCU</comment></option>
        <option name="YES" value="1"><comment>Forced; serializer always enabled</comment></option>
      </options>
      <comment>Force GMSK On.</comment>
    </bits>
    <bits access="rw" name="Tx Swap I_Q" pos="22" rst="0">
      <options>
        <option name="NO" value="0"><comment>No Swap</comment></option>
        <option name="YES" value="1"><comment>Swap I/Q</comment></option>
      </options>
      <comment>Tx swap I/Q. This bit is used only with the analog option.</comment>
    </bits>
 
    <bits access="w" name="Tx Fifo Reset" pos="23" rst="no">
      <comment>Writing a 1 to this bit resets and flush the transmit Fifo. 
        <br />Write only bit, this bit doesn.t need to be cleared.
      </comment>
    </bits>
    
    <bits access="rw" name="DigRF Rx Rate" pos="24" rst="1">
      <options>
        <option name="ONE" value="0"><comment>One sample per symbol</comment></option>
        <option name="TWO" value="1"><comment>Two samples per symbol</comment></option>
      </options>
      <comment>Rx rate for DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled)
      </comment>
    </bits>
    
    <bits access="rw" name="DigRF Rx Clk Pol" pos="25" rst="1">
      <comment>Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
        <br />0 = No inversion
        <br />1 = Invert clock polarity
      </comment>
    </bits>
    
    <bits access="rw" name="DigRF Tx mode" pos="26" rst="1">
      <options>
        <option name="Stream" value="0"></option>
        <option name="Block" value="1"></option>
      </options>
      <comment>Tx mode for the DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled)
      </comment>
    </bits>

    <bits access="rw" name="DigRF Tx Clk Pol" pos="27" rst="1">
      <comment>Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
        <br />0 = No inversion
        <br />1 = Invert clock polarity
      </comment>
    </bits>

    <bits access="rw" name="DigRF Sample Size" pos="30:28" rst="all1" display="hex">
      <comment>Shift input sample in DigRF mode only. 
        <br />The Rx sample are on 16-bit, this field select a variable of bit among 16.
        <br />000 = 16-bit selected
        <br />001 = 15-bit selected 
        <br />010 = 14-bit selected
        <br />011 = 13-bit selected
        <br />100 = 12-bit selected
      </comment>
    </bits>
    <bits access="rw" name="DigRF Alignement Select" pos="31" rst="1" display="hex">
      <comment>Select the sample alignement in DigRF mode only.. 
        <br />0 = MSB aligned sample
        <br />1 = LSB aligned sample 
      </comment>
    </bits>
  </reg>
  

    <reg protect="r" name="Status">
      <bits access="r" name="Rx Fifo level" pos="4:0" rst="0">
        <comment>Those bits indicate the number of data available in the Rx Fifo.</comment>
      </bits>
      <bits access="r" name="Tx Fifo level" pos="6:5" rst="0">
        <comment>Those bits indicate the number of data available in the Tx Fifo. Those data will be sent.
        </comment>
      </bits>
      <bits access="r" name="Rx Overflow Cause" pos="8" rst="0">
        <comment>Rx overflow cause register
        <br />This bit indicates that an interruption was generated when the Rx fifo is overflow. 
        <br />This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written.
        </comment>
      </bits>
      <bits access="r" name="Tx Overflow Cause" pos="9" rst="0">
        <comment>Tx overflow cause register
        <br />This bit indicates that an interruption was generated when the Tx fifo is overflow. 
        <br />This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written.
        </comment>
      </bits>
      <bits access="r" name="Tx Underflow Cause" pos="10" rst="0">
        <comment>Tx underflow cause register
        <br />This bit indicates that an interruption was generated when the Tx fifo is underflow. 
        <br />This bit is cleared when the Tx_underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written.
        </comment>
      </bits>
      <bits access="r" name="Rx Overflow Status" pos="16" rst="0">
        <comment>This bit indicates that the receiver received a new sample when the FIFO was already full. 
        <br />The new sample is discarded. This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written
        </comment>
      </bits>
      <bits access="r" name="Tx Overflow Status" pos="17" rst="0">
        <comment>This bit indicates that the user tried to write on the FIFO while it was already full. 
        <br />This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written
        </comment>
      </bits>
      <bits access="r" name="Tx Underflow Status" pos="18" rst="0">
        <comment>This bit indicates that the modulator tried to read on the FIFO while it was empty. 
        <br />This bit is cleared when the Tx_Underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written
        </comment>
      </bits>
    </reg>

    <reg protect="w" name="Interruption_clear">
      <bits access="w" name="Rx Overflow" pos="0" rst="no">
        <comment>Clear Rx Interrupt Overflow interrupt.
        </comment>
      </bits>
      <bits access="w" name="Tx Overflow" pos="1" rst="no">
        <comment>Clear Tx Interrupt Overflow interrupt.
        </comment>
      </bits>
      <bits access="w" name="Tx Underflow" pos="2" rst="no">
        <comment>Clear Tx Interrupt Underflow interrupt.
        </comment>
      </bits>
    </reg>
    <reg count="4" name="Tx Burst descriptor" protect="rw">
        <bits name="NB symbols" pos="7:0" access="rw" rst="0">
            <comment>Number of symbol to transmit
            </comment>
        </bits>
        <bits name="Modulation" pos="16" access="rw" rst="0">
            <comment>0 for GMSK, 1 for 8PSK 
            </comment>
        </bits>
        <bits name="End Burst" pos="24" access="rw" rst="0">
            <comment>Indicate an end of the transmit for this current burst
            </comment>
        </bits>
    </reg>

    <reg protect="r" name="Rx Offset">
      <bits access="r" name="Rx_Offset_I" pos="15:0" rst="all0" display="hex">
        <comment>Rx offset measured after calibration for I channel
        </comment>
      </bits>
      <bits access="r" name="Rx_Offset_Q" pos="31:16" rst="all0" display="hex">
        <comment>Rx offset measured after calibratio for Q channel
        </comment>
      </bits>
  </reg>

    <reg protect="rw" name="Rx Gain">
      <bits access="rw" name="Rx_Gain_dig" pos="9:0" rst="all0" display="hex">
        <comment>Rx Gain digital
        </comment>
      </bits>
      <bits access="rw" name="Rx_Gain_ana" pos="12:10" rst="all0" display="hex">
        <comment>Rx Gain analog
        </comment>
      </bits>
      <bits access="rw" name="Rx_Gain_en" pos="13" rst="all0" display="hex">
        <comment>Rx Gain  enable
        </comment>
      </bits>
  </reg>

    <hole size="192"/>

   
    
   <reg protect="rw" name="rx_control">
     <bits access="rw" name="enable_ctrl" pos="0" rst="0">
       <comment>Channel Enable, write one in this bit enable the channel.
       <br />When the channel is enabled, for a peripheral to memory transfer
       the DMA wait request from peripheral to start transfer. </comment>
     </bits>
 
     <bits access="rw" name="disable_ctrl" pos="1" rst="0">
       <comment>Channel Disable, write one in this bit disable the channel.
       <br />When writing one in this bit, the current AHB transfer and current
       APB transfer (if one in progress) is completed and the channel is then
       disabled.</comment>
     </bits>

     <bits access="rw" name="burst_size" pos="16" rst="1">
      <comment>Burst size on AHB bus 
        <br />0 = Single access 
        <br />1 = burst Access (4 words). 
      </comment>
    </bits>

    <bits access="rw" name="fifo_mode" pos="17" rst="1">
      <comment>Set FIFO mode . <br />0 = no fifo mode, transfer stop when the
      current transfer counter reaches zero. Channel must be re-enabled for
      future transfer. <br />1 = Fifo mode, when the current AHB address
      counter reaches the end address of the FIFO. AHB address counter is
      reloaded with the initial value. In FIFO mode channel is not disabled at
      the end of the transfer.</comment>
    </bits>
   </reg>

   <reg protect="r" name="rx_status">
     <bits access="r" name="enable_ctrl" pos="0" rst="0">
       <options>
         <option name="DISABLE" value="0" />
 
         <option name="ENABLE" value="1" />
 
         <default />
       </options>
 
       <comment>In no fifo mode the channel is automatically disabled at the
       end of the transfer. In fifo mode the channel is disabled only when
       disabled write is performed in the control register. </comment>
     </bits>
 
     <bits access="r" name="fifo_empty" pos="1" rst="1">
       <comment>When 1 the fifo is empty </comment>
     </bits>
     
     <bits access="r" name="cause_nb_htc" pos="2" rst="0">
      <comment>Cause interrupt half tc  when fifo mode is enable.</comment>
    </bits>

     <bits access="r" name="nb_htc" pos="3" rst="0">
       <comment> Half of TC interrupt when fifo mode is enable status bit. </comment>
     </bits>

     <bits access="r" name="cause_itc" pos="4" rst="0">
      <comment>Cause interrupt End of TC.</comment>
    </bits>

    <bits access="r" name="cause_ief" pos="5" rst="0">
      <comment>Cause interrupt End of FIFO. </comment>
    </bits>

    <bits access="r" name="cause_ihtc" pos="6" rst="0">
      <comment>Cause interrupt Half Transfer Count (This interruption is
      generated when the IFC has transferred 96 word).</comment>
    </bits>
 
     <bits access="r" name="itc" pos="7" rst="0">
       <comment>End of TC interrupt status bit. </comment>
     </bits>

    <bits access="r" name="ief" pos="8" rst="0">
      <comment>End of FIFO interrupt status bit. </comment>
    </bits>

    <bits access="r" name="ihtc" pos="9" rst="0">
      <comment>Half TC interrupt status bit.</comment>
    </bits>

     <bits access="r" name="cur_tc" pos="31:10" rst="0x3fffff">
       <comment>Current value of transfer counter.</comment>
     </bits>
   </reg>
 
   <reg protect="rw" name="rx_start_addr">
     <bits access="rw" name="start_addr" pos="31:2" rst="0x3FFFFFFF" display="hex">
       <comment>AHB Start Address.</comment>
     </bits>
   </reg>

   <reg protect="rw" name="rx_end_addr">
     <bits access="rw" name="end_addr"   pos="31:2" rst="0x3FFFFFFF" display="hex">
      <comment>The last page address of the FIFO, it is the first address not
      used for the FIFO. The start address of the FIFO is specified by the
      register AHB_ADDR and the last page address of the FIFO is specified by
      this field. The size of the fifo (END_ADDR - START_ADDR) must be a
      multiple of burst of 4x32-bits. </comment>
    </bits>
  </reg>


   <reg protect="rw" name="rx_tc_reg">
     <bits access="r" name="tc_reg" pos="21:0" rst="0x3FFFFF" display="hex">
     <comment>Transfer Count <br/>In no FIFO mode, this bit indicated
      the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per
      transfer. <br/>In FIFO mode this field define, after how many
      transfer an interrupt in generated.</comment>
     </bits>
   </reg>

    <reg protect="rw" name="rx_int_mask">
    <bits access="rw" name="end_tc" pos="0" rst="0">
      <comment>End TC Mask interrupt. When one this interrupt is
      enabled.</comment>
    </bits>

    <bits access="rw" name="end_fifo" pos="1" rst="0">
      <comment>END FIFO Mask interrupt. When one this interrupt is enabled.
      </comment>
    </bits>

    <bits access="rw" name="half_tc" pos="2" rst="0">
      <comment>Half TC Mask interrupt. When one this interrupt is
      enabled</comment>
    </bits>

    <bits access="rw" name="nb_half_tc" pos="3" rst="0">
      <comment>NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is
      enabled</comment>
    </bits>


</reg>

  <reg protect="rw" name="rx_int_clear">
    <bits access="c" name="end_tc" pos="0" rst="0">
      <comment>Write one to clear end of TC interrupt.</comment>
    </bits>

    <bits access="c" name="end_fifo" pos="1" rst="0">
      <comment>Write one to clear end of FIFO interrupt.</comment>
    </bits>

    <bits access="c" name="half_fifo" pos="2" rst="0">
      <comment>Write one to clear end of Half TC interrupt.</comment>
    </bits>

    <bits access="c" name="nb_half_fifo" pos="3" rst="0">
      <comment>Write one to clear end of Half TC (the real one) interrupt.</comment>
    </bits>
</reg>

   <reg protect="r" name="rx_cur_ahb_addr">
     <bits access="r" name="cur_ahb_addr" pos="31:0" rst="0x3ffe000">
       <comment>Current AHB address value.
       </comment>
     </bits>
   </reg>

   
   <reg protect="rw" name="tx_control">
     <bits access="rw" name="enable_ctrl" pos="0" rst="0">
       <comment>Channel Enable, write one in this bit enable the channel.
       <br />When the channel is enabled, for a peripheral to memory transfer
       the DMA wait request from peripheral to start transfer. </comment>
     </bits>
 
     <bits access="rw" name="disable_ctrl" pos="1" rst="0">
       <comment>Channel Disable, write one in this bit disable the channel.
       <br />When writing one in this bit, the current AHB transfer and current
       APB transfer (if one in progress) is completed and the channel is then
       disabled.</comment>
     </bits>

     <bits access="rw" name="burst_size" pos="16" rst="1">
      <comment>Burst size on AHB bus 
        <br />0 = Single access 
        <br />1 = burst Access (4 words). 
      </comment>
    </bits>

    <bits access="rw" name="fifo_mode" pos="17" rst="1">
      <comment>Set FIFO mode . <br />0 = no fifo mode, transfer stop when the
      current transfer counter reaches zero. Channel must be re-enabled for
      future transfer. <br />1 = Fifo mode, when the current AHB address
      counter reaches the end address of the FIFO. AHB address counter is
      reloaded with the initial value. In FIFO mode channel is not disabled at
      the end of the transfer.</comment>
    </bits>
   </reg>

   <reg protect="r" name="tx_status">
     <bits access="r" name="enable_ctrl" pos="0" rst="0">
       <options>
         <option name="DISABLE" value="0" />
 
         <option name="ENABLE" value="1" />
 
         <default />
       </options>
 
       <comment>In no fifo mode the channel is automatically disabled at the
       end of the transfer. In fifo mode the channel is disabled only when
       disabled write is performed in the control register. </comment>
     </bits>
 
     <bits access="r" name="fifo_empty" pos="1" rst="1">
       <comment>When 1 the fifo is empty </comment>
     </bits>
     
     <bits access="r" name="cause_nb_htc" pos="2" rst="0">
      <comment>Cause interrupt half tc  when fifo mode is enable.</comment>
    </bits>

     <bits access="r" name="nb_htc" pos="3" rst="0">
       <comment> Half of TC interrupt when fifo mode is enable status bit. </comment>
     </bits>

     <bits access="r" name="cause_itc" pos="4" rst="0">
      <comment>Cause interrupt End of TC.</comment>
    </bits>

    <bits access="r" name="cause_ief" pos="5" rst="0">
      <comment>Cause interrupt End of FIFO. </comment>
    </bits>

    <bits access="r" name="cause_ihtc" pos="6" rst="0">
      <comment>Cause interrupt Half Transfer Count (This interruption is
      generated when the IFC has transferred 96 word).</comment>
    </bits>
 
     <bits access="r" name="itc" pos="7" rst="0">
       <comment>End of TC interrupt status bit. </comment>
     </bits>

    <bits access="r" name="ief" pos="8" rst="0">
      <comment>End of FIFO interrupt status bit. </comment>
    </bits>

    <bits access="r" name="ihtc" pos="9" rst="0">
      <comment>Half TC interrupt status bit.</comment>
    </bits>

     <bits access="r" name="cur_tc" pos="31:10" rst="0x3fffff">
       <comment>Current value of transfer counter.</comment>
     </bits>
   </reg>
 
   <reg protect="rw" name="tx_start_addr">
     <bits access="rw" name="start_addr" pos="31:2" rst="0x3FFFFFFF" display="hex">
       <comment>AHB Start Address.</comment>
     </bits>
   </reg>

   <reg protect="rw" name="tx_end_addr">
     <bits access="rw" name="end_addr"   pos="31:2" rst="0x3FFFFFFF" display="hex">
      <comment>The last page address of the FIFO, it is the first address not
      used for the FIFO. The start address of the FIFO is specified by the
      register AHB_ADDR and the last page address of the FIFO is specified by
      this field. The size of the fifo (END_ADDR - START_ADDR) must be a
      multiple of burst of 4x32-bits. </comment>
    </bits>
  </reg>


   <reg protect="rw" name="tx_tc_reg">
     <bits access="r" name="tc_reg" pos="21:0" rst="0x3FFFFF" display="hex">
     <comment>Transfer Count <br/>In no FIFO mode, this bit indicated
      the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per
      transfer. <br/>In FIFO mode this field define, after how many
      transfer an interrupt in generated.</comment>
     </bits>
   </reg>

    <reg protect="rw" name="tx_int_mask">
    <bits access="rw" name="end_tc" pos="0" rst="0">
      <comment>End TC Mask interrupt. When one this interrupt is
      enabled.</comment>
    </bits>

    <bits access="rw" name="end_fifo" pos="1" rst="0">
      <comment>END FIFO Mask interrupt. When one this interrupt is enabled.
      </comment>
    </bits>

    <bits access="rw" name="half_tc" pos="2" rst="0">
      <comment>Half TC Mask interrupt. When one this interrupt is
      enabled</comment>
    </bits>

    <bits access="rw" name="nb_half_tc" pos="3" rst="0">
      <comment>NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is
      enabled</comment>
    </bits>


</reg>

  <reg protect="rw" name="tx_int_clear">
    <bits access="c" name="end_tc" pos="0" rst="0">
      <comment>Write one to clear end of TC interrupt.</comment>
    </bits>

    <bits access="c" name="end_fifo" pos="1" rst="0">
      <comment>Write one to clear end of FIFO interrupt.</comment>
    </bits>

    <bits access="c" name="half_fifo" pos="2" rst="0">
      <comment>Write one to clear end of Half TC interrupt.</comment>
    </bits>

    <bits access="c" name="nb_half_fifo" pos="3" rst="0">
      <comment>Write one to clear end of Half TC (the real one) interrupt.</comment>
    </bits>
</reg>

   <reg protect="r" name="tx_cur_ahb_addr">
     <bits access="r" name="cur_ahb_addr" pos="31:0" rst="0x3ffe000">
       <comment>Current AHB address value.
       </comment>
     </bits>
   </reg>

   
   <reg protect="rw" name="rfif_ctrl">
     <bits access="rw" name="dump_en" pos="0" rst="0x0" display="hex">
       <comment> dump the 'data from dfe to nb core' to mem</comment>
     </bits>
     
     <bits access="rw" name="dump_mode" pos="1" rst="0x0" display="hex">
         <comment> when the bit is 1, dump only when nb-core comes an pulse ,capture the set data numbers ,then stop
                   when the bit is 0, dump all bit normal dump mode </comment>
     </bits>

     <bits access="rw" name="dump_downsample" pos="2" rst="0x0" display="hex">
         <comment> when the bit is 1, downsample enable 
                   when the bit is 0, disable </comment>
     </bits>
 
     <bits access="rw" name="feed_dl" pos="4" rst="0x0" display="hex">
       <comment> get data from mem, simu the data format from dfe to nb core</comment>
     </bits>

     <bits access="rw" name="feed_ul" pos="5" rst="0x0" display="hex">
       <comment> get data from mem, simu the data format from nbcore to dfe</comment>
     </bits>

     <bits access="rw" name="feed_speed_div" pos="23:8" rst="0x20" display="hex">
         <comment> feed data rate  1.92MHz=0x20 192KHz=0x140, 96KHz=0x280, 38.4KHz=0x640, 32KHz=0x780  </comment>
     </bits>

     <bits access="r" name="feed_fifo_empty" pos="24" rst="0x1" display="hex">
       <comment> fifo empty siganl </comment>
     </bits>

     <bits access="r" name="dump_fifo_empty" pos="25" rst="0x1" display="hex">
       <comment> fifo empty signal</comment>
    </bits>

      <bits access="rw" name="feed_fifo_clr" pos="26" rst="0x0" display="hex">
        <comment> clr feed fifo point 
                </comment>
     </bits>

     <bits access="rw" name="dump_fifo_clr" pos="27" rst="0x0" display="hex">
         <comment> clr dump fifo point 
                    </comment>
     </bits>

     <bits access="rw" name="nb_debug" pos="31" rst="0x0" display="hex">
         <comment> when the bit is 1, nb use the rf_dma 
                   when the bit is 0, 2g use the rf_dma </comment>
     </bits>
   </reg>

   <reg protect="rw" name="dfe_filter_ctrl">
     <bits access="rw" name="bw_sel" pos="3:0" rst="0x0" display="hex">
       <comment> the bandwidth select signal </comment>
     </bits>

     <bits access="rw" name="filter_bypass" pos="4" rst="0x1" display="hex">
       <comment> bypass the filter function to the data </comment>
     </bits>

     <bits access="rw" name="iq_mismatch" pos="8" rst="0x0" display="hex">
         <comment> combine a unused data with I0 used as I0Q0,  combine Q0I1 , used as I1Q1.
                   next goes on. the last Qn will be discarded.</comment>
     </bits>

     <bits access="rw" name="rbdp_delay_sel" pos="15:12" rst="0xa" display="hex">
         <comment>  set the delay of fclk_fordata to delay the rbdp_tx data</comment>
     </bits>

     <bits access="rw" name="fclk_delay_sel" pos="19:16" rst="0x2" display="hex">
         <comment>  set the delay of fclk external, only for the clk_phy gen fclk </comment>
     </bits>

     <bits access="rw" name="fclk_source_sel" pos="20" rst="0x0" display="hex">
         <comment>  1'b0 the source is fclk gen by clk_phy, 1'b1 the source is mclk </comment>
     </bits>
 
 </reg>

   <hole size="192"/>
  
   <reg protect="rw" name="nb_if_irsr">
     <bits access="rw" name="dump_ovfl" pos="0" rst="0x0" display="hex">
       <comment> dump_ovfl irq </comment>
     </bits>

     <bits access="rw" name="dump_udfl" pos="1" rst="0x0" display="hex">
       <comment> dump_udfl irq </comment>
     </bits>

     <bits access="rw" name="feed_ovfl" pos="2" rst="0x0" display="hex">
       <comment> feed_ovfl irq </comment>
     </bits>

     <bits access="rw" name="feed_udfl" pos="3" rst="0x0" display="hex">
       <comment> feed_udfl irq </comment>
     </bits>
 
     <bits access="rw" name="dump_ovfl_real" pos="4" rst="0x0" display="hex">
       <comment> dump_ovfl  when  ifc is still working irq </comment>
     </bits>

     <bits access="rw" name="dump_udfl_real" pos="5" rst="0x0" display="hex">
       <comment> dump_udfl  when  ifc is still working irq </comment>
     </bits>
 </reg>

   <reg protect="rw" name="nb_if_imr">
     <bits access="rw" name="dump_ovfl" pos="0" rst="0x0" display="hex">
       <comment> dump_ovfl mask </comment>
     </bits>

     <bits access="rw" name="dump_udfl" pos="1" rst="0x0" display="hex">
       <comment> dump_udfl mask </comment>
     </bits>

     <bits access="rw" name="feed_ovfl" pos="2" rst="0x0" display="hex">
       <comment> feed_ovfl mask </comment>
     </bits>

     <bits access="rw" name="feed_udfl" pos="3" rst="0x0" display="hex">
       <comment> feed_udfl mask </comment>
     </bits>

     <bits access="rw" name="dump_ovfl_real" pos="4" rst="0x0" display="hex">
       <comment> dump_ovfl  when  ifc is still working  mask </comment>
     </bits>

     <bits access="rw" name="dump_udfl_real" pos="5" rst="0x0" display="hex">
       <comment> dump_udfl  when  ifc is still working  mask </comment>
     </bits>
 </reg>

   <reg protect="rw" name="nb_if_isr">
     <bits access="rw" name="dump_ovfl" pos="0" rst="0x0" display="hex">
       <comment> dump_ovfl  before mask irq source </comment>
     </bits>

     <bits access="rw" name="dump_udfl" pos="1" rst="0x0" display="hex">
       <comment> dump_udfl  before mask irq source </comment>
     </bits>

     <bits access="rw" name="feed_ovfl" pos="2" rst="0x0" display="hex">
       <comment> feed_ovfl  before mask irq source </comment>
     </bits>

     <bits access="rw" name="feed_udfl" pos="3" rst="0x0" display="hex">
       <comment> feed_udfl  before mask irq source </comment>
     </bits>

     <bits access="rw" name="dump_ovfl_real" pos="4" rst="0x0" display="hex">
       <comment> dump_ovfl  when  ifc is still working irq  source </comment>
     </bits>

     <bits access="rw" name="dump_udfl_real" pos="5" rst="0x0" display="hex">
       <comment> dump_udfl  when  ifc is still working irq source </comment>
     </bits>
 </reg>

   <reg protect="rw" name="nb_if_icr">
     <bits access="rw" name="dump_ovfl" pos="0" rst="0x0" display="hex">
       <comment> dump_ovfl clr irq </comment>
     </bits>

     <bits access="rw" name="dump_udfl" pos="1" rst="0x0" display="hex">
       <comment> dump_udfl clr irq </comment>
     </bits>

     <bits access="rw" name="feed_ovfl" pos="2" rst="0x0" display="hex">
       <comment> feed_ovfl clr irq </comment>
     </bits>

     <bits access="rw" name="feed_udfl" pos="3" rst="0x0" display="hex">
       <comment> feed_udfl clr irq </comment>
     </bits>

     <bits access="rw" name="dump_ovfl_real" pos="4" rst="0x0" display="hex">
       <comment> dump_ovfl  when  ifc is still working clr irq </comment>
     </bits>

     <bits access="rw" name="dump_udfl_real" pos="5" rst="0x0" display="hex">
       <comment> dump_udfl  when  ifc is still working clr irq </comment>
     </bits>
 </reg>

</module>
</archive>

<archive relative="rf_interface.xml">
  <module name="rf_interface" category="RF_Dig">
    <reg protect="r" name="reg_000_bit_ro">
      <bits access="r" name="reg_000_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[0]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_002_bit_ro">
      <bits access="r" name="reg_002_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[1]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_004_bit_ro">
      <bits access="r" name="reg_004_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[2]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_006_bit_ro">
      <bits access="r" name="reg_006_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[3]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_008_bit_ro">
      <bits access="r" name="reg_008_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[8]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_00a_bit_ro">
      <bits access="r" name="reg_00a_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[9]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_00c_bit_ro">
      <bits access="r" name="reg_00c_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[10]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_00e_bit_ro">
      <bits access="r" name="reg_00e_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[11]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_010_bit_ro">
      <bits access="r" name="reg_010_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[12]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_012_bit_ro">
      <bits access="r" name="reg_012_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[13]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_014_bit_ro">
      <bits access="r" name="reg_014_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[14]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_016_bit_ro">
      <bits access="r" name="reg_016_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[15]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_018_bit_ro">
      <bits access="r" name="reg_018_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[16]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_01a_bit_ro">
      <bits access="r" name="reg_01a_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[17]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_01c_bit_ro">
      <bits access="r" name="reg_01c_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[18]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_01e_bit_ro">
      <bits access="r" name="reg_01e_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[19]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_020_bit_ro">
      <bits access="r" name="reg_020_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[20]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_022_bit_ro">
      <bits access="r" name="reg_022_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[21]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_024_bit_ro">
      <bits access="r" name="reg_024_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[22]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_026_bit_ro">
      <bits access="r" name="reg_026_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI. write this register will generate irq[23]
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_028_bit_ro">
      <bits access="r" name="reg_028_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_02a_bit_ro">
      <bits access="r" name="reg_02a_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_02c_bit_ro">
      <bits access="r" name="reg_02c_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_02e_bit_ro">
      <bits access="r" name="reg_02e_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <hole size="768"/>
    <reg protect="r" name="reg_sys_ctrl_bit_ro">
      <bits access="r" name="reg_sys_ctrl_bit" pos="15:0" rst="16641">
        <comment>
          reset register. read only by RISCV, write and read by SPI. bit [0] is used to reset SPI register logics, other bits are no use
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_page_bit_ro">
      <bits access="r" name="reg_page_bit" pos="15:0" rst="6">
        <comment>
          page read register. read only by RISCV and SPI. page is wrote by SPI at address 0x7fff
        </comment>
      </bits>
    </reg>
    <hole size="448"/>
    <reg protect="r" name="reg_100_bit_ro">
      <bits access="r" name="reg_100_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_102_bit_ro">
      <bits access="r" name="reg_102_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_104_bit_ro">
      <bits access="r" name="reg_104_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_106_bit_ro">
      <bits access="r" name="reg_106_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_108_bit_ro">
      <bits access="r" name="reg_108_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_10a_bit_ro">
      <bits access="r" name="reg_10a_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_10c_bit_ro">
      <bits access="r" name="reg_10c_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_10e_bit_ro">
      <bits access="r" name="reg_10e_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_110_bit_ro">
      <bits access="r" name="reg_110_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_112_bit_ro">
      <bits access="r" name="reg_112_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_114_bit_ro">
      <bits access="r" name="reg_114_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_116_bit_ro">
      <bits access="r" name="reg_116_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_118_bit_ro">
      <bits access="r" name="reg_118_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_11a_bit_ro">
      <bits access="r" name="reg_11a_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_11c_bit_ro">
      <bits access="r" name="reg_11c_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_11e_bit_ro">
      <bits access="r" name="reg_11e_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_120_bit_ro">
      <bits access="r" name="reg_120_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_122_bit_ro">
      <bits access="r" name="reg_122_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_124_bit_ro">
      <bits access="r" name="reg_124_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_126_bit_ro">
      <bits access="r" name="reg_126_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_128_bit_ro">
      <bits access="r" name="reg_128_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_12a_bit_ro">
      <bits access="r" name="reg_12a_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_12c_bit_ro">
      <bits access="r" name="reg_12c_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_12e_bit_ro">
      <bits access="r" name="reg_12e_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_130_bit_ro">
      <bits access="r" name="reg_130_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_132_bit_ro">
      <bits access="r" name="reg_132_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_134_bit_ro">
      <bits access="r" name="reg_134_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_136_bit_ro">
      <bits access="r" name="reg_136_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_138_bit_ro">
      <bits access="r" name="reg_138_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_13a_bit_ro">
      <bits access="r" name="reg_13a_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_13c_bit_ro">
      <bits access="r" name="reg_13c_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_13e_bit_ro">
      <bits access="r" name="reg_13e_bit" pos="15:0" rst="0">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_140_bit_ro">
      <bits access="r" name="reg_140_bit" pos="15:0" rst="32768">
        <comment>
          data register. read only by RISCV, write and read by SPI.
        </comment>
      </bits>
    </reg>
    <hole size="992"/>
    <reg protect="rw" name="int_clear00">
      <bits access="rw" name="int_ctrl_bit_0" pos="15:0" rst="0">
        <comment>
          irq clear bit [15:0], [7:4] is no use
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="int_clear111">
      <bits access="rw" name="int_ctrl_bit_1" pos="15:0" rst="0">
        <comment>
          irq clear bit [31:16], [31:24] is no use
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="int2tmuc0">
      <bits access="r" name="irq0" pos="15:0" rst="0">
        <comment>
          read only irq[15:0].
[0]:   interrupt 0 of spi write, which assert high when spi address is 15'h0000 and page address is 5'b00110
[1]:   interrupt 1 of spi write, which assert high when spi address is 15'h0004 and page address is 5'b00110
[2]:   interrupt 2 of spi write, which assert high when spi address is 15'h0008 and page address is 5'b00110
[3]:   interrupt 3 of spi write, which assert high when spi address is 15'h000c and page address is 5'b00110
[4]:   interrupt of timer 0
[5]:   interrupt of timer 1
[6]:   interrupt of timer 2
[7]:   interrupt of DFE
[8]:   interrupt 4 of spi write, which assert high when spi address is 15'h0010 and page address is 5'b00110
[9]:   interrupt 5 of spi write, which assert high when spi address is 15'h0014 and page address is 5'b00110
[10]: interrupt 6 of spi write, which assert high when spi address is 15'h0018 and page address is 5'b00110
[11]: interrupt 7 of spi write, which assert high when spi address is 15'h001c and page address is 5'b00110
[12]: interrupt 8 of spi write, which assert high when spi address is 15'h0020 and page address is 5'b00110
[13]: interrupt 9 of spi write, which assert high when spi address is 15'h0024 and page address is 5'b00110
[14]: interrupt 10 of spi write, which assert high when spi address is 15'h0028 and page address is 5'b00110
[15]: interrupt 11 of spi write, which assert high when spi address is 15'h002c and page address is 5'b00110
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="int2tmuc1">
      <bits access="r" name="irq1" pos="15:0" rst="0">
        <comment>
          read only irq[31:16].
[0]:   interrupt 12 of spi write, which assert high when spi address is 15'h0030 and page address is 5'b00110
[1]:   interrupt 13 of spi write, which assert high when spi address is 15'h0034 and page address is 5'b00110
[2]:   interrupt 14 of spi write, which assert high when spi address is 15'h0038 and page address is 5'b00110
[3]:   interrupt 15 of spi write, which assert high when spi address is 15'h003c and page address is 5'b00110
[4]:   interrupt 16 of spi write, which assert high when spi address is 15'h0040 and page address is 5'b00110
[5]:   interrupt 17 of spi write, which assert high when spi address is 15'h0044 and page address is 5'b00110
[6]:   interrupt 18 of spi write, which assert high when spi address is 15'h0048 and page address is 5'b00110
[7]:   interrupt 19 of spi write, which assert high when spi address is 15'h004c and page address is 5'b00110
[8]:   interrupt of mailbox 0
[9]:   interrupt of mailbox 1
[10]: interrupt of watch dog
[11]: interrupt of uart
[12]: interrupt which assert by signal dfe_rx_enable
[13]: interrupt which assert by signal gsm_digrf_tx_strobe
[14]: interrupt which assert by signal npll_pu_in
[15]: interrupt which assert by signal gpll_pu_in
        </comment>
      </bits>
    </reg>
    <hole size="1440"/>
    <reg protect="rw" name="xcvsdm_reg0">
      <bits access="rw" name="freq_xcvsdm0" pos="15:0" rst="0">
        <comment>
          bit [15:0] of RFPLL SDM frequency for GSM RX and NB RX/TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="xcvsdm_reg1">
      <bits access="rw" name="freq_xcvsdm1" pos="15:0" rst="0">
        <comment>
          bit [31:16] of RFPLL SDM frequency for GSM RX and NB RX/TX
        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="xcvsdm_reg2">
      <bits access="r" name="xcvsdm_reg2_reserved_0" pos="15:3" rst="0">
      </bits>
      <bits access="rw" name="freq_xcvsdm2" pos="2:0" rst="0">
        <comment>
          bit [34:32] of RFPLL SDM frequency for GSM RX and NB RX/TX
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_freq_enable">
      <bits access="r" name="reg_freq_enable_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_enable" pos="0" rst="0">
        <comment>
          load SDM frequency of all PLLs(RFPLL, GPLL, NPLL) to RTL at the same time, write 0 before assert it
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="xcvsdm_reg3">
      <bits access="r" name="xcvsdm_reg3_reserved_0" pos="15:5" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_bypass_xcvsdm" pos="4" rst="0">
        <comment>
          bypass freq_enable, i.e., SDM frequency of RFPLL takes effect immidiately when it is loaded into regsiter
        </comment>
      </bits>
      <bits access="rw" name="dither_bypass_xcvsdm" pos="3" rst="0">
        <comment>
          sdm rfpll dither_bypass_xcvsdm
        </comment>
      </bits>
      <bits access="rw" name="dll_mode_xcvsdm" pos="2:0" rst="1">
        <comment>
          dividing ratio of RFPLL feedback clock to generate 26MHz clock used by GSM TX logic of DFE:
0b000: 182M divided by 7
0b001: 208M divided by 8
0b010: 234M divided by 9
0b011: 260M divided by 10
0b100: 26M with no division
0b101: 52M divided by 2
others: 208M divided by 8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="xcvsdm_reg4">
      <bits access="r" name="xcvsdm_reg4_reserved_0" pos="15:6" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="tx_rx_sel_xcvsdm" pos="5" rst="0">
        <comment>
          select for TX using RFPLL SDM:
0b0: GSM RX or NB RX or NB TX without PolarIQ. SDM frequency is from registers that are xcvsdm_reg2/1/0
0b1: GSM TX or NB TX with PolarIQ. SDM frequency is from DFE GSM former and PolarIQ split
        </comment>
      </bits>
      <bits access="rw" name="resetn_xcvsdm" pos="4" rst="0">
        <comment>
          reset of RFPLL SDM, active low
        </comment>
      </bits>
      <bits access="rw" name="int_dec_sel_xcvsdm" pos="3:1" rst="2">
        <comment>
          decimal bit width selection of RFPLL SDM output. It should be fixed to 3'h2 in 8809nez.
0b000: int divide
0b001: 1 bit decimal divide
0b010: 2 bits decimal divide
0b011: 3 bit decimal divide
others: bypass SDM
        </comment>
      </bits>
      <bits access="rw" name="fbc_inv_xcvsdm" pos="0" rst="0">
        <comment>
          feedback clock inverse used by RFPLL SDM
0b0: no inverse
0b1: inverse
        </comment>
      </bits>
    </reg>
    <hole size="192"/>
    <reg protect="rw" name="bbpll1_reg1">
      <bits access="r" name="bbpll1_reg1_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="npll_cp_rbit" pos="13:11" rst="4">
        <comment>
          NPLL pll_cpbias_rbit
        </comment>
      </bits>
      <bits access="rw" name="npll_cp_bit" pos="10:7" rst="1">
        <comment>
          NPLL pll_cpbias_ibit
        </comment>
      </bits>
      <bits access="rw" name="npll_cpc2_bit" pos="6:4" rst="4">
        <comment>
          NPLL pll_cpc2_bit
        </comment>
      </bits>
      <bits access="rw" name="npll_digreg_range" pos="3:0" rst="8">
        <comment>
          NPLL digreg_range
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll1_reg2">
      <bits access="r" name="bbpll1_reg2_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="npll_band_sel" pos="13:12" rst="0">
        <comment>
          NPLL band_sel
        </comment>
      </bits>
      <bits access="rw" name="npll_testsig_sel" pos="11:10" rst="0">
        <comment>
          NPLL testsig_sel
        </comment>
      </bits>
      <bits access="rw" name="npll_pcon_mode" pos="9" rst="0">
        <comment>
          NPLL pcom_mode
        </comment>
      </bits>
      <bits access="rw" name="npll_refmulti2_en" pos="8" rst="1">
        <comment>
          NPLL refmulti2_en
        </comment>
      </bits>
      <bits access="rw" name="npll_vco_high_test" pos="7" rst="0">
        <comment>
          NPLL vco_high_test
        </comment>
      </bits>
      <bits access="rw" name="npll_vco_low_test" pos="6" rst="0">
        <comment>
          NPLL vco_low_test
        </comment>
      </bits>
      <bits access="rw" name="npll_int_mode" pos="5" rst="0">
        <comment>
          NPLL int_mode
        </comment>
      </bits>
      <bits access="rw" name="npll_sdm_clk_test_en" pos="4" rst="0">
        <comment>
          NPLL sdm_clk_test_en
        </comment>
      </bits>
      <bits access="rw" name="pu_npll_dr1" pos="3" rst="0">
        <comment>
          direct conrol of analog pu_npll
        </comment>
      </bits>
      <bits access="rw" name="pu_npll_reg1" pos="2" rst="0">
        <comment>
          value of analog pu_npll. It takes affect when pu_npll_dr1 is 0b1
        </comment>
      </bits>
      <bits access="rw" name="pu_npll_dr" pos="1" rst="0">
        <comment>
          direct conrol of baseband pu_npll
        </comment>
      </bits>
      <bits access="rw" name="pu_npll_reg" pos="0" rst="0">
        <comment>
          value of baseband pu_npll. It takes affect when pu_npll_dr is 0b1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll1_reg3">
      <bits access="r" name="bbpll1_reg3_reserved_0" pos="15:11" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="npll_cpr2_bit" pos="10:8" rst="4">
        <comment>
          NPLL pll_cpr2_bit
        </comment>
      </bits>
      <bits access="rw" name="npll_reser_reg" pos="7:0" rst="1">
        <comment>
          NPLL pll_reserved_reg
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll1_reg5">
      <bits access="rw" name="npll_sdm_freq1" pos="15:0" rst="24576">
        <comment>
          bit [31:16] of NPLL SDM frequency
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll1_reg6">
      <bits access="rw" name="npll_sdm_freq0" pos="15:0" rst="0">
        <comment>
          bit [15:0] of NPLL SDM frequency
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll1_reg7">
      <bits access="r" name="bbpll1_reg7_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="npll_freq_bypass" pos="7" rst="0">
        <comment>
          bypass freq_enable, i.e., SDM frequency of NPLL takes effect immidiately when it is loaded into regsiter
0b0: no bypass
0b1: bypass
        </comment>
      </bits>
      <bits access="rw" name="npll_int_dec_sel" pos="6:4" rst="3">
        <comment>
          decimal bit width selection of NPLL SDM output. It should be fixed to 3'b011 in 8809nez.
0b000: int divide
0b001: 1 bit decimal divide
0b010: 2 bits decimal divide
0b011: 3 bit decimal divide
others: bypass SDM
        </comment>
      </bits>
      <bits access="rw" name="npll_dither_bypass" pos="3" rst="1">
        <comment>
          dither bypass of NPLL SDM
0b0: no bypass
0b1: bypass
        </comment>
      </bits>
      <bits access="rw" name="npll_fbc_inv" pos="2" rst="0">
        <comment>
          feedback clock inverse used by NPLL SDM
0b0: no inverse
0b1: inverse
        </comment>
      </bits>
      <bits access="rw" name="npll_sdm_resetn_dr" pos="1" rst="0">
        <comment>
          direct conrol of NPLL SDM reset
        </comment>
      </bits>
      <bits access="rw" name="npll_sdm_resetn_reg" pos="0" rst="0">
        <comment>
          reset of NPLL SDM, active low. It takes affect when npll_sdm_resetn_dr is 0b1
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="bbpll1_rega">
      <bits access="rw" name="npll_sdm_reset_time_sel" pos="15:14" rst="1">
        <comment>
          the time to release reset of NPLL SDM after pu_npll assert.
0b00: 10us
0b01: 12us
0b10: 15us
0b11: 40us
        </comment>
      </bits>
      <bits access="rw" name="npll_sdmclk_sel_time_sel" pos="13:12" rst="1">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="r" name="bbpll1_rega_reserved_0" pos="11:5" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_adc_sel_reg" pos="4" rst="1">
        <comment>
          select of 30.72MHz clock of NPLL to ADC
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_adc_en_reg" pos="3" rst="1">
        <comment>
          enable of 30.72MHz clock of NPLL to ADC
        </comment>
      </bits>
      <bits access="rw" name="npll_clk2dig_en_reg" pos="2" rst="1">
        <comment>
          enable of 61.44MHz clock of NPLL to DFE
        </comment>
      </bits>
      <bits access="rw" name="npll_clk2dig_sel_reg" pos="1" rst="1">
        <comment>
          select of 61.44MHz clock of NPLL to DFE
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_gen_en_reg" pos="0" rst="1">
        <comment>
          enable pu_npll from baseband
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="bbpll1_regb">
      <bits access="r" name="npll_pu" pos="15" rst="0">
        <comment>
          NPLL pu status
        </comment>
      </bits>
      <bits access="r" name="npll_lock" pos="14" rst="0">
        <comment>
          NPLL lock status
        </comment>
      </bits>
      <bits access="r" name="npll_sdm_resetn" pos="13" rst="0">
        <comment>
          NPLL SDM reset status
        </comment>
      </bits>
      <bits access="r" name="npll_sdm_clk_sel" pos="12" rst="0">
        <comment>
          NPLL sdm_clk_sel status
        </comment>
      </bits>
      <bits access="r" name="npll_clk_ready" pos="11" rst="0">
        <comment>
          NPLL clock status
        </comment>
      </bits>
      <bits access="r" name="npll_lock_steady" pos="10" rst="0">
        <comment>
          NPLL locked status
        </comment>
      </bits>
      <bits access="r" name="bbpll1_regb_reserved_0" pos="9:0" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll1_regd">
      <bits access="r" name="bbpll1_regd_reserved_0" pos="15:6" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="resetn_npll" pos="5" rst="1">
        <comment>
          software reset of logics to control NPLL pu and pd, active low
        </comment>
      </bits>
      <bits access="rw" name="npll_clkout_en_counter_sel" pos="4:2" rst="2">
        <comment>
          the time to open NPLL clocks after pu_npll assert.
0b000: 10us+50us+1us
0b000: 10us+60us+1us
0b000: 10us+70us+1us
0b000: 10us+80us+1us
0b000: 10us+90us+1us
0b000: 10us+100us+1us
        </comment>
      </bits>
      <bits access="rw" name="npll_lock_counter_sel" pos="1:0" rst="1">
        <comment>
          NPLL locked time.
0b00: 1us
0b01: 2us
0b10: 3us
0b11: 4us
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll1_regf">
      <bits access="r" name="bbpll1_regf_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="npll_clk2dig_en_drreg" pos="11" rst="0">
        <comment>
          direct value of npll_clk2dig_en
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_adc_en_drreg" pos="10" rst="0">
        <comment>
          direct value of npll_clk_adc_en
        </comment>
      </bits>
      <bits access="rw" name="npll_clk2dig_sel_drreg" pos="9" rst="0">
        <comment>
          direct value of npll_clk2dig_sel
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_adc_sel_drreg" pos="8" rst="0">
        <comment>
          direct value of npll_clk_adc_sel
        </comment>
      </bits>
      <bits access="rw" name="npll_clk2dig_en_dr" pos="7" rst="0">
        <comment>
          direct control of npll_clk2dig_en
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_adc_en_dr" pos="6" rst="0">
        <comment>
          direct control of npll_clk_adc_en
        </comment>
      </bits>
      <bits access="rw" name="npll_clk2dig_sel_dr" pos="5" rst="0">
        <comment>
          direct control of npll_clk2dig_sel
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_adc_sel_dr" pos="4" rst="0">
        <comment>
          direct control of npll_clk_adc_sel
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_rstb_reg" pos="3" rst="0">
        <comment>
          direct value of npll_clk_rstb
        </comment>
      </bits>
      <bits access="rw" name="npll_clk_rstb_dr" pos="2" rst="0">
        <comment>
          direct control of npll_clk_rstb
        </comment>
      </bits>
      <bits access="rw" name="npll_sdm_clk_sel_reg" pos="1" rst="0">
        <comment>
          direct value of npll_sdm_clk_sel
        </comment>
      </bits>
      <bits access="rw" name="npll_sdm_clk_sel_dr" pos="0" rst="0">
        <comment>
          direct control of npll_sdm_clk_sel
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_reg1">
      <bits access="r" name="bbpll2_reg1_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpll_cp_rbit" pos="13:11" rst="4">
        <comment>
          GPLL pll_cpbias_rbit
        </comment>
      </bits>
      <bits access="rw" name="gpll_cp_ibit" pos="10:7" rst="1">
        <comment>
          GPLL pll_cpbias_ibit
        </comment>
      </bits>
      <bits access="rw" name="gpll_cpc2_bit" pos="6:4" rst="4">
        <comment>
          GPLL pll_cpc2_bit
        </comment>
      </bits>
      <bits access="rw" name="gpll_digreg_range" pos="3:0" rst="8">
        <comment>
          GPLL digreg_range
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_reg2">
      <bits access="r" name="bbpll2_reg2_reserved_0" pos="15:14" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpll_band_sel" pos="13:12" rst="0">
        <comment>
          GPLL band_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_testsig_sel" pos="11:10" rst="0">
        <comment>
          GPLL testsig_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_pcon_mode" pos="9" rst="0">
        <comment>
          GPLL pcom_mode
        </comment>
      </bits>
      <bits access="rw" name="gpll_refmulti2_en" pos="8" rst="1">
        <comment>
          GPLL refmulti2_en
        </comment>
      </bits>
      <bits access="rw" name="gpll_vco_high_test" pos="7" rst="0">
        <comment>
          GPLL vco_high_test
        </comment>
      </bits>
      <bits access="rw" name="gpll_vco_low_test" pos="6" rst="0">
        <comment>
          GPLL vco_low_test
        </comment>
      </bits>
      <bits access="rw" name="gpll_int_mode" pos="5" rst="0">
        <comment>
          GPLL int_mode
        </comment>
      </bits>
      <bits access="rw" name="gpll_sdm_clk_test_en" pos="4" rst="0">
        <comment>
          GPLL sdm_clk_test_en
        </comment>
      </bits>
      <bits access="rw" name="pu_gpll_dr1" pos="3" rst="0">
        <comment>
          direct conrol of analog pu_gpll
        </comment>
      </bits>
      <bits access="rw" name="pu_gpll_reg1" pos="2" rst="0">
        <comment>
          value of analog pu_gpll. It takes affect when pu_gpll_dr1 is 0b1
        </comment>
      </bits>
      <bits access="rw" name="pu_gpll_dr" pos="1" rst="0">
        <comment>
          direct conrol of baseband pu_gpll
        </comment>
      </bits>
      <bits access="rw" name="pu_gpll_reg" pos="0" rst="0">
        <comment>
          value of baseband pu_gpll. It takes affect when pu_gpll_dr is 0b1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_reg3">
      <bits access="r" name="bbpll2_reg3_reserved_0" pos="15:11" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpll_cpr2_bit" pos="10:8" rst="4">
        <comment>
          NPLL pll_cpr2_bit
        </comment>
      </bits>
      <bits access="rw" name="gpll_reser_reg" pos="7:0" rst="1">
        <comment>
          NPLL pll_reserved_reg
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_reg5">
      <bits access="rw" name="gpll_sdm_freq1" pos="15:0" rst="6144">
        <comment>
          bit [31:16] of GPLL SDM frequency
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_reg6">
      <bits access="rw" name="gpll_sdm_freq0" pos="15:0" rst="0">
        <comment>
          bit [15:0] of GPLL SDM frequency
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_reg7">
      <bits access="r" name="bbpll2_reg7_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpll_freq_bypass" pos="7" rst="0">
        <comment>
          bypass freq_enable, i.e., SDM frequency of GPLL takes effect immidiately when it is loaded into regsiter
0b0: no bypass
0b1: bypass
        </comment>
      </bits>
      <bits access="rw" name="gpll_int_dec_sel" pos="6:4" rst="3">
        <comment>
          decimal bit width selection of GPLL SDM output. It should be fixed to 3'b011 in 8809nez.
0b000: int divide
0b001: 1 bit decimal divide
0b010: 2 bits decimal divide
0b011: 3 bit decimal divide
others: bypass SDM
        </comment>
      </bits>
      <bits access="rw" name="gpll_dither_bypass" pos="3" rst="1">
        <comment>
          dither bypass of GPLL SDM
0b0: no bypass
0b1: bypass
        </comment>
      </bits>
      <bits access="rw" name="gpll_fbc_inv" pos="2" rst="0">
        <comment>
          feedback clock inverse used by GPLL SDM
0b0: no inverse
0b1: inverse
        </comment>
      </bits>
      <bits access="rw" name="gpll_sdm_resetn_dr" pos="1" rst="0">
        <comment>
          direct conrol of GPLL SDM reset
        </comment>
      </bits>
      <bits access="rw" name="gpll_sdm_resetn_reg" pos="0" rst="0">
        <comment>
          reset of GPLL SDM, active low. It takes affect when gpll_sdm_resetn_dr is 0b1
        </comment>
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="bbpll2_rega">
      <bits access="rw" name="gpll_sdm_reset_time_sel" pos="15:14" rst="1">
        <comment>
          the time to release reset of GPLL SDM after pu_gpll assert.
0b00: 10us
0b01: 12us
0b10: 15us
0b11: 40us
        </comment>
      </bits>
      <bits access="rw" name="gpll_sdmclk_sel_time_sel" pos="13:12" rst="1">
        <comment>
          no use
        </comment>
      </bits>
      <bits access="r" name="bbpll2_rega_reserved_0" pos="11:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_624m_en_reg" pos="6" rst="0">
        <comment>
          enable of 624MHz clock of GPLL to baseband
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_624m_sel_reg" pos="5" rst="0">
        <comment>
          select of 624MHz clock of GPLL to baseband
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_adc_sel_reg" pos="4" rst="1">
        <comment>
          select of 26MHz clock of GPLL to ADC
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_adc_en_reg" pos="3" rst="1">
        <comment>
          enable of 26MHz clock of GPLL to ADC
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_26m_en_reg" pos="2" rst="1">
        <comment>
          enable of 26MHz clock of GPLL to DFE
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_26m_sel_reg" pos="1" rst="1">
        <comment>
          select of 26MHz clock of GPLL to DFE
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_gen_en_reg" pos="0" rst="1">
        <comment>
          enable pu_gpll from baseband
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="bbpll2_regb">
      <bits access="r" name="gpll_pu" pos="15" rst="0">
        <comment>
          GPLL pu status
        </comment>
      </bits>
      <bits access="r" name="gpll_lock" pos="14" rst="0">
        <comment>
          GPLL lock status
        </comment>
      </bits>
      <bits access="r" name="gpll_sdm_resetn" pos="13" rst="0">
        <comment>
          GPLL SDM reset status
        </comment>
      </bits>
      <bits access="r" name="gpll_sdm_clk_sel" pos="12" rst="0">
        <comment>
          GPLL sdm_clk_sel status
        </comment>
      </bits>
      <bits access="r" name="gpll_clk_ready" pos="11" rst="0">
        <comment>
          GPLL clock status
        </comment>
      </bits>
      <bits access="r" name="gpll_lock_steady" pos="10" rst="0">
        <comment>
          GPLL locked status
        </comment>
      </bits>
      <bits access="r" name="bbpll2_regb_reserved_0" pos="9:0" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_regd">
      <bits access="r" name="bbpll2_regd_reserved_0" pos="15:6" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="resetn_gpll" pos="5" rst="1">
        <comment>
          software reset of logics to control GPLL pu and pd, active low
        </comment>
      </bits>
      <bits access="rw" name="gpll_clkout_en_counter_sel" pos="4:2" rst="2">
        <comment>
          the time to open GPLL clocks after pu_gpll assert.
0b000: 10us+50us+1us
0b000: 10us+60us+1us
0b000: 10us+70us+1us
0b000: 10us+80us+1us
0b000: 10us+90us+1us
0b000: 10us+100us+1us
        </comment>
      </bits>
      <bits access="rw" name="gpll_lock_counter_sel" pos="1:0" rst="1">
        <comment>
          GPLL locked time.
0b00: 1us
0b01: 2us
0b10: 3us
0b11: 4us
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="bbpll2_regf">
      <bits access="rw" name="gpll_clk2dig_624m_en_drreg" pos="15" rst="0">
        <comment>
          direct value of gpll_clk2dig_624m_en
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_624m_sel_drreg" pos="14" rst="0">
        <comment>
          direct value of gpll_clk2dig_624m_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_624m_en_dr" pos="13" rst="0">
        <comment>
          direct control of gpll_clk2dig_624m_en
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_624m_sel_dr" pos="12" rst="0">
        <comment>
          direct control of gpll_clk2dig_624m_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_26m_en_drreg" pos="11" rst="0">
        <comment>
          direct value of gpll_clk2dig_26m_en
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_adc_en_drreg" pos="10" rst="0">
        <comment>
          direct value of gpll_clk_adc_en
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_26m_sel_drreg" pos="9" rst="0">
        <comment>
          direct value of gpll_clk2dig_26m_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_adc_sel_drreg" pos="8" rst="0">
        <comment>
          direct value of gpll_clk_adc_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_26m_en_dr" pos="7" rst="0">
        <comment>
          direct control of gpll_clk2dig_26m_en
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_adc_en_dr" pos="6" rst="0">
        <comment>
          direct control of gpll_clk_adc_en
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk2dig_26m_sel_dr" pos="5" rst="0">
        <comment>
          direct control of gpll_clk2dig_26m_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_adc_sel_dr" pos="4" rst="0">
        <comment>
          direct control of gpll_clk_adc_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_rstb_reg" pos="3" rst="0">
        <comment>
          direct value of gpll_clk_rstb
        </comment>
      </bits>
      <bits access="rw" name="gpll_clk_rstb_dr" pos="2" rst="0">
        <comment>
          direct control of gpll_clk_rstb
        </comment>
      </bits>
      <bits access="rw" name="gpll_sdm_clk_sel_dr" pos="1" rst="0">
        <comment>
          direct control of gpll_sdm_clk_sel
        </comment>
      </bits>
      <bits access="rw" name="gpll_sdm_clk_sel_reg" pos="0" rst="0">
        <comment>
          direct value of gpll_sdm_clk_sel
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_cal_reg1">
      <bits access="rw" name="reg_90_bit1" pos="15:8" rst="0">
        <comment>
          rfpll_cal: target freq[15:8]
        </comment>
      </bits>
      <bits access="rw" name="reg_90_bit0" pos="7:0" rst="0">
        <comment>
          rfpll_cal: target freq[7:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_cal_reg2">
      <bits access="rw" name="reg_91_bit15to8" pos="15:8" rst="0">
        <comment>
          rfpll_cal:
[12:8]: xcvpll_vco_bits[12:8] in software
[13]: reserved
[14]: xcvpll_cnt_enable in software
[15]: xcvpll_cal_enable in software
        </comment>
      </bits>
      <bits access="rw" name="reg_91_bit70" pos="7" rst="0">
        <comment>
          rfpll_cal: reset, active low
        </comment>
      </bits>
      <bits access="rw" name="reg_91_bit6to0" pos="6:0" rst="0">
        <comment>
          rfpll_cal:
[0]: pll_cal_hd, select haredare(1) or software(0)
[1]: xcvpll_cal_opt  
[3:2]: xcvpll_cnt_delay_sel 
[6:4]: xcvpll_init_delay
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="rfpll_cal_reg3">
      <bits access="rw" name="reg_92_bit1" pos="15:8" rst="0">
        <comment>
          rfpll_cal: reserved
        </comment>
      </bits>
      <bits access="rw" name="reg_92_bit0" pos="7:0" rst="0">
        <comment>
          rfpll_cal: xcvpll_vco_bits[7:0] in software
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="rfpll_cal_reg4">
      <bits access="r" name="xcvpll_cal_enable" pos="15" rst="0">
        <comment>
          rfpll_cal xcv_pll_cal_en
        </comment>
      </bits>
      <bits access="r" name="xcvpll_cnt_enable" pos="14" rst="0">
        <comment>
          rfpll_cal xcv_pll_cnt_en
        </comment>
      </bits>
      <bits access="r" name="xcvpll_cal_ready" pos="13" rst="0">
        <comment>
          rfpll_cal xcvpll_cal_ready
        </comment>
      </bits>
      <bits access="r" name="xcvpll_vco_bits" pos="12:0" rst="0">
        <comment>
          rfpll_cal xcvpll_vco_bits
        </comment>
      </bits>
    </reg>
    <hole size="128"/>
    <reg protect="rw" name="gpio_reg">
      <bits access="rw" name="gpio_reg_out" pos="15:0" rst="0">
        <comment>
          no use
        </comment>
      </bits>
    </reg>
    <hole size="480"/>
    <reg protect="rw" name="pa_strobe">
      <bits access="r" name="pa_strobe_reserved_0" pos="15" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="strobe_dr" pos="14" rst="0">
        <comment>
          direct control of strobe.
0b0: strobe from baseband
0b1: strobe from register srobe_reg
        </comment>
      </bits>
      <bits access="rw" name="multi_slot_sel" pos="13:12" rst="0">
        <comment>
          multiple slots control.
0b00: 1 slot
0b01: 2 slots
0b10: 3 slots
0b11: 4 slots
        </comment>
      </bits>
      <bits access="rw" name="strobe_reg" pos="11" rst="0">
        <comment>
          direct value of strobe
        </comment>
      </bits>
      <bits access="rw" name="slot_number_dr" pos="10" rst="0">
        <comment>
          direct control of slot number
        </comment>
      </bits>
      <bits access="rw" name="slot_number_reg" pos="9:8" rst="0">
        <comment>
          direct value of slot number
        </comment>
      </bits>
      <bits access="rw" name="time_sel_after_rampd" pos="7:0" rst="0">
        <comment>
          counter after rampdown
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ctrl_reg1">
      <bits access="rw" name="ramp_curve_sel_3" pos="15:12" rst="0">
        <comment>
          seletction of PA ramp curve for the 4th slot
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_sel_2" pos="11:8" rst="0">
        <comment>
          seletction of PA ramp curve for the 3rd slot
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_sel_1" pos="7:4" rst="0">
        <comment>
          seletction of PA ramp curve for the 2nd slot
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_sel_0" pos="3:0" rst="0">
        <comment>
          seletction of PA ramp curve for the 1st slot
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ctrl_reg2">
      <bits access="rw" name="ramp_mult_factor_1" pos="15:8" rst="0">
        <comment>
          multiply factor of PA ramp curve for the 2nd slot
        </comment>
      </bits>
      <bits access="rw" name="ramp_mult_factor_0" pos="7:0" rst="0">
        <comment>
          multiply factor of PA ramp curve for the 1st slot
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ctrl_reg3">
      <bits access="rw" name="ramp_mult_factor_3" pos="15:8" rst="0">
        <comment>
          multiply factor of PA ramp curve for the 4th slot
        </comment>
      </bits>
      <bits access="rw" name="ramp_mult_factor_2" pos="7:0" rst="0">
        <comment>
          multiply factor of PA ramp curve for the 3rd slot
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ctrl_reg4">
      <bits access="r" name="pa_ctrl_reg4_reserved_0" pos="15:11" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="ramp_dac_din_reg" pos="10:1" rst="0">
        <comment>
          direct value of ramp_dac
        </comment>
      </bits>
      <bits access="rw" name="ramp_dac_din_dr" pos="0" rst="0">
        <comment>
          direct control of ramp_dac
        </comment>
      </bits>
    </reg>
    <hole size="352"/>
    <reg protect="rw" name="reg_100_bit">
      <bits access="rw" name="pu_lna" pos="15" rst="0">
        <comment>
          pu_lna
        </comment>
      </bits>
      <bits access="rw" name="pu_powdet_hb" pos="14" rst="0">
        <comment>
          pu_powdet_hb
        </comment>
      </bits>
      <bits access="rw" name="pu_powdet_lb" pos="13" rst="0">
        <comment>
          pu_powdet_lb
        </comment>
      </bits>
      <bits access="rw" name="pu_rmx" pos="12" rst="0">
        <comment>
          pu_rmx
        </comment>
      </bits>
      <bits access="rw" name="pu_pga" pos="11" rst="0">
        <comment>
          pu_pga
        </comment>
      </bits>
      <bits access="rw" name="pu_rxflt" pos="10" rst="0">
        <comment>
          pu_rxflt
        </comment>
      </bits>
      <bits access="rw" name="pu_adc" pos="9" rst="0">
        <comment>
          pu_adc
        </comment>
      </bits>
      <bits access="rw" name="pu_dac" pos="8" rst="0">
        <comment>
          pu_dac
        </comment>
      </bits>
      <bits access="rw" name="pu_txflt" pos="7" rst="0">
        <comment>
          pu_txflt
        </comment>
      </bits>
      <bits access="rw" name="pu_tmx" pos="6" rst="0">
        <comment>
          pu_tmx
        </comment>
      </bits>
      <bits access="rw" name="pu_ramp_dac" pos="5" rst="0">
        <comment>
          pu_ramp_dac
        </comment>
      </bits>
      <bits access="rw" name="pu_padrv" pos="4" rst="0">
        <comment>
          pu_padrv
        </comment>
      </bits>
      <bits access="rw" name="tx_powdet_en" pos="3" rst="0">
        <comment>
          tx_powdet_en
        </comment>
      </bits>
      <bits access="rw" name="pu_gsm_padrv" pos="2" rst="0">
        <comment>
          pu_gsm_padrv
        </comment>
      </bits>
      <bits access="rw" name="pu_vco" pos="1" rst="0">
        <comment>
          pu_vco
        </comment>
      </bits>
      <bits access="rw" name="pu_pll_presc" pos="0" rst="0">
        <comment>
          pu_pll_presc
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_101_bit">
      <bits access="rw" name="pu_pll_peri" pos="15" rst="0">
        <comment>
          pu_pll_peri
        </comment>
      </bits>
      <bits access="rw" name="pu_mdll" pos="14" rst="0">
        <comment>
          pu_mdll
        </comment>
      </bits>
      <bits access="rw" name="pu_ts" pos="13" rst="0">
        <comment>
          pu_ts
        </comment>
      </bits>
      <bits access="rw" name="pu_bg" pos="12" rst="0">
        <comment>
          pu_bg
        </comment>
      </bits>
      <bits access="rw" name="vco_rxcap_short" pos="11" rst="1">
        <comment>
          vco_rxcap_short
        </comment>
      </bits>
      <bits access="rw" name="vco_txcap_short" pos="10" rst="1">
        <comment>
          vco_txcap_short
        </comment>
      </bits>
      <bits access="rw" name="vco_sel_nb" pos="9" rst="0">
        <comment>
          vco_sel_nb
        </comment>
      </bits>
      <bits access="rw" name="vco_sel_trx" pos="8" rst="0">
        <comment>
          vco_sel_trx
        </comment>
      </bits>
      <bits access="rw" name="sel_bg" pos="7" rst="1">
        <comment>
          sel_bg
        </comment>
      </bits>
      <bits access="rw" name="ivref_bit" pos="6" rst="1">
        <comment>
          ivref_bit
        </comment>
      </bits>
      <bits access="rw" name="lna_band_sel" pos="5" rst="0">
        <comment>
          lna_band_sel
        </comment>
      </bits>
      <bits access="rw" name="gsm_tx_band_sel" pos="4" rst="0">
        <comment>
          gsm_tx_band_sel
        </comment>
      </bits>
      <bits access="rw" name="tx_band_sel" pos="3:2" rst="0">
        <comment>
          tx_band_sel[1:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_101_bit_reserved_0" pos="1" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
      <bits access="rw" name="pu_lvshifter" pos="0" rst="0">
        <comment>
          pu_lvshifter
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_102_bit">
      <bits access="rw" name="rxflt_rstn" pos="15" rst="0">
        <comment>
          rxflt_rstn
        </comment>
      </bits>
      <bits access="rw" name="adc_rstn" pos="14" rst="0">
        <comment>
          adc_rstn
        </comment>
      </bits>
      <bits access="rw" name="dac_rstn" pos="13" rst="0">
        <comment>
          dac_rstn
        </comment>
      </bits>
      <bits access="rw" name="txflt_rstn" pos="12" rst="0">
        <comment>
          txflt_rstn
        </comment>
      </bits>
      <bits access="rw" name="ts_rstn" pos="11" rst="0">
        <comment>
          ts_rstn
        </comment>
      </bits>
      <bits access="rw" name="mdll_startup" pos="10" rst="0">
        <comment>
          mdll_startup
        </comment>
      </bits>
      <bits access="rw" name="xtal_clk2xcv_rfpll_en" pos="9" rst="0">
        <comment>
          xtal_clk2xcv_rfpll_en
        </comment>
      </bits>
      <bits access="rw" name="xtal_clk2xcv_adc_en" pos="8" rst="0">
        <comment>
          xtal_clk2xcv_adc_en
        </comment>
      </bits>
      <bits access="rw" name="xtal_clk2ts_en" pos="7" rst="0">
        <comment>
          xtal_clk2ts_en
        </comment>
      </bits>
      <bits access="rw" name="reg_102_bit_reserved_0" pos="6:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_103_bit">
      <bits access="rw" name="mdll_startup_v" pos="15:13" rst="4">
        <comment>
          mdll_startup_v[2:0]
        </comment>
      </bits>
      <bits access="rw" name="mdll_clk2xcv_rfpll_enb" pos="12" rst="0">
        <comment>
          mdll_clk2xcv_rfpll_enb
        </comment>
      </bits>
      <bits access="rw" name="mdll_clk2bt_rfpll_enb" pos="11" rst="0">
        <comment>
          mdll_clk2bt_rfpll_enb
        </comment>
      </bits>
      <bits access="rw" name="mdll_div_num" pos="10:7" rst="0">
        <comment>
          mdll_div_num[3:0]
        </comment>
      </bits>
      <bits access="rw" name="mdll_dither_bit" pos="6:4" rst="4">
        <comment>
          mdll_dither_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="mdll_cp_ibit" pos="3:1" rst="2">
        <comment>
          mdll_cp_ibit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_103_bit_reserved_0" pos="0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_104_bit">
      <bits access="rw" name="mdll_band" pos="15:13" rst="0">
        <comment>
          mdll_band[2:0]
        </comment>
      </bits>
      <bits access="rw" name="mdll_band_sel" pos="12" rst="0">
        <comment>
          mdll_band_sel
        </comment>
      </bits>
      <bits access="rw" name="mdll_vctrl_test_en" pos="11" rst="0">
        <comment>
          mdll_vctrl_test_en
        </comment>
      </bits>
      <bits access="rw" name="mdll_dither_mode" pos="10" rst="1">
        <comment>
          mdll_dither_mode
        </comment>
      </bits>
      <bits access="rw" name="mdll_dither_en" pos="9" rst="1">
        <comment>
          mdll_dither_en
        </comment>
      </bits>
      <bits access="rw" name="reg_104_bit_reserved_0" pos="8:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_105_bit">
      <bits access="rw" name="pll_reg_presc_bit" pos="15:12" rst="0">
        <comment>
          pll_reg_presc_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_reg_flt_bit" pos="11:8" rst="0">
        <comment>
          pll_reg_flt_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_reg_dig_bit" pos="7:4" rst="0">
        <comment>
          pll_reg_dig_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_reg_div2_bit" pos="3:1" rst="4">
        <comment>
          pll_reg_div2_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_lp_mode" pos="0" rst="0">
        <comment>
          pll_lp_mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_106_bit">
      <bits access="rw" name="pll_open_en" pos="15" rst="0">
        <comment>
          pll_open_en
        </comment>
      </bits>
      <bits access="rw" name="pll_ref_sel" pos="14" rst="0">
        <comment>
          pll_ref_sel
        </comment>
      </bits>
      <bits access="rw" name="pll_sdm_clk_sel" pos="13" rst="0">
        <comment>
          pll_sdm_clk_sel
        </comment>
      </bits>
      <bits access="rw" name="pll_cal_clk_sel" pos="12" rst="0">
        <comment>
          pll_cal_clk_sel
        </comment>
      </bits>
      <bits access="rw" name="pll_fdiv_sel" pos="11" rst="0">
        <comment>
          pll_fdiv_sel
        </comment>
      </bits>
      <bits access="rw" name="pll_bypass_notch" pos="10" rst="0">
        <comment>
          pll_bypass_notch
        </comment>
      </bits>
      <bits access="rw" name="pll_xfer_aux_en" pos="9" rst="0">
        <comment>
          pll_xfer_aux_en
        </comment>
      </bits>
      <bits access="rw" name="pll_vco_gain_bit" pos="8:5" rst="9">
        <comment>
          pll_vco_gain_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_sinc_mode" pos="4:2" rst="1">
        <comment>
          pll_sinc_mode[2:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_refmulti2_en" pos="1" rst="0">
        <comment>
          pll_refmulti2_en
        </comment>
      </bits>
      <bits access="rw" name="reg_106_bit_reserved_0" pos="0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_107_bit">
      <bits access="rw" name="pll_r_bit" pos="15:14" rst="2">
        <comment>
          pll_r_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_pfd_res_bit" pos="13:8" rst="30">
        <comment>
          pll_pfd_res_bit[5:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_lpf_gain" pos="7:4" rst="0">
        <comment>
          pll_lpf_gain[3:0]
        </comment>
      </bits>
      <bits access="rw" name="pll_cp_bit" pos="3:0" rst="0">
        <comment>
          pll_cp_bit[3:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_108_bit">
      <bits access="rw" name="pll_cal_bit" pos="15:14" rst="1">
        <comment>
          pll_cal_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="vco_aux_capbit" pos="13:10" rst="7">
        <comment>
          vco_aux_capbit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_108_bit_reserved_0" pos="9:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_109_bit">
      <bits access="rw" name="vco_core_ibit" pos="15:11" rst="8">
        <comment>
          vco_core_ibit[4:0]
        </comment>
      </bits>
      <bits access="rw" name="vco_lp_en" pos="10" rst="0">
        <comment>
          vco_lp_en
        </comment>
      </bits>
      <bits access="rw" name="vco_v_mode" pos="9" rst="1">
        <comment>
          vco_v_mode
        </comment>
      </bits>
      <bits access="rw" name="vco_reg_buf_bit" pos="8:4" rst="0">
        <comment>
          vco_reg_buf_bit[4:0]
        </comment>
      </bits>
      <bits access="rw" name="vco_reg_buf_lp_bit" pos="3:1" rst="3">
        <comment>
          vco_reg_buf_lp_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="vco_reg_buf_lp_mode" pos="0" rst="0">
        <comment>
          vco_reg_buf_lp_mode
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_10a_bit">
      <bits access="rw" name="lna_s2d_en" pos="15" rst="1">
        <comment>
          lna_s2d_en
        </comment>
      </bits>
      <bits access="rw" name="lna_diff_en" pos="14" rst="0">
        <comment>
          lna_diff_en
        </comment>
      </bits>
      <bits access="rw" name="lna_avdd_sel" pos="13" rst="1">
        <comment>
          lna_avdd_sel
        </comment>
      </bits>
      <bits access="rw" name="lna_nwell_sel" pos="12" rst="1">
        <comment>
          lna_nwell_sel
        </comment>
      </bits>
      <bits access="rw" name="lna_res_short" pos="11" rst="0">
        <comment>
          lna_res_short
        </comment>
      </bits>
      <bits access="rw" name="powdet_ref_bit" pos="10:8" rst="4">
        <comment>
          powdet_ref_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="powdet_mode" pos="7" rst="0">
        <comment>
          powdet_mode
        </comment>
      </bits>
      <bits access="rw" name="pga_bw_rbit" pos="6:5" rst="0">
        <comment>
          pga_bw_rbit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="pga_bw_cbit" pos="4:3" rst="3">
        <comment>
          pga_bw_cbit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="pga_cal_resolv" pos="2:1" rst="0">
        <comment>
          pga_cal_resolv[1:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_10a_bit_reserved_0" pos="0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_10b_bit">
      <bits access="rw" name="pga_cal_i" pos="15:8" rst="128">
        <comment>
          pga_cal_i[7:0]
        </comment>
      </bits>
      <bits access="rw" name="pga_cal_q" pos="7:0" rst="128">
        <comment>
          pga_cal_q[7:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_10c_bit">
      <bits access="rw" name="rxflt_iq_swap" pos="15" rst="0">
        <comment>
          rxflt_iq_swap
        </comment>
      </bits>
      <bits access="rw" name="rxflt_if_bit" pos="14:13" rst="1">
        <comment>
          rxflt_if_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="rxflt_cap_bit" pos="12:9" rst="7">
        <comment>
          rxflt_cap_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="rxflt_cal_mode" pos="8" rst="1">
        <comment>
          rxflt_cal_mode
        </comment>
      </bits>
      <bits access="rw" name="rxflt_cal_en" pos="7" rst="0">
        <comment>
          rxflt_cal_en
        </comment>
      </bits>
      <bits access="rw" name="rxflt_cal_clk_edge" pos="6" rst="0">
        <comment>
          rxflt_cal_clk_edge
        </comment>
      </bits>
      <bits access="rw" name="rxflt_auxin_en" pos="5" rst="0">
        <comment>
          rxflt_auxin_en
        </comment>
      </bits>
      <bits access="rw" name="reg_10c_bit_reserved_0" pos="4:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_10d_bit">
      <bits access="rw" name="adc_open" pos="15" rst="0">
        <comment>
          adc_open
        </comment>
      </bits>
      <bits access="rw" name="adc_iq_swap" pos="14" rst="0">
        <comment>
          adc_iq_swap
        </comment>
      </bits>
      <bits access="rw" name="adc_nrz_mode" pos="13" rst="0">
        <comment>
          adc_nrz_mode
        </comment>
      </bits>
      <bits access="rw" name="adc_lpass_mode" pos="12" rst="0">
        <comment>
          adc_lpass_mode
        </comment>
      </bits>
      <bits access="rw" name="adc_if200k_en" pos="11" rst="0">
        <comment>
          adc_if200k_en
        </comment>
      </bits>
      <bits access="rw" name="adc_cal_refi_en" pos="10" rst="0">
        <comment>
          adc_cal_refi_en
        </comment>
      </bits>
      <bits access="rw" name="adc_cal_refi_bit" pos="9:7" rst="4">
        <comment>
          adc_cal_refi_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="adc_clk_xtal26m_en" pos="6" rst="1">
        <comment>
          adc_clk_xtal26m_en
        </comment>
      </bits>
      <bits access="rw" name="adc_clk_gsm26m_en" pos="5" rst="0">
        <comment>
          adc_clk_gsm26m_en
        </comment>
      </bits>
      <bits access="rw" name="adc_clk_nb30m_en" pos="4" rst="0">
        <comment>
          adc_clk_nb30m_en
        </comment>
      </bits>
      <bits access="rw" name="reg_10d_bit_reserved_0" pos="3:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_10e_bit">
      <bits access="rw" name="padrv_bias_ibit" pos="15:10" rst="7">
        <comment>
          padrv_bias_ibit[5:0]
        </comment>
      </bits>
      <bits access="rw" name="padrv_vbias_bit" pos="9:6" rst="7">
        <comment>
          padrv_vbias_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="padrv_cap_bit" pos="5:2" rst="7">
        <comment>
          padrv_cap_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_10e_bit_reserved_0" pos="1:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_10f_bit">
      <bits access="rw" name="tmx_vcom_sel" pos="15" rst="1">
        <comment>
          tmx_vcom_sel
        </comment>
      </bits>
      <bits access="rw" name="tmx_reg_bypass" pos="14" rst="0">
        <comment>
          tmx_reg_bypass
        </comment>
      </bits>
      <bits access="rw" name="tmx_lobias_bit" pos="13:11" rst="4">
        <comment>
          tmx_lobias_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="tmx_lobuff_drv_bit" pos="10:9" rst="2">
        <comment>
          tmx_lobuff_drv_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="tmx_vcom_nbit" pos="8:3" rst="16">
        <comment>
          tmx_vcom_nbit[5:0]
        </comment>
      </bits>
      <bits access="rw" name="tmx_reg_div_bit" pos="2:0" rst="4">
        <comment>
          tmx_reg_div_bit[2:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_110_bit">
      <bits access="rw" name="tmx_vcom_pbit" pos="15:10" rst="16">
        <comment>
          tmx_vcom_pbit[5:0]
        </comment>
      </bits>
      <bits access="rw" name="gsm_tx_div2_bias_bit" pos="9:7" rst="1">
        <comment>
          gsm_tx_div2_bias_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_110_bit_reserved_0" pos="6:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_111_bit">
      <bits access="rw" name="txflt_lp_mode" pos="15" rst="1">
        <comment>
          txflt_lp_mode
        </comment>
      </bits>
      <bits access="rw" name="txflt_op_ibit" pos="14:13" rst="2">
        <comment>
          txflt_op_ibit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="txflt_mode_bit" pos="12:11" rst="2">
        <comment>
          txflt_mode_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="txflt_cap_bit" pos="10:7" rst="7">
        <comment>
          txflt_cap_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="txflt_cal1_en" pos="6" rst="0">
        <comment>
          txflt_cal1_en
        </comment>
      </bits>
      <bits access="rw" name="txflt_cal2_en" pos="5" rst="0">
        <comment>
          txflt_cal2_en
        </comment>
      </bits>
      <bits access="rw" name="txflt_cal_clk_edge" pos="4" rst="1">
        <comment>
          txflt_cal_clk_edge
        </comment>
      </bits>
      <bits access="rw" name="dac_vtr_sel" pos="3" rst="1">
        <comment>
          dac_vtr_sel
        </comment>
      </bits>
      <bits access="rw" name="dac_vlow_ctrl_bit" pos="2:0" rst="4">
        <comment>
          dac_vlow_ctrl_bit[2:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_112_bit">
      <bits access="rw" name="dac_isel_bit" pos="15:12" rst="1">
        <comment>
          dac_isel_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="dac_core_bit" pos="11:9" rst="4">
        <comment>
          dac_core_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="dac_cm_bit" pos="8:7" rst="2">
        <comment>
          dac_cm_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="dac_mux_en_bit" pos="6:5" rst="2">
        <comment>
          dac_mux_en_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="dac_iout_en" pos="4" rst="0">
        <comment>
          dac_iout_en
        </comment>
      </bits>
      <bits access="rw" name="dac_clk_edge" pos="3" rst="1">
        <comment>
          dac_clk_edge
        </comment>
      </bits>
      <bits access="rw" name="bt_mon_sel" pos="2" rst="0">
        <comment>
          bt_mon_sel
        </comment>
      </bits>
      <bits access="rw" name="auxflt_out_en" pos="1:0" rst="0">
        <comment>
          auxflt_out_en[1:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_113_bit">
      <bits access="rw" name="lna_gain_bit" pos="15:14" rst="2">
        <comment>
          lna_gain_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="lna_fb_rbit" pos="13:11" rst="2">
        <comment>
          lna_fb_rbit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="lna_blk_en" pos="10:8" rst="0">
        <comment>
          lna_blk_en[2:0]
        </comment>
      </bits>
      <bits access="rw" name="lna_ibit" pos="7:4" rst="8">
        <comment>
          lna_ibit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="lna_vbit" pos="3:0" rst="7">
        <comment>
          lna_vbit[3:0]
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_114_bit">
      <bits access="rw" name="lna_vbcg_bit" pos="15:13" rst="6">
        <comment>
          lna_vbcg_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="rmx_lp_mode" pos="12" rst="0">
        <comment>
          rmx_lp_mode
        </comment>
      </bits>
      <bits access="rw" name="rmx_lobias_bit" pos="11:9" rst="4">
        <comment>
          rmx_lobias_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="rmx_gain_bit" pos="8:6" rst="5">
        <comment>
          rmx_gain_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="rmx_div_sel" pos="5:4" rst="0">
        <comment>
          rmx_div_sel[1:0]
        </comment>
      </bits>
      <bits access="rw" name="rmx_div2_bias_bit" pos="3:1" rst="1">
        <comment>
          rmx_div2_bias_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_114_bit_reserved_0" pos="0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_115_bit">
      <bits access="rw" name="pga_gain_bit" pos="15:14" rst="3">
        <comment>
          pga_gain_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="pga_drv_ibit" pos="13" rst="0">
        <comment>
          pga_drv_ibit
        </comment>
      </bits>
      <bits access="rw" name="pga_op_ibit" pos="12:11" rst="3">
        <comment>
          pga_op_ibit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="pga_bypass" pos="10" rst="0">
        <comment>
          pga_bypass
        </comment>
      </bits>
      <bits access="rw" name="rxflt_gain1_bit" pos="9:8" rst="3">
        <comment>
          rxflt_gain1_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="rxflt_gain2_bit" pos="7:6" rst="3">
        <comment>
          rxflt_gain2_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="rxflt_lp_mode" pos="5:3" rst="7">
        <comment>
          rxflt_lp_mode[2:0]
        </comment>
      </bits>
      <bits access="rw" name="rxflt_op_ibit" pos="2:1" rst="2">
        <comment>
          rxflt_op_ibit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_115_bit_reserved_0" pos="0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_116_bit">
      <bits access="rw" name="adc_gain_bit" pos="15:14" rst="2">
        <comment>
          adc_gain_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="adc_isel_bit" pos="13:12" rst="1">
        <comment>
          adc_isel_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="adc_lp_mode" pos="11" rst="0">
        <comment>
          adc_lp_mode
        </comment>
      </bits>
      <bits access="rw" name="reg_116_bit_reserved_0" pos="10:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_117_bit">
      <bits access="rw" name="padrv_balun_swap" pos="15" rst="1">
        <comment>
          padrv_balun_swap
        </comment>
      </bits>
      <bits access="rw" name="padrv_gain_bit" pos="14:11" rst="13">
        <comment>
          padrv_gain_bit[3:0]
        </comment>
      </bits>
      <bits access="rw" name="tmx_gain_bit" pos="10:8" rst="7">
        <comment>
          tmx_gain_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="txflt_gain_bit" pos="7:5" rst="7">
        <comment>
          txflt_gain_bit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="dac_range_bit" pos="4:3" rst="2">
        <comment>
          dac_range_bit[1:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_117_bit_reserved_0" pos="2:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_118_bit">
      <bits access="rw" name="ramp_dac_gain_bit" pos="15:11" rst="0">
        <comment>
          ramp_dac_gain_bit[4:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_118_bit_reserved_0" pos="10:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_119_bit">
      <bits access="rw" name="ts_adc_ibit" pos="15:13" rst="3">
        <comment>
          ts_adc_ibit[2:0]
        </comment>
      </bits>
      <bits access="rw" name="ts_vref_bg_sel" pos="12" rst="1">
        <comment>
          ts_vref_bg_sel
        </comment>
      </bits>
      <bits access="rw" name="ts_vbe_bias_sdm" pos="11" rst="0">
        <comment>
          ts_vbe_bias_sdm
        </comment>
      </bits>
      <bits access="rw" name="ts_vbe_bias_bit" pos="10:3" rst="0">
        <comment>
          ts_vbe_bias_bit[7:0]
        </comment>
      </bits>
      <bits access="rw" name="ts_clk_sel" pos="2:1" rst="1">
        <comment>
          ts_clk_sel[1:0]
        </comment>
      </bits>
      <bits access="rw" name="ts_clk_reverse" pos="0" rst="0">
        <comment>
          ts_clk_reverse
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_11a_bit">
      <bits access="rw" name="ts_div_num" pos="15:12" rst="0">
        <comment>
          ts_div_num[3:0]
        </comment>
      </bits>
      <bits access="rw" name="ts_chopper_en" pos="11" rst="1">
        <comment>
          ts_chopper_en
        </comment>
      </bits>
      <bits access="rw" name="ts_beta_indep_en" pos="10" rst="0">
        <comment>
          ts_beta_indep_en
        </comment>
      </bits>
      <bits access="rw" name="ts_test_xtal_en" pos="9" rst="0">
        <comment>
          ts_test_xtal_en
        </comment>
      </bits>
      <bits access="rw" name="ts_vref_ctrl" pos="8:6" rst="4">
        <comment>
          ts_vref_ctrl[2:0]
        </comment>
      </bits>
      <bits access="rw" name="reg_11a_bit_reserved_0" pos="5:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="reg_11b_bit">
      <bits access="r" name="powdet_latch_out_hb" pos="15" rst="0">
        <comment>
          powdet_latch_out_hb
        </comment>
      </bits>
      <bits access="r" name="powdet_latch_out_lb" pos="14" rst="0">
        <comment>
          powdet_latch_out_lb
        </comment>
      </bits>
      <bits access="r" name="rxflt_cal_out_i" pos="13" rst="0">
        <comment>
          rxflt_cal_out_i
        </comment>
      </bits>
      <bits access="r" name="rxflt_cal_out_q" pos="12" rst="0">
        <comment>
          rxflt_cal_out_q
        </comment>
      </bits>
      <bits access="r" name="txflt_cal_out_i" pos="11" rst="0">
        <comment>
          txflt_cal_out_i
        </comment>
      </bits>
      <bits access="r" name="txflt_cal_out_q" pos="10" rst="0">
        <comment>
          txflt_cal_out_q
        </comment>
      </bits>
      <bits access="r" name="pll_lock" pos="9" rst="0">
        <comment>
          pll_lock
        </comment>
      </bits>
      <bits access="r" name="adc_cal_c_out" pos="8" rst="0">
        <comment>
          adc_cal_c_out
        </comment>
      </bits>
      <bits access="r" name="avss" pos="7:0" rst="0">
        <comment>
          avss
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_11c_bit">
      <bits access="rw" name="reg_11c_bit_reserved_0" pos="15:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="reg_11d_bit">
      <bits access="rw" name="reg_11d_bit_reserved_0" pos="15:0" rst="0">
        <comment>
          Reserved
        </comment>
      </bits>
    </reg>
    <hole size="3136"/>
    <reg protect="rw" name="control_rf_reg0">
      <bits access="r" name="control_rf_reg0_reserved_0" pos="15:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="rx_tx_rf" pos="2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dccal_q_enable_reg" pos="1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="dccal_i_enable_reg" pos="0" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="control_rf_reg1">
      <bits access="r" name="control_rf_reg1_reserved_0" pos="15:7" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpio_auxclk_en_nodelay" pos="6" rst="1">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="aux_buf_delay" pos="5" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpio_auxclk_en_dr" pos="4" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="gpio_auxclk_en_reg" pos="3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="thermo_cal_enable" pos="2" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="polarity_i" pos="1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="polarity_q" pos="0" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="control_rf_reg2">
      <bits access="rw" name="cnt_max_dccal_i" pos="15:0" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="control_rf_reg3">
      <bits access="r" name="control_rf_reg3_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="cnt_max_dccal_q" pos="7:0" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="control_rf_reg6">
      <bits access="r" name="control_rf_reg6_reserved_0" pos="15:1" rst="0">
      </bits>
      <bits access="rw" name="chip_tx_mode_reg" pos="0" rst="0">
        <comment>
          reset of PA ramp logics, active low
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_gen_reg0">
      <bits access="r" name="clk_gen_reg0_reserved_0" pos="15" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_4" pos="14:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_3" pos="11:9" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_2" pos="8:6" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_1" pos="5:3" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_0" pos="2:0" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_gen_reg1">
      <bits access="r" name="clk_gen_reg1_reserved_0" pos="15:9" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_7" pos="8:6" rst="0">
        <comment>
          clock selection of xcv_cal_clk[2]
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_6" pos="5:3" rst="0">
        <comment>
          clock selection of xcv_cal_clk[1]
        </comment>
      </bits>
      <bits access="rw" name="freq_clk_div_5" pos="2:0" rst="0">
        <comment>
          clock selection of xcv_cal_clk[0].
0b000: 26MHz/1024
0b001: 26MHz/512
0b010: 26MHz/256
0b011: 26MHz/128
0b100: 26MHz/64
0b101: 26MHz/32
0b110: 26MHz/16
0b111: 26MHz/8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="clk_gen_reg2">
      <bits access="rw" name="inv_clk_div" pos="15:8" rst="0">
        <comment>
          clock inverse of xcv_cal_clk and inernal clocks
        </comment>
      </bits>
      <bits access="rw" name="enable_clk_div" pos="7:0" rst="0">
        <comment>
          clock enable of xcv_cal_clk and inernal clocks
        </comment>
      </bits>
    </reg>
    <hole size="3840"/>
    <reg protect="r" name="chip_id_reg0">
      <bits access="r" name="chip_id0" pos="15:0" rst="35081">
        <comment>
          chip id0
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="chip_id_reg1">
      <bits access="r" name="chip_id_reg1_reserved_0" pos="15:8" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="chip_id1" pos="7:0" rst="0">
        <comment>
          chip id1
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="chip_id_reg2">
      <bits access="r" name="revision_id" pos="15:0" rst="35081">
        <comment>
          revision_id
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="mean_dcccal_i_reg0">
      <bits access="r" name="mean_dccal_i0" pos="15:0" rst="0">
        <comment>
          bit [15:0] of mean_dccal_i
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="mean_dcccal_i_reg1">
      <bits access="r" name="mean_dcccal_i_reg1_reserved_0" pos="15:1" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="mean_dccal_i1" pos="0" rst="0">
        <comment>
          bit [16] of mean_dccal_i
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="mean_dcccal_q_reg">
      <bits access="r" name="mean_dcccal_q_reg_reserved_0" pos="15:9" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="r" name="mean_dccal_q" pos="8:0" rst="0">
        <comment>
          mean_dccal_q
        </comment>
      </bits>
    </reg>
    <reg protect="r" name="revid_reg">
      <bits access="r" name="revid_reg_reserved_0" pos="15:8" rst="0">
        <comment>
          reseved
        </comment>
      </bits>
      <bits access="r" name="revid_tx" pos="7:4" rst="0">
        <comment>
          GPLL
        </comment>
      </bits>
      <bits access="r" name="revid_rx" pos="3:0" rst="0">
        <comment>
          NPLL
        </comment>
      </bits>
    </reg>
    <hole size="7968"/>
    <reg protect="rw" name="pa_ramp_reg0">
      <bits access="rw" name="ramp_curv0_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg1">
      <bits access="rw" name="ramp_curv0_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg2">
      <bits access="rw" name="ramp_curv0_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg3">
      <bits access="rw" name="ramp_curv0_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg4">
      <bits access="rw" name="ramp_curv0_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg5">
      <bits access="rw" name="ramp_curv0_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg6">
      <bits access="rw" name="ramp_curv0_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg7">
      <bits access="rw" name="ramp_curv0_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv0_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg10">
      <bits access="rw" name="ramp_curv1_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg11">
      <bits access="rw" name="ramp_curv1_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg12">
      <bits access="rw" name="ramp_curv1_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg13">
      <bits access="rw" name="ramp_curv1_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg14">
      <bits access="rw" name="ramp_curv1_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg15">
      <bits access="rw" name="ramp_curv1_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg16">
      <bits access="rw" name="ramp_curv1_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg17">
      <bits access="rw" name="ramp_curv1_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv1_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg20">
      <bits access="rw" name="ramp_curv2_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg21">
      <bits access="rw" name="ramp_curv2_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg22">
      <bits access="rw" name="ramp_curv2_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg23">
      <bits access="rw" name="ramp_curv2_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg24">
      <bits access="rw" name="ramp_curv2_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg25">
      <bits access="rw" name="ramp_curv2_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg26">
      <bits access="rw" name="ramp_curv2_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg27">
      <bits access="rw" name="ramp_curv2_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv2_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg30">
      <bits access="rw" name="ramp_curv3_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg31">
      <bits access="rw" name="ramp_curv3_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg32">
      <bits access="rw" name="ramp_curv3_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg33">
      <bits access="rw" name="ramp_curv3_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg34">
      <bits access="rw" name="ramp_curv3_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg35">
      <bits access="rw" name="ramp_curv3_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg36">
      <bits access="rw" name="ramp_curv3_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg37">
      <bits access="rw" name="ramp_curv3_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv3_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg40">
      <bits access="rw" name="ramp_curv4_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg41">
      <bits access="rw" name="ramp_curv4_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg42">
      <bits access="rw" name="ramp_curv4_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg43">
      <bits access="rw" name="ramp_curv4_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg44">
      <bits access="rw" name="ramp_curv4_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg45">
      <bits access="rw" name="ramp_curv4_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg46">
      <bits access="rw" name="ramp_curv4_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg47">
      <bits access="rw" name="ramp_curv4_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv4_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg50">
      <bits access="rw" name="ramp_curv5_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg51">
      <bits access="rw" name="ramp_curv5_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg52">
      <bits access="rw" name="ramp_curv5_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg53">
      <bits access="rw" name="ramp_curv5_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg54">
      <bits access="rw" name="ramp_curv5_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg55">
      <bits access="rw" name="ramp_curv5_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg56">
      <bits access="rw" name="ramp_curv5_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg57">
      <bits access="rw" name="ramp_curv5_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv5_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg60">
      <bits access="rw" name="ramp_curv6_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg61">
      <bits access="rw" name="ramp_curv6_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg62">
      <bits access="rw" name="ramp_curv6_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg63">
      <bits access="rw" name="ramp_curv6_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg64">
      <bits access="rw" name="ramp_curv6_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg65">
      <bits access="rw" name="ramp_curv6_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg66">
      <bits access="rw" name="ramp_curv6_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg67">
      <bits access="rw" name="ramp_curv6_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv6_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg70">
      <bits access="rw" name="ramp_curv7_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg71">
      <bits access="rw" name="ramp_curv7_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg72">
      <bits access="rw" name="ramp_curv7_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg73">
      <bits access="rw" name="ramp_curv7_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg74">
      <bits access="rw" name="ramp_curv7_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg75">
      <bits access="rw" name="ramp_curv7_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg76">
      <bits access="rw" name="ramp_curv7_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg77">
      <bits access="rw" name="ramp_curv7_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv7_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg80">
      <bits access="rw" name="ramp_curv8_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg81">
      <bits access="rw" name="ramp_curv8_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg82">
      <bits access="rw" name="ramp_curv8_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg83">
      <bits access="rw" name="ramp_curv8_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg84">
      <bits access="rw" name="ramp_curv8_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg85">
      <bits access="rw" name="ramp_curv8_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg86">
      <bits access="rw" name="ramp_curv8_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg87">
      <bits access="rw" name="ramp_curv8_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv8_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg90">
      <bits access="rw" name="ramp_curv9_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg91">
      <bits access="rw" name="ramp_curv9_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg92">
      <bits access="rw" name="ramp_curv9_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg93">
      <bits access="rw" name="ramp_curv9_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg94">
      <bits access="rw" name="ramp_curv9_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg95">
      <bits access="rw" name="ramp_curv9_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg96">
      <bits access="rw" name="ramp_curv9_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg97">
      <bits access="rw" name="ramp_curv9_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv9_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega0">
      <bits access="rw" name="ramp_curva_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega1">
      <bits access="rw" name="ramp_curva_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega2">
      <bits access="rw" name="ramp_curva_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega3">
      <bits access="rw" name="ramp_curva_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega4">
      <bits access="rw" name="ramp_curva_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega5">
      <bits access="rw" name="ramp_curva_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega6">
      <bits access="rw" name="ramp_curva_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rega7">
      <bits access="rw" name="ramp_curva_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curva_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb0">
      <bits access="rw" name="ramp_curvb_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb1">
      <bits access="rw" name="ramp_curvb_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb2">
      <bits access="rw" name="ramp_curvb_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb3">
      <bits access="rw" name="ramp_curvb_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb4">
      <bits access="rw" name="ramp_curvb_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb5">
      <bits access="rw" name="ramp_curvb_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb6">
      <bits access="rw" name="ramp_curvb_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regb7">
      <bits access="rw" name="ramp_curvb_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp up curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvb_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp up curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc0">
      <bits access="rw" name="ramp_curvc_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc1">
      <bits access="rw" name="ramp_curvc_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc2">
      <bits access="rw" name="ramp_curvc_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc3">
      <bits access="rw" name="ramp_curvc_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc4">
      <bits access="rw" name="ramp_curvc_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc5">
      <bits access="rw" name="ramp_curvc_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc6">
      <bits access="rw" name="ramp_curvc_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regc7">
      <bits access="rw" name="ramp_curvc_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve0
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvc_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve0
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd0">
      <bits access="rw" name="ramp_curvd_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd1">
      <bits access="rw" name="ramp_curvd_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd2">
      <bits access="rw" name="ramp_curvd_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd3">
      <bits access="rw" name="ramp_curvd_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd4">
      <bits access="rw" name="ramp_curvd_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd5">
      <bits access="rw" name="ramp_curvd_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd6">
      <bits access="rw" name="ramp_curvd_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regd7">
      <bits access="rw" name="ramp_curvd_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve1
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvd_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve1
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege0">
      <bits access="rw" name="ramp_curve_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege1">
      <bits access="rw" name="ramp_curve_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege2">
      <bits access="rw" name="ramp_curve_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege3">
      <bits access="rw" name="ramp_curve_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege4">
      <bits access="rw" name="ramp_curve_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege5">
      <bits access="rw" name="ramp_curve_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege6">
      <bits access="rw" name="ramp_curve_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_rege7">
      <bits access="rw" name="ramp_curve_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve2
        </comment>
      </bits>
      <bits access="rw" name="ramp_curve_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve2
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf0">
      <bits access="rw" name="ramp_curvf_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf1">
      <bits access="rw" name="ramp_curvf_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf2">
      <bits access="rw" name="ramp_curvf_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf3">
      <bits access="rw" name="ramp_curvf_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf4">
      <bits access="rw" name="ramp_curvf_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf5">
      <bits access="rw" name="ramp_curvf_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf6">
      <bits access="rw" name="ramp_curvf_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_regf7">
      <bits access="rw" name="ramp_curvf_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve3
        </comment>
      </bits>
      <bits access="rw" name="ramp_curvf_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve3
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg100">
      <bits access="rw" name="ramp_curv10_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg101">
      <bits access="rw" name="ramp_curv10_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg102">
      <bits access="rw" name="ramp_curv10_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg103">
      <bits access="rw" name="ramp_curv10_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg104">
      <bits access="rw" name="ramp_curv10_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg105">
      <bits access="rw" name="ramp_curv10_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg106">
      <bits access="rw" name="ramp_curv10_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg107">
      <bits access="rw" name="ramp_curv10_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve4
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv10_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve4
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg110">
      <bits access="rw" name="ramp_curv11_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg111">
      <bits access="rw" name="ramp_curv11_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg112">
      <bits access="rw" name="ramp_curv11_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg113">
      <bits access="rw" name="ramp_curv11_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg114">
      <bits access="rw" name="ramp_curv11_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg115">
      <bits access="rw" name="ramp_curv11_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg116">
      <bits access="rw" name="ramp_curv11_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg117">
      <bits access="rw" name="ramp_curv11_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve5
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv11_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve5
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg120">
      <bits access="rw" name="ramp_curv12_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg121">
      <bits access="rw" name="ramp_curv12_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg122">
      <bits access="rw" name="ramp_curv12_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg123">
      <bits access="rw" name="ramp_curv12_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg124">
      <bits access="rw" name="ramp_curv12_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg125">
      <bits access="rw" name="ramp_curv12_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg126">
      <bits access="rw" name="ramp_curv12_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg127">
      <bits access="rw" name="ramp_curv12_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve6
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv12_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve6
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg130">
      <bits access="rw" name="ramp_curv13_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg131">
      <bits access="rw" name="ramp_curv13_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg132">
      <bits access="rw" name="ramp_curv13_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg133">
      <bits access="rw" name="ramp_curv13_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg134">
      <bits access="rw" name="ramp_curv13_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg135">
      <bits access="rw" name="ramp_curv13_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg136">
      <bits access="rw" name="ramp_curv13_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg137">
      <bits access="rw" name="ramp_curv13_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve7
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv13_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve7
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg140">
      <bits access="rw" name="ramp_curv14_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg141">
      <bits access="rw" name="ramp_curv14_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg142">
      <bits access="rw" name="ramp_curv14_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg143">
      <bits access="rw" name="ramp_curv14_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg144">
      <bits access="rw" name="ramp_curv14_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg145">
      <bits access="rw" name="ramp_curv14_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg146">
      <bits access="rw" name="ramp_curv14_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg147">
      <bits access="rw" name="ramp_curv14_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve8
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv14_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve8
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg150">
      <bits access="rw" name="ramp_curv15_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg151">
      <bits access="rw" name="ramp_curv15_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg152">
      <bits access="rw" name="ramp_curv15_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg153">
      <bits access="rw" name="ramp_curv15_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg154">
      <bits access="rw" name="ramp_curv15_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg155">
      <bits access="rw" name="ramp_curv15_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg156">
      <bits access="rw" name="ramp_curv15_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg157">
      <bits access="rw" name="ramp_curv15_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve9
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv15_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve9
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg160">
      <bits access="rw" name="ramp_curv16_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg161">
      <bits access="rw" name="ramp_curv16_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg162">
      <bits access="rw" name="ramp_curv16_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg163">
      <bits access="rw" name="ramp_curv16_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg164">
      <bits access="rw" name="ramp_curv16_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg165">
      <bits access="rw" name="ramp_curv16_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg166">
      <bits access="rw" name="ramp_curv16_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg167">
      <bits access="rw" name="ramp_curv16_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve10
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv16_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve10
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg170">
      <bits access="rw" name="ramp_curv17_p1" pos="15:8" rst="24">
        <comment>
          point 1 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_p0" pos="7:0" rst="0">
        <comment>
          point 0 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg171">
      <bits access="rw" name="ramp_curv17_p3" pos="15:8" rst="76">
        <comment>
          point 3 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_p2" pos="7:0" rst="52">
        <comment>
          point 2 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg172">
      <bits access="rw" name="ramp_curv17_p5" pos="15:8" rst="124">
        <comment>
          point 5 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_p4" pos="7:0" rst="104">
        <comment>
          point 4 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg173">
      <bits access="rw" name="ramp_curv17_p7" pos="15:8" rst="168">
        <comment>
          point 7 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_p6" pos="7:0" rst="148">
        <comment>
          point 6 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg174">
      <bits access="rw" name="ramp_curv17_p9" pos="15:8" rst="204">
        <comment>
          point 9 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_p8" pos="7:0" rst="188">
        <comment>
          point 8 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg175">
      <bits access="rw" name="ramp_curv17_pb" pos="15:8" rst="232">
        <comment>
          point 11 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_pa" pos="7:0" rst="220">
        <comment>
          point 10 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg176">
      <bits access="rw" name="ramp_curv17_pd" pos="15:8" rst="248">
        <comment>
          point 13 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_pc" pos="7:0" rst="240">
        <comment>
          point 12 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_ramp_reg177">
      <bits access="rw" name="ramp_curv17_pf" pos="15:8" rst="255">
        <comment>
          point 15 of PA ramp down curve11
        </comment>
      </bits>
      <bits access="rw" name="ramp_curv17_pe" pos="7:0" rst="252">
        <comment>
          point 14 of PA ramp down curve11
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="pa_on_h_reg">
      <bits access="r" name="pa_on_h_reg_reserved_0" pos="15:12" rst="0">
        <comment>
          reserved
        </comment>
      </bits>
      <bits access="rw" name="pa_on_h_dr_reg" pos="11" rst="0">
        <comment>
          pa_on_h direct value
        </comment>
      </bits>
      <bits access="rw" name="pa_on_h_dr_ctrl" pos="10" rst="0">
        <comment>
          pa_on_h direct control, active high
        </comment>
      </bits>
      <bits access="rw" name="ramp_dac_th" pos="9:0" rst="1023">
        <comment>
          ramp_dac threashold to assert pa_on_h
        </comment>
      </bits>
    </reg>
    <hole size="2016"/>
    <reg protect="rw" name="sys_ctrl_reg_20">
      <bits access="rw" name="sys_ctrl2_0" pos="15:0" rst="65535">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_ctrl_reg_22">
      <bits access="rw" name="sys_ctrl2_2" pos="15:0" rst="65535">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_ctrl_reg_24">
      <bits access="rw" name="sys_ctrl2_4" pos="15:0" rst="65535">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_ctrl_reg_26">
      <bits access="rw" name="sys_ctrl2_6" pos="15:0" rst="65535">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_ctrl_reg_28">
      <bits access="rw" name="sys_ctrl2_8" pos="15:0" rst="0">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_ctrl_reg_2a">
      <bits access="rw" name="sys_ctrl2_a" pos="15:0" rst="0">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_ctrl_reg_2c">
      <bits access="rw" name="sys_ctrl2_c" pos="15:0" rst="0">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="sys_ctrl_reg_2e">
      <bits access="rw" name="sys_ctrl2_e" pos="15:0" rst="0">
        <comment>
          for eco
        </comment>
      </bits>
    </reg>
  </module>
</archive>
<archive relative="rf_registers.xml">
</archive>
<archive relative = "rf_spi.xml">

    <var    name="CMD_FIFO_LEN_BITS" value="5"/>
    <var    name="CMD_FIFO_LEN" value="20"/> 
    <var    name="CMD_SIZE_BITS" value="8"/>
    
    <var    name="CMD_DATA_FIFO_LEN_BITS" value="4"/>
    <var    name="CMD_DATA_FIFO_LEN" value="exp2(CMD_DATA_FIFO_LEN_BITS)"/>
    
    <var    name="GAIN_TABLE_LEN_BITS" value="4"/>
    <var    name="GAIN_TABLE_LEN" value="15"/>  
    <var    name="GAIN_SIZE_BITS" value="4"/>

    <var    name="RX_DATA_FIFO_LEN_BITS" value="2"/>
    <var    name="RX_DATA_FIFO_LEN" value="exp2(RX_DATA_FIFO_LEN_BITS)"/>
    

<module name="rf_spi" category="Modem">

    <reg name="Ctrl" protect="rw">
        <bits name="Enable"         pos="0"     access="rw" rst="0">
            <comment>Enable the rf spi
                <br/>1 = Enable
                <br/>0 = Disable (will finish current command anyway)
            </comment>
        </bits>
        <bits name="CS_Polarity"    pos="1"     access="rw" rst="1">
            <comment>Chip select polarity
                <br/>1 = the chip select is active low
                <br/>0 = the chip select is active high
            </comment>
        </bits>
        <bits name="DigRF_Read"     pos="2"     access="rw" rst="1">
            <comment>DigRF Read style mode
                <br/>1 = DigRF Read style mode (read after CS disabled)
                <br/>0 = SPI Read mode (read during write)
            </comment>
        </bits>
        <bits name="Clocked_Back2Back"  pos="3" access="rw" rst="1">
            <comment>DigRF style clocked back to back mode
                <br/>1 = clocked back to back transfers using turnarround timing only when more data are present in the FIFO.
                <br/>0 = stop the clock between each access according to CS_End_Hold and CS_Pulse_Min timings
            </comment>
        </bits>
        <bits name="Input_Mode"     pos="4"     access="rw" rst="1">
            <comment>Input mode
                <br/>1 = Record input data to input FIFO
                <br/>0 = No input data
            </comment>
        </bits>
        <bits name="Clock_Polarity" pos="5"     access="rw" rst="1">
            <comment>SPI Clock polarity
                <br/>1 = the clock disabled level is high, and the first edge is a falling edge.
                <br/>0 = the clock disabled level is low, and the first edge is a rising edge.
            </comment>
        </bits>
        <bits name="Clock_Delay"    pos="7:6"   access="rw" rst="3">
            <comment>Transfer start to first edge delay
                <br/> value from 0 to 2 is the number of spi clock half period between the Transfer start and the first clock edge.
            </comment>
        </bits>
        <bits name="DO_Delay"       pos="9:8"   access="rw" rst="3">
            <comment>Transfer start to first data out delay
                <br/> value from 0 to 2 is the number of spi clock half period between the Transfer start and the first data out.
            </comment>
        </bits>
        <bits name="DI_Delay"       pos="11:10" access="rw" rst="3">
            <comment>Transfer start to first data in sampled delay
                <br/> value from 0 to 3 is the number of spi clock half period between the Transfer start and the first data sampled in.
                <br/> The DI_Delay only specify the sampling time, for frame size, the counter is based on the DO_Delay even in DigRF read mode.
            </comment>
        </bits>
        <bits name="CS_Delay"       pos="13:12" access="rw" rst="3">
            <comment>Transfer start to CS activation delay
                <br/> value from 0 to 3 is the number of spi clock half period between the Transfer start and the CS activation edge.
            </comment>
        </bits>
        <bits name="CS_End_Hold"    pos="15:14" access="rw" rst="3">
            <comment>Transfer end to chip select deactivation delay
                <br/> value from 0 to 3 is the number of spi clock half period between the end of transfer (DO) and the CS deactivation edge.
                <br/> <Strong>Not used for Clocked_Back2Back mode</Strong>
            </comment>
        </bits>
        <bits name="Frame_Size"     pos="20:16" access="rw" rst="31">
            <comment>Number of data in the frame, or number of out data in DigRF read mode.
                <br/>The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits)
                <br/>The frame size is given for the number of data, the actual number of clock pulses might be greater. First if Clock_Delay &lt; DO_Delay an extra clock pulse is generated, second in case of DigRF read or back2back, some more clock pulses will be generated.
            </comment>
            <options>
                <default/>
                <shift/>
                <mask/>
            </options>
        </bits>
        <bits name="CS_End_Pulse"   pos="23:22" access="rw" rst="3">
            <comment>Chip select deactivation to new start of transfer minimum delay
                <br/>value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new transfer start (transfer will start only if more data are available in the transmit FIFO)
                <br/> <Strong>Not used for Clocked_Back2Back mode</Strong>
            </comment>
        </bits>
        <bits name="Input_Frame_Size"   pos="28:24" access="rw" rst="31">
            <comment>Frame Size For Input in DigRF input mode
                <br/>The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits)
            </comment>
            <options>
                <default/>
                <shift/>
                <mask/>
            </options>
        </bits>
        <bits name="TurnAround_Time"    pos="31:30" access="rw" rst="3">
            <comment>TurnAround time: end of write frame to start of read frame delay (in cycles)
                <br/>value from 0 to 3 is the number of spi clock period between the end of the output frame (without the DO_Delay) and the Input Frame start.
                <br/>Also used for Clocked_Back2Back mode, when Clocked_Back2Back=1 and there is more data available in the transmit FIFO:
                <br/>value from 0 to 3 is the number of spi clock period between the end of the frame (without the DO_Delay) and the start of the new frame.
                (It can also be seen as the number of spi clock period between the end of the last data bit and the start of the new data bit.)
            </comment>
        </bits>
    </reg>
    <reg name="Status" protect="rw">
        <bits name="Active_Status"      pos="0"     access="r" rst="0">
            <comment>The SPI activity status
                <br/>1 = A transfer is in progress
                <br/>0 = The transfer is done
            </comment>
        </bits>
        <bits name="Error_Cmd"          pos="1"     access="rc" rst="0">
            <comment>Error status
                <br/>1 = a new command (or gain) has been requested while a command was in progress.
                <br/>0 = No error
                <br/>Write 1 to clear.
            </comment>
        </bits>
        <bits name="Table_Ovf"          pos="6"     access="rc" rst="0">
            <comment>The Gain Table overflow status.
                <br/>1 = Too many data has been written in the table
                <br/>Writing a 1 clear the overflow status.
            </comment>
        </bits>
        <bits name="Table_Udf"          pos="7"     access="rc" rst="0">
            <comment>The Gain Table underflow status.
                <br/> 1 = a next gain request has been received while the read pointer was already at the top of the table.
                <br/> Writing a '1' clear the underflow status.
            </comment>
        </bits>
        <bits name="Cmd_Level"          pos="CMD_FIFO_LEN_BITS+7:8" access="r" rst="0">
            <options>
                <mask/>
                <shift/>
            </options>
            <comment>Command FIFO level, number of command in the FIFO
            </comment>
        </bits>
        <bits name="Cmd_Ovf"            pos="14"    access="rc" rst="0">
            <comment>The command FIFO overflow status.
                <br/>1 = Too many data has been written in the FIFO
                <br/>Writing a 1 clear the overflow status.
            </comment>
        </bits>
        <bits name="Cmd_Udf"            pos="15"    access="rc" rst="0">
            <comment>The command FIFO underflow status.
                <br/>1 = Data has been requested to read while the FIFO was empty
                <br/>Writing a 1 clear the underflow status.
            </comment>
        </bits>
        <bits name="Cmd_Data_Level"     pos="CMD_DATA_FIFO_LEN_BITS+16:16"  access="r" rst="0">
            <options>
                <mask/>
                <shift/>
            </options>
            <comment>Command FIFO level, number of bytes in the FIFO
            </comment>
        </bits>
        <bits name="Cmd_Data_Ovf"       pos="22"    access="rc" rst="0">
            <comment>The command data FIFO overflow status.
                <br/>1 = Too many data has been written in the FIFO
                <br/>Writing a 1 clear the overflow status.
            </comment>
        </bits>
        <bits name="Cmd_Data_Udf"       pos="23"    access="rc" rst="0">
            <comment>The command data FIFO underflow status.
                <br/>1 = Data has been requested to read while the FIFO was empty
                <br/>Writing a 1 clear the underflow status.
            </comment>
        </bits>
        <bits name="Rx_Level"           pos="RX_DATA_FIFO_LEN_BITS+24:24"   access="r" rst="0">
            <options>
                <mask/>
                <shift/>
            </options>
            <comment>Receive FIFO level, number of bytes in the FIFO
            </comment>
        </bits>
        <bits name="Rx_Ovf"             pos="30"    access="rc" rst="0">
            <comment>The receive FIFO overflow status.
                <br/>1 = Too many data has been written in the FIFO
                <br/>Writing a 1 clear the overflow status.
            </comment>
        </bits>
        <bits name="Rx_Udf"             pos="31"    access="rc" rst="0">
            <comment>The receive FIFO underflow status.
                <br/>1 = Data has been requested to read while the FIFO was empty
                <br/>Writing a 1 clear the underflow status.
            </comment>
        </bits>
    </reg>
    <reg name="Rx_Data" protect="">
        <bits name="Rx_Data"    pos="7:0"   access="rw"  rst="no">
            <comment>Read in the receive FIFO
                <br/>Writing this register will write to Cmd_Data fifo (same as Cmd_Data register). This is because this address is used by the IFC channels to access the fifos.
            </comment>
        </bits>
    </reg>
    <reg name="Command" protect="w">
        <bits name="Send_Cmd"           pos="0"     access="w" rst="0">
            <comment> Writing 1 send the next command in the Cmd FIFO (This replace the TCU next cmd signal)
            </comment>
        </bits>
        <bits name="Flush_Cmd_FIFO"     pos="8"     access="w" rst="0">
            <comment>Writing 1 flush both Cmd, and cmd_data FIFO, <Strong>don't do it when SPI is active (transfer in progress)</Strong>
            </comment>
        </bits>
        <bits name="Flush_Rx_FIFO"      pos="16"    access="w" rst="0">
            <comment>Writing 1 flush the receive data FIFO, <Strong>don't do it when SPI is active (transfer in progress)</Strong>
            </comment>
        </bits>
        <bits name="Restart_Gain"       pos="24"    access="w" rst="0">
            <comment>Writing 1 place the read pointer at the beginning of the gain table. <Strong>don't do it when SPI is active (transfer in progress)</Strong>
            </comment>
        </bits>
        <bits name="Reload_Gain"        pos="28"    access="w" rst="0">
            <comment>Writing 1 place the write pointer at the beginning of the gain table allowing to fill the table.
            </comment>
        </bits>
        <bits name="Drive_Zero"         pos="31"    access="rw" rst="1">
            <comment>Writing 1 change all the ouputs of the SPI interface to drive a logical '0'. This mode stops when a new command is requested to be send (by TCU) or when writting 0 to this register. This mode is useful when powering off the tranciever chip connected to the RF_SPI.
            </comment>
        </bits>
    </reg>
    <reg name="Cmd_Size" protect="w">
        <bits name="Cmd_Size"    pos="CMD_SIZE_BITS-1:0"   access="w"  rst="no">
            <comment>Write the size in bytes of the next command in the FIFO
            </comment>
        </bits>
        <bits name="Cmd_Mark"   pos="31"    access="w"  rst="no">
            <comment>Write 1 to mark the command.
                <br/>Marked commands are discarded if Enable_Rf_Spi_Marked_Cmd is low in the tcu register.
            </comment>
        </bits>
    </reg>
    <reg name="Cmd_Data" protect="w">
        <bits name="Cmd_Data"    pos="7:0"   access="w"  rst="no">
            <comment>Write in the Command data FIFO
            </comment>
        </bits>
    </reg>
    <reg name="Gain_Size" protect="rw">
        <bits name="Gain_Size"   pos="GAIN_SIZE_BITS-1:0"   access="rw"  rst="0">
            <comment>Size of a Gain command in bytes.
            </comment>
        </bits>
    </reg>
    <reg name="Gain_Data" protect="w">
        <bits name="Gain_Data"   pos="7:0"   access="w"  rst="no">
            <comment>Write in the Gain Table (the pointer auto increments)
            </comment>
        </bits>
    </reg>
    <reg name="IRQ" protect="rw">
        <bits name="Cmd_Data_DMA_Done_Cause"    pos="0" access="rc" rst="0">
            <comment>Cmd_Data_DMA_Done IRQ Cause bit
                <br/> 1 = the IRQ was triggered by the end of the DMA transfer to the cmd FIFO.
                <br/> To clear it write 1 in this bit or Cmd_Data_DMA_Done_Status bit.
            </comment>
        </bits>
        <bits name="Cmd_FIFO_empty_Cause"       pos="2" access="r" rst="0">
            <comment>Cmd_FIFO_empty IRQ Cause bit
                <br/> 1 = the IRQ was triggered because the Cmd_FIFO is empty.
                <br/> To clear it, fill the FIFO.
            </comment>
        </bits>
        <bits name="Cmd_Threshold_Cause"        pos="3" access="r" rst="0">
            <comment>Cmd_Threshold IRQ Cause bit
                <br/> 1 = the IRQ was triggered because the Cmd_FIFO level is below the Cmd_Threshold.
                <br/> To clear it, fill the FIFO.
            </comment>
        </bits>
        <bits name="Rx_FIFO_full_Cause"         pos="4" access="r" rst="0">
            <comment>Rx_FIFO_full IRQ Cause bit
                <br/> 1 = the IRQ was triggered because the Rx_Data_FIFO is full.
                <br/> To clear it, read from the FIFO.
            </comment>
        </bits>
        <bits name="Rx_Threshold_Cause"         pos="5" access="r" rst="0">
            <comment>Rx_Threshold IRQ Cause bit
                <br/> 1 = the IRQ was triggered because the Rx_Data_FIFO level is over the Rx_Threshold.
                <br/> To clear it, read from the FIFO.
            </comment>
        </bits>
        <bits name="Error_Cause"                pos="6" access="r" rst="0">
            <comment>Error IRQ Cause bit
                <br/> 1 = the IRQ was triggered because an error occured. Read the Status register to check the kind of error.
                <br/> To clear it, clear it in the Status register.
            </comment>
        </bits>
        <bitgroup name="All_Cause">
            <entry ref="Cmd_Data_DMA_Done_Cause"/>
            <entry ref="Cmd_FIFO_empty_Cause"/>
            <entry ref="Cmd_Threshold_Cause"/>
            <entry ref="Rx_FIFO_full_Cause"/>
            <entry ref="Rx_Threshold_Cause"/>
            <entry ref="Error_Cause"/>
        </bitgroup>
        <bits name="Cmd_Data_DMA_Done_Status"   pos="16"    access="rc" rst="0">
            <comment>Cmd_Data_DMA_Done IRQ Status bit
                <br/> 1 = the end of the DMA transfer to the cmd FIFO occured.
                <br/> To clear it write 1 in this bit or Cmd_Data_DMA_Done_Cause bit.
            </comment>
        </bits>
        <bits name="Cmd_FIFO_empty_Status"      pos="18"    access="r" rst="1">
            <comment>Cmd_FIFO_empty IRQ Status bit
                <br/> 1 = the Cmd_FIFO is empty.
            </comment>
        </bits>
        <bits name="Cmd_Threshold_Status"       pos="19"    access="r" rst="1">
            <comment>Cmd_Threshold IRQ Status bit
                <br/> 1 = the Cmd_FIFO level is bellow the Cmd_Threshold.
            </comment>
        </bits>
        <bits name="Rx_FIFO_full_Status"        pos="20"    access="r" rst="0">
            <comment>Rx_FIFO_full IRQ Status bit
                <br/> 1 = the Rx_Data_FIFO is full.
            </comment>
        </bits>
        <bits name="Rx_Threshold_Status"        pos="21"    access="r" rst="0">
            <comment>Rx_Threshold IRQ Status bit
                <br/> 1 = the Rx_Data_FIFO level is over the Rx_Threshold.
            </comment>
        </bits>
        <bits name="Error_Status"               pos="22"    access="r" rst="0">
            <comment>Error IRQ Status bit
                <br/> 1 = an error occured. Read the Status register to check the kind of error.
            </comment>
        </bits>
        <bitgroup name="All_Status">
            <entry ref="Cmd_Data_DMA_Done_Status"/>
            <entry ref="Cmd_FIFO_empty_Status"/>
            <entry ref="Cmd_Threshold_Status"/>
            <entry ref="Rx_FIFO_full_Status"/>
            <entry ref="Rx_Threshold_Status"/>
            <entry ref="Error_Status"/>
        </bitgroup>
    </reg>
    <reg name="IRQ_Mask" protect="rw">
        <bits name="Cmd_Data_DMA_Done_Mask"     pos="0" access="rw" rst="0">
            <comment>Cmd_Data_DMA_Done IRQ Mask bit
                <br/> 1 = the Cmd_Data_DMA_Done IRQ is enabled
                <br/> 0 = the Cmd_Data_DMA_Done IRQ is disabled
            </comment>
        </bits>
        <bits name="Cmd_FIFO_empty_Mask"        pos="2" access="rw" rst="0">
            <comment>Cmd_FIFO_empty IRQ Mask bit
                <br/> 1 = the Cmd_FIFO_empty IRQ is enabled
                <br/> 0 = the Cmd_FIFO_empty IRQ is disabled
            </comment>
        </bits>
        <bits name="Cmd_Threshold_Mask"         pos="3" access="rw" rst="0">
            <comment>Cmd_Threshold IRQ Mask bit
                <br/> 1 = the Cmd_Threshold IRQ is enabled
                <br/> 0 = the Cmd_Threshold IRQ is disabled
            </comment>
        </bits>
        <bits name="Rx_FIFO_full_Mask"          pos="4" access="rw" rst="0">
            <comment>Rx_FIFO_full IRQ Mask bit
                <br/> 1 = the Rx_FIFO_full IRQ is enabled
                <br/> 0 = the Rx_FIFO_full IRQ is disabled
            </comment>
        </bits>
        <bits name="Rx_Threshold_Mask"          pos="5" access="rw" rst="0">
            <comment>Rx_Threshold IRQ Mask bit
                <br/> 1 = the Rx_Threshold IRQ is enabled
                <br/> 0 = the Rx_Threshold IRQ is disabled
            </comment>
        </bits>
        <bits name="Error_Mask"                 pos="6" access="rw" rst="0">
            <comment>Error IRQ Mask bit
                <br/> 1 = the Error IRQ is enabled
                <br/> 0 = the Error IRQ is disabled
            </comment>
        </bits>
        <bitgroup name="All_Mask">
            <entry ref="Cmd_Data_DMA_Done_Mask"/>
            <entry ref="Cmd_FIFO_empty_Mask"/>
            <entry ref="Cmd_Threshold_Mask"/>
            <entry ref="Rx_FIFO_full_Mask"/>
            <entry ref="Rx_Threshold_Mask"/>
            <entry ref="Error_Mask"/>
        </bitgroup>
    </reg>
    <reg name="IRQ_Threshold" protect="rw">
        <bits name="Cmd_Threshold"      pos="CMD_FIFO_LEN_BITS+7:8" access="r" rst="all1">
            <comment>Command FIFO Threshold, number of command in the FIFO bellow which the Cmd_Threshold_IRQ is triggered.
            </comment>
        </bits>
        <bits name="Rx_Threshold"       pos="RX_DATA_FIFO_LEN_BITS+23:24"   access="r" rst="all1">
            <comment>Receive FIFO Threshold, number of bytes in the FIFO above which the Rx_Threshold_IRQ is triggered.
            </comment>
        </bits>
    </reg>
    <reg name="Divider" protect="rw">
        <bits name="Divider"    pos="6:1"   access="rw" rst="0">
            <comment>Clock Divider
                <br/>The state machine clock is generated by dividing the system clock by the value of this register + 1. So the output clock is divided by (register + 1)*2
            </comment>
            <options><mask/><shift/></options>
        </bits>
        <bits name="Clock_Limiter" pos="28" access="rw" rst="0">
            <comment>When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz.
                <br/> for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
    </reg>
</module>
</archive>
<archive relative = "rffe.xml">

<module name="rf_dig_rffe" category="RF_Dig">

    <reg name="CMD_MIPI0" protect="rw">
        <bits name="cmd_mipi_low" pos="15:0" access="rw" rst="0">
            <comment>cmd_mipi_sr[15:0]
            </comment>
        </bits>
    </reg>

    <reg name="CMD_MIPI1" protect="rw">
        <bits name="cmd_mipi_high" pos="15:0" access="rw" rst="0">
            <comment>cmd_mipi_sr[31:16]
            </comment>
        </bits>
    </reg>

    <reg name="DATA_MIPI0" protect="rw">
        <bits name="data_mipi_low" pos="15:0" access="rw" rst="0">
            <comment>data_mipi_sr[15:0]
            </comment>
        </bits>
    </reg>
 
    <reg name="DATA_MIPI1" protect="rw">
        <bits name="data_mipi_high" pos="15:0" access="rw" rst="0">
            <comment>data_mipi_sr[31:16]
            </comment>
        </bits>
    </reg>
 
    <reg name="DATA_OUT0" protect="rw">
        <bits name="data_out_low" pos="15:0" access="rw" rst="0">
            <comment>data_out[15:0]
            </comment>
        </bits>
    </reg>
 
    <reg name="DATA_OUT1" protect="rw">
        <bits name="data_out_high" pos="15:0" access="rw" rst="0">
            <comment>data_out[31:16]
            </comment>
        </bits>
    </reg>
 
    <reg name="DATA_VALID" protect="rw">
        <bits name="data_out_high" pos="3:0" access="rw" rst="0">
            <comment>data_valid byte[3:0]
            </comment>
        </bits>
    </reg>
 
</module>

</archive>
<archive relative = "sci.xml">
<module name="sci" category="Modem">
    <reg name="Config" protect="rw">
        <bits name="Enable" pos="0" access="rw" rst="0">
            <comment>Enables the SIM Card IF module
            </comment>
        </bits>
        <bits name="Parity" pos="1" access="rw" rst="0">
            <comment>Selects the parity generation/detection
            </comment>
            <options>
                <option value="0" name="Even_parity"/>
                <option value="1" name="Odd_parity"/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="PERF" pos="2" access="rw" rst="0">
            <comment>Parity Error Receive Feed-through
                <br/>0 = Don't store bytes with detected parity errors
                <br/>1 = Feed-through bytes with detected parity errors
            </comment>
        </bits>
        <bits name="Filter_Disable" pos="3" access="rw" rst="0">
            <comment>Enable or disable NULL (0x60) character filtering when SIM card sends NULL to reset WWT timer.
                <br/>0 = Enable NULL character filtering, NULL characters are not reported if not data.
                <br/>1 = Disable NULL character filtering.  NULL characters (0x60) are transferred to the SCI data buffer.
            </comment>
        </bits>
        <bits name="ClockStop" pos="4" access="rw" rst="1">
            <comment>Manual SCI Clock Stop control.  Manually starts and stops the SCI clock.  This bit must be set to '1' when Autostop mode is enabled.
                <br/>0 = Enable the SCI clock
                <br/>1 = Disable SCI clock
            </comment>
        </bits>
        <bits name="AutoStop_En_H" pos="5" access="rw" rst="0">
            <comment>Enables automatic clock shutdown when command is complete.  Enabling this will generate the necessary startup and shutdown delays required by the SIM protocol.
                <br/>0 = Auto clock control not enabled.  SCI clock controlled by SCI_Clockstop bit
                <br/>1 = Auto clock control enabled.
            </comment>
        </bits>
        <bits name="MSBH_LSBL" pos="6" access="rw" rst="1">
            <comment>Sets the transmission and reception bit order:
                <br/>0 = LSB is sent/recieved first (Direct convention)
                <br/>1 = MSB is sent/received first (Inverse convention)
            </comment>
        </bits>
        <bits name="LLI" pos="7" access="rw" rst="1">
            <comment>Logic Level Invert:
                <br/>0 = Logic level 0 data is sent/received as '0' or 'A' which is the same as the start bit.  (Direct convention)
                <br/>1 = Logic level 0 data is sent/received as '1' or 'Z' which is the opposite of the start bit.  (Inverse convention)
            </comment>
        </bits>
        <bits name="PEGen_Len" pos="8" access="rw" rst="0">
            <comment>Parity Error signal length.  This configuration bit can be used to extend the duration of the parity error signal generation from 1 ETU to 1.5 ETU
                <br/>0 = Parity Error signal duration is 1 ETU starting at 10.5 ETU
                <br/>1 = Parity Error signal duration is 1.5 ETU starting at 10.5 ETU
            </comment>
        </bits>
        <bits name="Parity_En" pos="9" access="rw" rst="0">
            <comment>Enable or disable parity error checking on the receive data
                <br/>0 = Disable parity error checking
                <br/>1 = Enable parity error checking
            </comment>
        </bits>
        <bits name="Stop_Level" pos="10" access="rw" rst="1">
            <comment>Logical value of the clock signal when SCI clock is stopped (either due to automatic shutdown or manual shutdown)
                <br/>0 = Stop clock at low level
                <br/>1 = Stop clock at high level
            </comment>
        </bits>
        <bits name="Rx_Clk_Cnt_Sample " pos="15:11" access="rw" rst="1">
            <comment> tunning the sample local.
            </comment>
        </bits>
        <bits name="ARG_H" pos="16" access="rw" rst="0">
            <comment>Automatic Reset Generator.  Write a '1' to this bit to initiate an automatic reset procedure on the SIM.  Write '0' to switch back to SCI_Reset control (bit 20).  An ARG interrupt will be generated if the ARG process succeeded or failed.  The ARG status bit (ARG_Det) must be read to determine if a reset response from the card was detected.  This bit needs to be cleared between ARG attempts.
            </comment>
        </bits>
        <bits name="AFD_En_H" pos="17" access="rw" rst="0">
            <comment>Automatic format detection.  This bit is generally set in conjunction with the ARG_H bit to enable automatic detection of the data convention.
                <br/>1 = Enable TS detection and automatic convention settings programming
                <br/>0 = disable automatic settings and use the register bits (MSBH_LSBL and LLI) to control the convention
            </comment>
        </bits>
        <bits name="Tx_Resend_En_H" pos="18" access="rw" rst="1">
            <comment>1 = Enable automatic resend of characters when Tx parity error is detected
                <br/>0 = Disable automatic resend
            </comment>
        </bits>
        <bits name="IO_data_l" pos="19" access="rw" rst="0">
            <comment>1 = pulldown
                <br/>0 = pullup
            </comment>
        </bits>
        <bits name="Reset" pos="20" access="rw" rst="0">
            <comment>Direct connection to the SIM card reset pin.  This is overridden when ARG_H is enabled
                <br/>0 = SCI_Reset low voltage
                <br/>1 = SCI Reset high voltage
            </comment>
        </bits>
        <bits name="Dly_Sel" pos="21" access="rw" rst="0">
            <comment>This selects between two delay times for the automatic clock stop startup and shutdown:
                <br/>0 = short delay
                <br/>Startup/Shutdown : 744 SCI clocks / 1860 SCI clocks
                <br/>1 = long delay
                <br/>Startup/Shutdown : (2 x 744) SCI clocks / (2 x 1860) SCI clocks
            </comment>
        </bits>
        <bits name="In_avg_en" pos="22" access="rw" rst="1">
            <comment>Input data average enable.
                <br/>0 = Disable
                <br/>1 = Enable
            </comment>
        </bits>
        <bits name="Par_Chk_Offset" pos="29:24" access="rw" rst="0xe">
            <comment>Allows fine control of the parity check position during the parity error time period.
            </comment>
        </bits>
        <bits name="Sci_Mode" pos="31:30" access="rw" rst="0">
            <comment>These bits are reserved and must be written as '00' for the SCI module to work properly:
                <br/>"11" = Ser In &lt;- Ser Out loopback
                <br/>"10" = Ser In &lt;- Ser In (unmasked)
                <br/>others = Ser In &lt;- Ser In masked with Txing_H (normal mode)
            </comment>
        </bits>
    </reg>
    <reg name="Status" protect="r">
        <bits name="RxData_Rdy" pos="0" access="r" rst="0">
            <comment>Returns the status of the Rx FIFO:
                <br/>0 = Rx FIFO empty
                <br/>1 = There is at least 1 character in the Rx FIFO
            </comment>
        </bits>
        <bits name="Tx_FIFO_Rdy" pos="1" access="r" rst="1">
            <comment>Returns the status of the Tx FIFO:
                <br/>0 = Tx FIFO is full
                <br/>1 = There is at least 1 free spot in the Tx FIFO
            </comment>
        </bits>
        <bits name="Format_Det" pos="2" access="r" rst="0">
            <comment>Returns the status of the automatic format detection after reset:
                <br/>0 = TS character has not been detected in the ATR
                <br/>1 = TS character has been detected and SCI module is using the automatic convention settings
                <br/>
                <br/>This bit is cleared when the AFD_En bit is cleared
            </comment>
        </bits>
        <bits name="ARG_Det" pos="3" access="r" rst="0">
            <comment>Returns the status of the automatic reset procedure:
                <br/>0 = ARG detection has failed
                <br/>1 = ARG detection has detected that the SIM has responded to the reset
                <br/>
                <br/>This bit is used in conjunction with the ARG interrupt.  The ARG interrupt will be generated at the successful or unsuccessful termination of the ARG process.  This bit can be used to determine the success or failure.
            </comment>
        </bits>
        <bits name="Reset_Det" pos="4" access="r" rst="0">
            <comment>This is the status of the Reset pin when automatic reset generation is enabled.  This bit can be used to discover whether the SIM card that has successfully responded to an ARG procedure has an active high or active low reset. (Det means 'Detection')
            </comment>
        </bits>
        <bits name="Clk_Rdy_H" pos="5" access="r" rst="0">
            <comment>Status of the control signal to the clock control module.  This bit respects the startup and shutdown phases, so during these times, the clock may actually be on, but it is not considered to be 'ready'
                <br/>0 = SCI clock may be on or off but is not ready for use
                <br/>1 = SCI clock is on and ready for use
            </comment>
        </bits>
        <bits name="Clk_Off" pos="6" access="r" rst="1">
            <comment>Status bit of the Sci clock. 
                <br/>0 = Sci clock is ON
                <br/>1 = Sci clock is OFF
            </comment>
        </bits>
        <bits name="Rx_Err" pos="8" access="r" rst="0">
            <comment>A receive parity error was detected. Reading this register clears the bit.
            </comment>
        </bits>
        <bits name="Tx_Err" pos="9" access="r" rst="0">
            <comment>A transmit parity error was detected. Reading this register clears the bit.
            </comment>
        </bits>
        <bits name="RxOverflow" pos="10" access="r" rst="0">
            <comment>The internal receive FIFO has reached an overflow condition. Reading this register clears the bit.
            </comment>
        </bits> 
        <bits name="TxOverflow" pos="11" access="r" rst="0">
            <comment>The internal transmit FIFO has reached an overflow condition. Reading this register clears the bit.
            </comment>
        </bits>
        <bits name="AutoStop_State" pos="31:30" access="r" rst="0">
            <comment>Returns the state of the clock management state machine when AutoStop mode is enabled.  This value is '00' when manual mode is selected.
            </comment>
            <options>
                <option value="0" name="Startup_phase"><comment>Clock is on, but not ready to be used.</comment></option>
                <option value="1" name="Auto_on"><comment>Clock is on and ready to be used</comment></option>
                <option value="2" name="Shutdown_phase"><comment>Clock is still on, but should not be used.</comment></option>
                <option value="3" name="Clock_off"><comment>Clock is off.</comment></option>
                <mask/>
                <shift/>
            </options>
        </bits>
    </reg>
    <reg name="Data" protect="--">
        <bits name="Data_IN" pos="7:0" access="w" rst="0">
            <comment>Writing to this register will send the data to the SIM card. If automatic clock shutdown is enabled, the appropriate delay will be applied before the data is actually sent. 
            </comment>
        </bits>
        <bits name="Data_OUT" pos="7:0" access="r" rst="0">
            <comment>Reading this register will read from the receive data FIFO.
            </comment>
        </bits>
    </reg>
    <reg name="ClkDiv" protect="rw">
        <bits name="ClkDiv" pos="8:0" access="rw" rst="0x174">
            <comment>Clock divider for generating the baud clock from the SCI clock.  This value must match the value used by the SIM card whose default value is 0x174.
            </comment>
        </bits>
        <bits name="Baud_x8_En" pos="9" access="rw" rst="0">
            <comment>Speed mode enable.
                <br/>0 = Low speed mode
                <br/>1 = High speed mode(372/32, 372/64, 512/64)
            </comment>
        </bits>
        <bits name="Rx_Clk_Cnt_Limit" pos="14:10" access="rw" rst="0x10">
            <comment>Rx_clk_cnt wrap value.
            </comment>
         </bits>
        <bits name="Clk_Tst" pos="15" access="rw" rst="0">
          </bits>
        <bits name="ClkDiv_16" pos="23:16" access="rw" rst="0x18">
            <comment>Secondary clock divider for generating 16x baud clock.
            </comment>
        </bits>
        <bits name="MainDiv" pos="29:24" access="rw" rst="0x4">
            <comment>Main clock divider to generate the SCI clock.  This value should be calculated as follows:
                <br/>MainDiv = Clk_Sys/(2xSCI_Clk) - 1
                <br/>where SCI_Clk is in the range of 3-5 MHz as specified in the SIM specification.
            </comment>
            <options><mask/><default/></options>
        </bits>
        <bits name="Clk_Out_Inv" pos="30" access="rw" rst="0">
            <comment>Inverts the polarity of the SCI clock to the SIM card only.
                <br/>0 = No inversion
                <br/>1 = Invert external SCI clock
            </comment>
        </bits>
        <bits name="Clk_Inv" pos="31" access="rw" rst="0">
            <comment>Inverts  SCI clock to the SIM card .
                <br/>0 = No inversion
                <br/>1 = Invert external SCI clock
            </comment>
        </bits>
    </reg>
    <reg name="RxCnt" protect="rw">
        <bits name="RxCnt" pos="9:0" access="rw" rst="0">
            <comment>This value should be programmed with the number of expected characters to receive.  It will be decremented each time a character is <strong>actually</strong> received and should be 0 when the transfer is complete.  If a character is sent after the RxCnt reaches zero, the extra character flag will be set but this value will stay at zero.
            </comment>
        </bits>
        <bits name="Clk_Persist" pos="31" access="rw" rst="0">
            <comment>When in automatic clock shutdown mode, this bit can prevent the clock from entering shutdown mode when the transfer is complete.  This should be used for multi-transfer commands where the clock must not be shut down until the command is complete.  This bit must be programmed for each transfer.
                <br/>1 = Keep clock on
                <br/>0 = Allow clock shutdown when transfer is complete
            </comment>
        </bits>
    </reg>
    <reg name="Times" protect="rw">
        <bits name="ChGuard" pos="7:0" access="rw" rst="1">
            <comment>This is the extra guard time that can be added to the 2 ETU minimum (and default) guard time between successive transmitted characters.  This should be programmed depending on the SIM's ATR.  The total ETU guard time will be ChGuard + 1.
            </comment>
            <options>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="TurnaroundGuard" pos="11:8" access="rw" rst="0x6">
            <comment>Turnaround guard time configuration.  This value can be used to adjust the delay between the leading edge of a received character and the leading edge of the next transmitted character.  The minimum time specified in the SIM recommendation is 16 ETU.  The number of ETUs can be calculated using the following formula:
                <br/>Total Turnaround Time (in ETUs) = 11 + TurnaroundGuard
            </comment>
            <options>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="WI" pos="23:16" access="rw" rst="0x0A">
            <comment>Work Waiting Time factor.  A timeout will be generated when the WWT is exceeded.  The WWT is calculated by:
                <br/>       WWT = 960 x WI x (F/Fi)
                <br/>where Fi is the main SCI clock frequency (3-5 MHz) and F is 372 before an enhanced PPS and 512 after an enhanced PPS.
                <br/>The SCI_WI value must be calculated as follows:
                <br/>       SCI_WI = WI * D
                <br/>Thus, by default (WI = 10) this value needs to be set to 10 before an EPPS, but needs to be scaled to WI*D=80 after the EPPS procedure.
            
            </comment>
            <options>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="Tx_PERT" pos="31:24" access="rw" rst="0xFF">
            <comment>Number of times to try resending character when the SIM indicates a parity error.
            </comment>
        </bits>
    </reg>  
    <reg name="Ch_Filt" protect="rw">
        <bits name="Ch_Filt" pos="7:0" access="rw" rst="0x60">
            <comment>Value of the character to be filtered.  0x60 is the NULL character in the SIM protocol.  If character filtering is enabled, the <strong>first</strong> 0x60 character that is received by the SIM during a transfer will <strong>not</strong> be recorded.  The purpose of this character is to enable the SIM to reset the WWT counter when the SIM is not ready to send the data.  This filter has no effect on characters within the datastream.
            </comment>
        </bits>
    </reg>  
    
    <reg name="dbg" protect="w">
        <bits name="FIFO_RX_Clr" pos="0" access="w" rst="0">
            <comment>Clear RX FIFO.
            </comment>
        </bits>     
        <bits name="FIFO_TX_Clr" pos="1" access="w" rst="0">
            <comment>Clear TX FIFO.
            </comment>
        </bits>     
        <comment>UNDOCUMENTED FEATURE</comment>
    </reg>  
    <reg name="Int_Cause" protect="r">
        <bits name="Rx_Done" pos="0" access="r" rst="0">
            <comment>Number of expected Rx characters, as programmed in the RxCnt register, has been received.
            </comment>
        </bits>
        <bits name="Rx_Half" pos="1" access="r" rst="0">
            <comment>Receiver FIFO is half full.
            </comment>
        </bits>
        <bits name="WWT_Timeout" pos="2" access="r" rst="0">
            <comment>No Tx character has been sent NOR any Rx character detected within the WWT timeout.
            </comment>
        </bits>
        <bits name="Extra_Rx" pos="3" access="r" rst="0">
            <comment>An extra character has been received after the number of characters in RxCnt has been received.
            </comment>
        </bits>
        <bits name="Resend_Ovfl" pos="4" access="r" rst="0">
            <comment>The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field.
            </comment>
        </bits>     
        <bits name="ARG_End" pos="5" access="r" rst="0">
            <comment>End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not.
            </comment>
        </bits>     
        <bits name="Sci_DMA_Tx_Done" pos="6" access="r" rst="0">
            <comment>DMA tx done.
            </comment>
        </bits>     
        <bits name="Sci_DMA_Rx_Done" pos="7" access="r" rst="0">
            <comment>DMA rx done.
            </comment>
        </bits>     
        <comment>
            This register is a <b>READ ONLY</b> register that returns the logical <b>and</b> of the SCI_INT_STATUS register and the SCI_INT_MASK. If any of these bits is '1', the SCI module will generate an interrupt.  Bits 21:16 return the <u>status</u> of the interrupt which is the interrupt state before the mask is applied.  These bits should only be used for debugging.
        </comment>
    </reg>  
    <reg name="Int_Clr" protect="rw">
        <bits name="Rx_Done" pos="0" access="c" rst="0">
            <comment>Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received.
            </comment>
        </bits>
        <bits name="Rx_Half" pos="1" access="c" rst="0">
            <comment>Receiver FIFO is half full.
            </comment>
        </bits>
        <bits name="WWT_Timeout" pos="2" access="c" rst="0">
            <comment>No Tx character has been sent NOR any Rx character detected within the WWT timeout.
            </comment>
        </bits>
        <bits name="Extra_Rx" pos="3" access="c" rst="0">
            <comment>An extra character has been received after the number of characters in SCI_RxCnt has been received.
            </comment>
        </bits>
        <bits name="Resend_Ovfl" pos="4" access="c" rst="0">
            <comment>The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field.
            </comment>
        </bits>     
        <bits name="ARG_End" pos="5" access="c" rst="0">
            <comment>End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not.
            </comment>
        </bits>     
        <bits name="Sci_DMA_Tx_Done" pos="6" access="c" rst="0">
            <comment>DMA tx done.
            </comment>
        </bits>     
        <bits name="Sci_DMA_Rx_Done" pos="7" access="c" rst="0">
            <comment>DMA rx done.
            </comment>
        </bits>     
        <comment>
            This is a WRITE ONLY register that is used to clear an SCI interrupt. Write a '1' to the interrupt that is to be cleared. Writing '0' has no effect.
        </comment>
    </reg>  
    <reg name="Int_Mask" protect="rw">
        <bits name="Rx_Done" pos="0" access="rw" rst="0">
            <comment>Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received.
            </comment>
        </bits>
        <bits name="Rx_Half" pos="1" access="rw" rst="0">
            <comment>Receiver FIFO is half full.
            </comment>
        </bits>
        <bits name="WWT_Timeout" pos="2" access="rw" rst="0">
            <comment>No Tx character has been sent NOR any Rx character detected within the WWT timeout.
            </comment>
        </bits>
        <bits name="Extra_Rx" pos="3" access="rw" rst="0">
            <comment>An extra character has been received after the number of characters in SCI_RxCnt has been received.
            </comment>
        </bits>
        <bits name="Resend_Ovfl" pos="4" access="rw" rst="0">
            <comment>The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field.
            </comment>
        </bits>     
        <bits name="ARG_End" pos="5" access="rw" rst="0">
            <comment>End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not.
            </comment>
        </bits>  
        <bits name="Sci_DMA_Tx_Done" pos="6" access="rw" rst="0">
            <comment>DMA tx done.
            </comment>
        </bits>     
        <bits name="Sci_DMA_Rx_Done" pos="7" access="rw" rst="0">
            <comment>DMA rx done.
            </comment>
        </bits>     
        <comment>
            This register is READ/WRITE register that enables the desired interrupt. A '1' in a bit position indicates that the corresponding interrupt is enabled and if the interrupt occurs, the SCI will generate a hardware interrupt.
        </comment>
    </reg>  
    <reg name="PA_CLK_STOP_EN" protect="rw">
        <bits name="PA_CLK_STOP_EN" pos="0" access="rw" rst="0">
            <comment>Set this bit to 1'b0, then when pa_en = 1,sci stops work.
            </comment>
        </bits>
    </reg>
</module>
</archive>
<archive relative = "sdmmc.xml">

<module name="sdmmc" category="Periph">


    <reg name="apbi_ctrl_sdmmc" protect="rw">
       <bits name="L_Endian"  pos="2:0" access="rw" rst="000">
          <comment>Controls the big endian or little endian of the FIFO data.
              <br/>Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0.
              <br/>"000": the order is not changed.
                <br/>Byte3="0A",Byte2="0B",Byte1="0C",Byte0="0D".
              <br/>"001": reversed on byte.
                <br/>Byte3="0D",Byte2="0C,Byte1="0B",Byte0="0A".
              <br/>"010": reversed on half word.
                <br/>Byte3="0C",Byte2="0D,Byte1="0A",Byte0="0B".
              <br/>"010": reversed on bit.
                <br/>Byte3="B0",Byte2="30,Byte1="D0",Byte0="50".
              <br/>"100": reversed on bit.
                <br/>Byte3="0A",Byte2="0X,Byte1="0D",Byte0="0C".
          </comment>
       </bits> 
       <bits name="Soft_rst_L" pos="3" access="rw" rst="1">
          <comment>For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind.
              <br/>Active Low.
          </comment>
       </bits>
     </reg>

     <hole size="32"/>

     <reg name="APBI_FIFO_TxRx"  protect="--">   
         <bits name="DATA_IN" pos="31:0" access="w" rst="0">
           <comment>Write to the transmit FIFO
           </comment>
         </bits>
         <bits name="DATA_OUT" pos="31:0" access="r" rst="0">
           <comment>Read in the receive FIFO
           </comment>
         </bits>
     </reg>



<hole size="16288"/>

<reg protect="rw" name="SDMMC_CONFIG">

	<bits access="rw" name="SDMMC_SENDCMD" pos="0" rst="0">
		<comment>SD/MMC operation begin register, active high.<br /> 
		When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'.
		</comment>
	</bits>
	
	<bits access="rw" name="SDMMC_SUSPEND" pos="1" rst="1">
		<comment>SD/MMC operation suspend register, active high.
		</comment>
	</bits>
	
	<bits access="rw" name="RSP_EN" pos="4" rst="0">
		<comment>'1'indicates having a response,'0'indicates no response.
		</comment>
	</bits>
	
    <bits access="rw" name="RSP_SEL" pos="6:5" rst="0">
        <options>
            <default/>
            <option name="R2" value="0b10"/>
            <option name="R3" value="0b01"/>
            <option name="OTHER" value="0b00"/>
        </options>
		<comment>Response select register,"10" means R2 response, "01" means R3 response, "00" means others response, "11" is reserved.
		</comment> 
	</bits>
	
    <bits access="rw" name="RD_WT_EN" pos="8" rst="0">
		<comment>'1' indicates data operation, which includes read and write.
		</comment>
	</bits>
	
	<bits access="rw" name="RD_WT_SEL" pos="9" rst="0">
        <options>
            <default/>
            <option name="READ" value="0"/>
            <option name="WRITE" value="1"/>
        </options>
		<comment>'1' means write operation,'0' means read operation.
		</comment>
	</bits>
	
	<bits access="rw" name="S_M_SEL" pos="10" rst="0">
        <options>
            <default/>
            <option name="SIMPLE"   value="0"/>
            <option name="MULTIPLE" value="1"/>
        </options>
		<comment>'1'means multiple block data operation.
		</comment>
	</bits>
	<bits access="rw" name="AUTO_FLAG_EN" pos="16" rst="1">
	</bits>
	
</reg>
	
<reg protect="r" name="SDMMC_STATUS">

	<bits access="r" name="Not_SDMMC_OVER" pos="0" rst="0">
		<comment>'1' means the SD/MMC operation is not over.
		</comment>
	</bits>
		
	<bits access="r" name="BUSY" pos="1" rst="0">
		<comment>'1' means SD/MMC is busy.
		</comment>
	</bits>	

	<bits access="r" name="DL_BUSY" pos="2" rst="0">
		<comment>'1' means the data line is busy.
		</comment>
	</bits>
	
	<bits access="r" name="SUSPEND" pos="3" rst="1">
		<comment>'1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'.
		</comment>
	</bits>

	
	
		

	<bits access="r" name="RSP_ERROR" pos="8" rst="0">
		<comment>Response CRC checks error register '1' means response CRC check error.
		</comment>
	</bits>
	
	<bits access="r" name="NO_RSP_ERROR" pos="9" rst="0">
		<comment>'1' means the card has no response to command. 
		</comment>
	</bits>
	
	<bits access="r" name="CRC_STATUS" pos="14:12" rst="0">
		<comment>CRC check for SD/MMC write operation <br /> 
		"101" transmission error<br />
		"010" transmission right<br />
		"111" flash programming error
		</comment>
	</bits>
	
	<bits access="r" name="DATA_ERROR" pos="23:16" rst="0">
		<comment>8 bits data CRC check, "00000000" means no data error, "00000001" means DATA0 CRC check error, "10000000" means DATA7 CRC check error, each bit match one data line.
		</comment>
	</bits>

	<bits access="r" name="DAT3_VAL" pos="24" rst="-">
		<comment>SDMMC DATA 3 value.
		</comment>
	</bits>
	
</reg>

<reg protect="rw" name="SDMMC_CMD_INDEX">

	<bits access="rw" name="COMMAND" pos="5:0" rst="0">
		<comment>SD/MMC command register.
		</comment>
	</bits>

</reg>

<reg protect="rw" name="SDMMC_CMD_ARG">

	<bits access="rw" name="ARGUMENT" pos="31:0" rst="0">
		<comment>SD/MMC command argument register, write data to the SD/MMC card.
		</comment>
	</bits>

</reg>

<reg protect="r" name="SDMMC_RESP_INDEX">

	<bits access="r" name="RESPONSE" pos="5:0" rst="0">
		<comment>SD/MMC response index register.
		</comment>
	</bits>

</reg>

<reg protect="r" name="SDMMC_RESP_ARG3">

	<bits access="r" name="ARGUMENT3" pos="31:0" rst="0">
		<comment>Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2.
		</comment>
	</bits>

</reg>

<reg protect="r" name="SDMMC_RESP_ARG2">

	<bits access="r" name="ARGUMENT2" pos="31:0" rst="0">
		<comment>95 to 64 bit response argument of R2.
		</comment>
	</bits>

</reg>

<reg protect="r" name="SDMMC_RESP_ARG1">

	<bits access="r" name="ARGUMENT1" pos="31:0" rst="0">
		<comment>63 to 32 bit response argument of R2.
		</comment>
	</bits>

</reg>

<reg protect="r" name="SDMMC_RESP_ARG0">

	<bits access="r" name="ARGUMENT0" pos="31:0" rst="0">
		<comment>31 to 0 bit response argument of R2.
		</comment>
	</bits>

</reg>

<reg protect="rw" name="SDMMC_DATA_WIDTH">

	<bits access="rw" name="SDMMC_DATA_WIDTH" pos="3:0" rst="0">
		<comment>SD/MMC data width:<br />
		0x1: 1 data line<br />
		0x2: 2 reserved<br />
		0x4: 4 data lines<br />
		0x8: 8 data lines
		</comment>
	</bits>

</reg>

<reg protect="rw" name="SDMMC_BLOCK_SIZE">

	<bits access="rw" name="SDMMC_BLOCK_SIZE" pos="3:0" rst="0">
		<comment>SD/MMC size of one block:<br />
		0-1:reserved<br />
		2: 1 word<br />
		3: 2 words<br />
		4: 4 words<br />
		5: 8 words<br />
		6: 16 words<br />
 		       <br />
		11: 512 words<br />
		12-15 reserved
		</comment>
	</bits>

</reg>

<reg protect="rw" name="SDMMC_BLOCK_CNT">

	<bits access="rw" name="SDMMC_BLOCK_CNT" pos="15:0" rst="0">
		<comment>Block number that wants to transfer.
		</comment>
	</bits>

</reg>

<reg protect="r" name="SDMMC_INT_STATUS">

	<bits access="r" name="NO_RSP_INT" pos="0" rst="0">
		<comment>'1' means no response.
		</comment>
	</bits>

	<bits access="r" name="RSP_ERR_INT" pos="1" rst="0">
		<comment>'1' means CRC error of response.
		</comment>
	</bits>
	
	<bits access="r" name="RD_ERR_INT" pos="2" rst="0">
		<comment>'1' means CRC error of reading data.
		</comment>
	</bits>

	<bits access="r" name="WR_ERR_INT" pos="3" rst="0">
		<comment>'1' means CRC error of writing data.
		</comment>
	</bits>

	<bits access="r" name="DAT_OVER_INT" pos="4" rst="0">
		<comment>'1' means data transmission is over.
		</comment>
	</bits>

	<bits access="r" name="TXDMA_DONE_INT" pos="5" rst="0">
		<comment>'1' means tx dma done.
		</comment>
	</bits>

	<bits access="r" name="RXDMA_DONE_INT" pos="6" rst="0">
		<comment>'1' means rx dma done.
		</comment>
	</bits>
	
	<bits access="r" name="NO_RSP_SC" pos="8" rst="0">
		<comment>'1' means no response is the source of interrupt.
		</comment>
	</bits>

	<bits access="r" name="RSP_ERR_SC" pos="9" rst="0">
		<comment>'1' means CRC error of response is the source of interrupt.
		</comment>
	</bits>
	
	<bits access="r" name="RD_ERR_SC" pos="10" rst="0">
		<comment>'1' means CRC error of reading data is the source of interrupt.
		</comment>
	</bits>

	<bits access="r" name="WR_ERR_SC" pos="11" rst="0">
		<comment>'1' means CRC error of writing data is the source of interrupt.
		</comment>
	</bits>
	 
	<bits access="r" name="DAT_OVER_SC" pos="12" rst="0">
		<comment>'1' means the end of data transmission is the source of interrupt.
		</comment>
	</bits>

	<bits access="r" name="TXDMA_DONE_SC" pos="13" rst="0">
		<comment>'1' means tx dma done is the source of interrupt.
		</comment>
	</bits>

	<bits access="r" name="RXDMA_DONE_SC" pos="14" rst="0">
		<comment>'1' means rx dma done is the source of interrupt.
		</comment>
	</bits>    
	
</reg>



<reg protect="rw" name="SDMMC_INT_MASK">

	<bits access="rw" name="NO_RSP_MK" pos="0" rst="0">
		<comment>When no response, '1' means INT is disable.
		</comment>
	</bits>

	<bits access="rw" name="RSP_ERR_MK" pos="1" rst="0">
		<comment>When CRC error of response, '1' means INT is disable.
		</comment>
	</bits>
	
	<bits access="rw" name="RD_ERR_MK" pos="2" rst="0">
		<comment>When CRC error of reading data, '1' means INT is disable.
		</comment>
	</bits>

	<bits access="rw" name="WR_ERR_MK" pos="3" rst="0">
		<comment>When CRC error of writing data, '1' means INT is disable.
		</comment>
	</bits>

	<bits access="rw" name="DAT_OVER_MK" pos="4" rst="0">
		<comment>When data transmission is over, '1' means INT is disable.
		</comment>
	</bits>

	<bits access="rw" name="TXDMA_DONE_MK" pos="5" rst="0">
		<comment>when tx dma done, '1' means INT is disabled.
		</comment>
	</bits>

	<bits access="rw" name="RXDMA_DONE_MK" pos="6" rst="0">
		<comment>'1' means rx dma done, '1' means INT is disabled.
		</comment>
	</bits>    
</reg>


<reg protect="w" name="SDMMC_INT_CLEAR">

	<bits access="w" name="NO_RSP_CL" pos="0" rst="0">
		<comment>Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC.
		</comment>
	</bits>

	<bits access="w" name="RSP_ERR_CL" pos="1" rst="0">
		<comment>Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC.
		</comment>
	</bits>
	
	<bits access="w" name="RD_ERR_CL" pos="2" rst="0">
		<comment>Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC.
		</comment>
	</bits>

	<bits access="w" name="WR_ERR_CL" pos="3" rst="0">
		<comment>Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC.
		</comment>
	</bits>

	<bits access="w" name="DAT_OVER_CL" pos="4" rst="0">
		<comment>Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC.
		</comment>
	</bits>

 	<bits access="w" name="TXDMA_DONE_CL" pos="5" rst="0">
		<comment>Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC.
		</comment>
	</bits>

	<bits access="w" name="RXDMA_DONE_CL" pos="6" rst="0">
		<comment>Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC.
		</comment>
	</bits>   
</reg>

<reg protect="rw" name="SDMMC_TRANS_SPEED">

	<bits access="rw" name="SDMMC_TRANS_SPEED" pos="7:0" rst="0">
		<comment>Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)).
		</comment>
	</bits>
</reg>

<reg protect="rw" name="SDMMC_MCLK_ADJUST">

	<bits access="rw" name="SDMMC_MCLK_ADJUST" pos="3:0" rst="0">
		<comment>This register may delay the mclk output. 
			 When MCLK_ADJUSTER = n, Mclk is outputted with  n Pclk.	
		</comment>
	</bits>

	<bits access="rw" name="CLK_INV" pos="4" rst="0">
		<comment>Invert Mclk.	
		</comment>
	</bits>

</reg>

</module>
</archive>
<archive relative = "seg_scan.xml">

<module name="seg_scan" category="Periph">

    <reg name="code_num_reg" protect="rw">
        <bits name="code_num"   pos="4:0"   access="rw" rst="5'h7">
            <comment> configure  the range (1-18) of code number  registers
            </comment>
        </bits>
    </reg>

    <reg name="refresh_cycle_reg" protect="rw"  >
        <bits name="refresh_cycle"   pos="31:0" access="rw" rst="32'hffff">
            <comment>configure the refreshed cycle in pclk domain when change output data from another code number register.
            </comment>
        </bits>
    </reg>

    <reg name="ctrl" protect="rw">
        <bits name="start"    pos="0"     access="rw" rst="0">
            <comment>this is a pulse signal
            </comment>
        </bits>
        <bits name="stop"    pos="1"     access="rw" rst="0">
            <comment>this is a pulse signal
            </comment>
        </bits>
        <bits name="load_en"   pos="2"     access="rw" rst="0">
            <comment>hardware enable and software clear.
            </comment>
        </bits>
    </reg>

    <reg name="code0_reg" protect="rw"  >
        <bits name="code0" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 0 output.
            </comment>
        </bits>
    </reg>

    <reg name="code1_reg" protect="rw"  >
        <bits name="code1" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 1 output.
            </comment>
        </bits>
    </reg>

    <reg name="code2_reg" protect="rw"  >
        <bits name="code2" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 2 output.
            </comment>
        </bits>
    </reg>

    <reg name="code3_reg" protect="rw"  >
        <bits name="code3" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 3 output.
            </comment>
        </bits>
    </reg>

    <reg name="code4_reg" protect="rw"  >
        <bits name="code4" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 4 output.
            </comment>
        </bits>
    </reg>

    <reg name="code5_reg" protect="rw"  >
        <bits name="code5" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 5 output.
            </comment>
        </bits>
    </reg>

    <reg name="code6_reg" protect="rw"  >
        <bits name="code6" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 6 output.
            </comment>
        </bits>
    </reg>

    <reg name="code7_reg" protect="rw"  >
        <bits name="code7" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 7 output.
            </comment>
        </bits>
    </reg>

    <reg name="code8_reg" protect="rw"  >
        <bits name="code8" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 8 output.
            </comment>
        </bits>
    </reg>

    <reg name="code9_reg" protect="rw"  >
        <bits name="code9" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 9 output.
            </comment>
        </bits>
    </reg>

    <reg name="code10_reg" protect="rw"  >
        <bits name="code10" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 10 output.
            </comment>
        </bits>
    </reg>

    <reg name="code11_reg" protect="rw"  >
        <bits name="code11" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 11 output.
            </comment>
        </bits>
    </reg>

    <reg name="code12_reg" protect="rw"  >
        <bits name="code12" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 12 output.
            </comment>
        </bits>
    </reg>

    <reg name="code13_reg" protect="rw"  >
        <bits name="code13" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 13 output.
            </comment>
        </bits>
    </reg>

    <reg name="code14_reg" protect="rw"  >
        <bits name="code14" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 14 output.
            </comment>
        </bits>
    </reg>

    <reg name="code15_reg" protect="rw"  >
        <bits name="code15" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 15 output.
            </comment>
        </bits>
    </reg>

    <reg name="code16_reg" protect="rw"  >
        <bits name="code16" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 16 output.
            </comment>
        </bits>
    </reg>

    <reg name="code17_reg" protect="rw"  >
        <bits name="code17" pos="17:0"   access="rw" rst="18'h0">
            <comment> pattern 17 output.
            </comment>
        </bits>
    </reg>


    <reg name="pin_oen0_reg" protect="rw" > 
        <bits name="pin_oen0" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 0 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen1_reg" protect="rw"  >
        <bits name="pin_oen1" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 1 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen2_reg" protect="rw"  >
        <bits name="pin_oen2" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 2 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen3_reg" protect="rw"  >
        <bits name="pin_oen3" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 3 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen4_reg" protect="rw"  >
        <bits name="pin_oen4" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 4 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen5_reg" protect="rw"  >
        <bits name="pin_oen5" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 5 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen6_reg" protect="rw"  >
        <bits name="pin_oen6" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 6 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen7_reg" protect="rw"  >
        <bits name="pin_oen7" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 7 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen8_reg" protect="rw"  >
        <bits name="pin_oen8" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 8 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen9_reg" protect="rw"  >
        <bits name="pin_oen9" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 9 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen10_reg" protect="rw"  >
        <bits name="pin_oen10" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 10 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen11_reg" protect="rw"  >
        <bits name="pin_oen11" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 11 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen12_reg" protect="rw"  >
        <bits name="pin_oen12" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 12 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen13_reg" protect="rw"  >
        <bits name="pin_oen13" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 13 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen14_reg" protect="rw"  >
        <bits name="pin_oen14" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 14 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen15_reg" protect="rw"  >
        <bits name="pin_oen15" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 15 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen16_reg" protect="rw"  >
        <bits name="pin_oen16" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 16 of pin_oen.
            </comment>
        </bits>
    </reg>

    <reg name="pin_oen17_reg" protect="rw"  >
        <bits name="pin_oen17" pos="17:0"   access="rw" rst="18'h3ffff">
            <comment> pattern 17 of pin_oen.
            </comment>
        </bits>
    </reg>


</module>
</archive>
<archive relative = "spi.xml">
<var name = "SPI_TX_FIFO_SIZE" value="16"/>
<var name = "SPI_RX_FIFO_SIZE" value="16"/>

<module name="spi" category="Periph">
    <reg name="ctrl" protect="rw">
        <bits name="Enable"  pos="0" access="rw" rst="0">
            <comment>Enable the module and activate the chip select selected by CS_sel field.
            </comment>
        </bits>
        <bits name="CS_sel" pos="2:1" access="rw" rst="0">
            <comment>Selects the active CS.
            </comment>
            <options>
                <option name="CS0" value="0"/>
                <option name="CS1" value="1"/>
                <option name="CS2" value="2"/>
                <option name="CS3" value="3"/>
                <default/><shift/><mask/>
            </options>
        </bits>
        <bits name="Input_mode" pos="4" access="rw"  rst="1">
            <comment>When set to 1 the inputs are activated, else only the output is driven and no data are stored in the receive FIFO.
                <br/>Notes: The Input_mode bit status is also readable onto the bit rxtx_buffer[31].
            </comment>
        </bits>
        <bits name="Clock_Polarity" pos="5" access="rw" rst="1">
            <comment>The spi clock polarity
                <br/>when '0' the clock disabled level is low, and the first edge is a rising edge.
                <br/>When '1' the clock disabled level is high, and the first edge is a falling edge.
            </comment>
        </bits>
        <bits name="Clock_Delay" pos="7:6" access="rw" rst="3">
            <comment>Transfer start to first edge delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first clock edge.
            </comment>
        </bits>
        <bits name="DO_Delay" pos="9:8" access="rw" rst="3">
            <comment>Transfer start to first data out delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first data out
            </comment>
        </bits>
        <bits name="DI_Delay" pos="11:10" access="rw" rst="3">
            <comment>Transfer start to first data in sample delay value from 0 to 3 is the number of spi clock half period between the CS activation and the first data in sampled.
                <br/>NOTE: DI_Delay must be less or equal to DO_Delay + CS_Delay + 2.
                <br/>In other words DI_Delay can be 3 only if DO_Delay and CS_Delay are not both equal to 0.
            </comment>
        </bits>
        <bits name="CS_Delay" pos="13:12" access="rw" rst="3">
            <comment>Transfer end to chip select deactivation delay value from 0 to 3 is the number of spi clock half period between the end of transfer and CS deactivation
            </comment>
        </bits>
        <bits name="CS_Pulse" pos="15:14" access="rw" rst="3">
            <comment>Chip select deactivation to reactivation minimum delay value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new CS activation (CS will activate only if more data are available in the transmit FIFO)
            </comment>
        </bits>
        <bits name="Frame_Size" pos="20:16" access="rw" rst="31">
            <comment>Frame Size
                <br/>The frame size is the binary value of this register + 1 valid value are 3 to 31 (frame size 4 to 32bits)
            </comment>
        </bits>
        <bits name="OE_delay" pos="28:24" access="rw" rst="31">
            <comment>OE delay
                <br/>When 0: regular mode, SPI_DO pin as output only.
                <br/>Value from 1 to 31 is the number of data out to transfert before the SPI_DO pin switch to input.
            </comment>
        </bits>
        <bits name="ctrl_data_mux_sel" pos="29" access="rw" rst="0">
            <comment>Selects the active CS and Input_reg either from the ctrl or rxtx_buffer register.
                <br/>If SPI FIFO 8b or 32b, when set to "0": CS from CS_sel and INPUT from Input_mode in the register ctrl.
                <br/>Only if SPI FIFO 32b, when set to "1": CS and INPUT from SPI DATA.(Do not work for FIFO8b)
            </comment>
            <options>
                <option name="Ctrl_reg_sel"  value="0"/>
                <option name="Data_reg_sel"  value="1"/>
                <default/><shift/><mask/>
            </options>            
        </bits>
        
        <bits name="Input_sel" pos="31:30" access="rw" rst="0">
            <comment>Selects the input line to be used as SPI data in.(Not used for SPI3)
                <br/>when "00" the SPI_DI_0 is used.
                <br/>When "01" the SPI_DI_1 is used.
                <br/>When "10" the SPI_DI_2 is used. 
                <br/>When "11" reserved.
            </comment>
        </bits>
        
    </reg>
        
    <reg name="status" protect="rw">

        <bits name="Active_Status" pos="0" access="r" rst="0">
            <comment>'1' when a transfer is in progress.
            </comment>
        </bits>
        <bits name="Cause_Rx_Ovf_Irq" pos="3" access="rw" rst="0">
            <comment>The receive FIFO overflow irq cause.
                <br/>Writing a '1' clear the receive overflow status and cause.
            </comment>
        </bits>
        <bits name="Cause_Tx_Th_Irq" pos="4" access="r" rst="0">
            <comment>The transmit FIFO threshold irq cause.
            </comment>
        </bits>
        <bits name="Cause_Tx_Dma_Irq" pos="5" access="rw" rst="0">
            <comment>The transmit Dma Done irq cause.
                <br/>Writing a '1' clear the transmit Dma Done status and cause.
            </comment>
        </bits>
        <bits name="Cause_Rx_Th_Irq" pos="6" access="r" rst="0">
            <comment>The receive FIFO threshold irq cause.
            </comment>
        </bits>
        <bits name="Cause_Rx_Dma_Irq" pos="7" access="rw" rst="0">
            <comment>The receive Dma Done irq cause.
                <br/>Writing a '1' clear the receive Dma Done status and cause.
            </comment>
        </bits>
        <bitgroup name="Irq_Cause">
            <entry ref="Cause_Rx_Ovf_Irq"/>
            <entry ref="Cause_Tx_Th_Irq"/>
            <entry ref="Cause_Tx_Dma_Irq"/>
            <entry ref="Cause_Rx_Th_Irq"/>
            <entry ref="Cause_Rx_Dma_Irq"/>
        </bitgroup>
        <bits name="Tx_Ovf" pos="9" access="rw" rst="0">
            <comment>The transmit FIFO overflow status.
                <br/>Writing a '1' clear the transmit overflow status and cause.
            </comment>
        </bits>
        <bits name="Rx_Udf" pos="10" access="rw" rst="0">
            <comment>The receive FIFO underflow status.
                <br/>Writing a '1' clear the receive underflow status and cause.
            </comment>
        </bits>
        <bits name="Rx_Ovf" pos="11" access="rw" rst="0">
            <comment>The receive FIFO overflow status.
                <br/>Writing a '1' clear the receive overflow status and cause.
            </comment>
        </bits> 
        <bits name="Tx_Th" pos="12" access="r" rst="0">
            <comment>The transmit FIFO threshold status.
            </comment>
        </bits> 
        <bits name="Tx_Dma_Done" pos="13" access="rw" rst="0">
            <comment>The transmit Dma Done status.
                <br/>Writing a '1' clear the transmit Dma Done status and cause.
            </comment>
        </bits> 
        <bits name="Rx_Th" pos="14" access="r" rst="0">
            <comment>The receive FIFO threshold status.
            </comment>
        </bits> 
        <bits name="Rx_Dma_Done" pos="15" access="rw" rst="0">
            <comment>The receive Dma Done status.
                <br/>Writing a '1' clear the receive Dma Done status and cause.
            </comment>
        </bits> 
        <bits name="Tx_Space" pos="20:16" access="r" rst="16" >
            <comment>Transmit FIFO Space
                <br/>Number of empty spot in the FIFO
            </comment>
            <options>
                <mask/>
                <shift/>
            </options>
        </bits> 
        <bits name="Rx_Level" pos="28:24" access="r" rst="0">
            <comment>Receive FIFO level
                <br/>Number of DATA in the FIFO
            </comment>
            <options>
                <mask/>
                <shift/>
            </options>
        </bits> 
        <bits name="FIFO_Flush" pos="30" access="w" rst="0">
            <comment>Writing '1' flush both FIFO, don't do it when SPI is active (transfer in progress)
            </comment>
        </bits>
    </reg>
    <reg name="rxtx_buffer" protect="--">
        <comment>Spi1 fifo size (rxtx_buffer): 8bits.<br/>
                 Spi2 fifo size (rxtx_buffer): 8bits.<br/>
                 Spi3 fifo size (rxtx_buffer): 32bits.<br/>

        </comment>
        <bits name="DATA_IN_OUT" pos="28:0" access="rw" rst="0">
            <comment>Write to the transmit FIFO
	    Read in the receive FIFO.
            </comment>
        </bits>
        
        <bits name="CS" pos="30:29" access="rw" rst="0">
            <comment>
                Chip Select on which write the data written in the
                Fifo. 
		Data in bit [30:29]
		Data out bit [30:29]
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>

        <bits name="READ_ENA" pos="31" access="rw" rst="0">
            <comment>
                Set this bit to one when the data received while sending
                this peculiar data are expected to be kept in the FIFO,
                otherwise no data is recorded in the FIFO.
		Data in bit [31]
		Data out bit [31]
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>

    </reg>
    <reg name="cfg" protect="rw">
        <bits name="CS_Polarity" pos="2:0" access="rw" rst="all1" cut="1" cutprefix="CS_Polarity">
            <comment>Chip select polarity
            </comment>
            <options>
                <option name="active high" value="0"><comment>chip select is active high</comment></option>
                <option name="active low" value="1"><comment>chip select is active low</comment></option>
                <mask/><shift/><default/>
            </options>
        </bits>
        <bits name="Clock_Divider" pos="25:16" access="rw" rst="0x3ff">
            <comment>Clock Divider
                <br/>The state machine clock is generated by dividing the system clock by the value of this register + 1.
                <br/>So the output clock is divided by (register + 1)*2
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>
        <bits name="Clock_Limiter" pos="28" access="rw" rst="1">
            <comment>When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz.
                <br/> for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock.
            </comment>
            <options><mask/><shift/><default/></options>
        </bits>

    </reg>

    <reg name="pattern" protect="rw">
        <bits name="pattern" pos="7:0" access="rw" rst="0">
            <comment>MMC Pattern value for RX pattern match mode.
            </comment>
        </bits>
        <bits name="pattern_mode" pos="8" access="rw" rst="0">
            <comment> Enable the pattern mode.
            </comment>
            <options>
                <option name="disabled" value="0"><comment>Spi Behaviour.</comment></option>
                <option name="enabled" value="1"><comment>Pattern matching.</comment></option>
                <default/><shift/><mask/>
            </options>
        </bits>
        <bits name="pattern_selector" pos="9" access="rw" rst="0">
            <comment> Select the RX pattern matching mode when the pattern_mode is enabled( set 1). Used for SD/MMC SPI mode.</comment>
            <options>
                <option name="UNTIL" value="0"><comment>No datas are written into the RX FIFO UNTIL the received data is equal to the pattern.</comment></option>
                <option name="WHILE" value="1"><comment>No datas are written into the RX FIFO WHILE the received data is equal to the pattern.</comment></option>
                <default/><shift/><mask/>
            </options>
        </bits>
    </reg>
    
    <reg name="stream" protect="rw">
        <bits name="tx_stream_bit" pos="0" access="rw" rst="0">
            <comment>When TX stream mode is enabled, once the TX fifo is empty, all new bits send have the value of this bit.
            </comment>
            <options>
                <option name="zero" value="0"/>
                <option name="one" value="1"/>
                <default/><shift/><mask/>
            </options>
        </bits>
        <bits name="tx_stream_mode" pos="8" access="rw" rst="0">
            <comment>Enable the TX stream mode. Used for SD/MMC SPI mode.
                <br/>When enabled, this mode provide infinite bit stream for sending, after fifo is empty the extra bits generated all have the same value. The value is in tx_stream_bit.
            </comment>    
            <options>
                <option name="disabled" value="0"/>
                <option name="enabled" value="1"/>
                <default/><shift/><mask/>
            </options>
        </bits>
        <bits name="tx_stream_stop_with_rx_dma_done" pos="16" access="rw" rst="0">
            <comment>Allow to automatically clear the tx_stream_mode when Rx_Dma_Done is set.
            </comment>    
            <options>
                <option name="disabled" value="0"/>
                <option name="enabled" value="1"/>
                <default/><shift/><mask/>
            </options>
        </bits>
    </reg>
    <reg name="pin_control" protect="rw">
        <bits name="clk_ctrl" pos="1:0" access="rw" rst="0">
            <options>
                <option name="Spi Ctrl" value="0"><comment>The Spi_Clk pin is set OUTPUT(Basic SPI Behaviour).</comment></option>
                <option name="Input Ctrl" value="1"><comment>The Spi_Clk pin is set INPUT (High Impedance).</comment></option>
                <option name="Force 0 Ctrl" value="2"><comment>The Spi_Clk pin is set OUTPUT and forced to 0.</comment></option>
                <option name="Force 1 Ctrl" value="3"><comment>The Spi_Clk pin is set OUTPUT and forced to 1.</comment></option>
                <default/>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="do_ctrl" pos="3:2" access="rw" rst="0">
            <options>
                <option name="Spi Ctrl" value="0"><comment>The Spi_DO pin is set OUTPUT(Basic SPI Behaviour).</comment></option>
                <option name="Input Ctrl" value="1"><comment>The Spi_DO pin is set INPUT (High Impedance).</comment></option>
                <option name="Force 0 Ctrl" value="2"><comment>The Spi_DO pin is set OUTPUT and forced to 0.</comment></option>
                <option name="Force 1 Ctrl" value="3"><comment>The Spi_DO pin is set OUTPUT and forced to 1.</comment></option>
                <default/>
                <mask/>
                <shift/>
            </options>            
        </bits>
        <bits name="cs0_ctrl" pos="5:4" access="rw" rst="0">
            <options>
                <option name="Spi Ctrl" value="0"><comment>The Spi_CSO pin is set OUTPUT(Basic SPI Behaviour).</comment></option>
                <option name="Input Ctrl" value="1"><comment>The Spi_CSO pin is set INPUT (High Impedance).</comment></option>
                <option name="Force 0 Ctrl" value="2"><comment>The Spi_CSO pin is set OUTPUT and forced to 0.</comment></option>
                <option name="Force 1 Ctrl" value="3"><comment>The Spi_CSO pin is set OUTPUT and forced to 1.</comment></option>
                <default/>
                <mask/>
                <shift/>
            </options>               
        </bits>        
        <bits name="cs1_ctrl" pos="7:6" access="rw" rst="0">
            <options>
                <option name="Spi Ctrl" value="0"><comment>The Spi_CS1 pin is set OUTPUT(Basic SPI Behaviour).</comment></option>
                <option name="Input Ctrl" value="1"><comment>The Spi_CS1 pin is set INPUT (High Impedance).</comment></option>
                <option name="Force 0 Ctrl" value="2"><comment>The Spi_CS1 pin is set OUTPUT and forced to 0.</comment></option>
                <option name="Force 1 Ctrl" value="3"><comment>The Spi_CS1 pin is set OUTPUT and forced to 1.</comment></option>
                <default/>
                <mask/>
                <shift/>
            </options>   
        </bits>
        <bits name="cs2_ctrl" pos="9:8" access="rw" rst="0">
            <options>
                <option name="Spi Ctrl" value="0"><comment>The Spi_CS2 pin is set OUTPUT(Basic SPI Behaviour).</comment></option>
                <option name="Input Ctrl" value="1"><comment>The Spi_CS2 pin is set INPUT (High Impedance).</comment></option>
                <option name="Force 0 Ctrl" value="2"><comment>The Spi_CS2 pin is set OUTPUT and forced to 0.</comment></option>
                <option name="Force 1 Ctrl" value="3"><comment>The Spi_CS2 pin is set OUTPUT and forced to 1.</comment></option>
                <default/>
                <mask/>
                <shift/>
            </options>   
        </bits> 
         
    </reg>
    <reg name="irq" protect="rw">
        <bits name="Mask_Rx_ovf_Irq" pos="0" access="rw" rst="0">
            <comment>Mask the receive FIFO overflow irq
            </comment>
        </bits>
        <bits name="Mask_Tx_Th_Irq" pos="1" access="rw" rst="0">
            <comment>Mask the transmit FIFO threshold irq
            </comment>
        </bits>
        <bits name="Mask_Tx_Dma_Irq" pos="2" access="rw" rst="0">
            <comment>Mask the transmit Dma Done irq
            </comment>
        </bits>
        <bits name="Mask_Rx_Th_Irq" pos="3" access="rw" rst="0">
            <comment>Mask the receive FIFO threshold irq
            </comment>
        </bits>
        <bits name="Mask_Rx_Dma_Irq" pos="4" access="rw" rst="0">
            <comment>Mask the receive DMA Done irq
            </comment>
        </bits>
        <bitgroup name="Irq_Mask">
            <entry ref="Mask_Rx_ovf_Irq"/>
            <entry ref="Mask_Tx_Th_Irq"/>
            <entry ref="Mask_Tx_Dma_Irq"/>
            <entry ref="Mask_Rx_Th_Irq"/>
            <entry ref="Mask_Rx_Dma_Irq"/>
        </bitgroup>
        <bits name="Tx_Threshold" pos="6:5" access="rw" rst="3">
            <comment>Transmit FIFO threshold this threshold is used to generate the irq.
            </comment>
            <options>
                <option name="1 Empty Slot" value="0"/>
                <option name="4 Empty Slots" value="1"/>
                <option name="8 Empty Slots" value="2"/>
                <option name="12 Empty Slots" value="3"/>
                <default/><shift/><mask/>
            </options>
        </bits>
        <bits name="Rx_Threshold" pos="8:7" access="rw" rst="3">
            <comment>Receive FIFO threshold this threshold is used to generate the irq.
            </comment>
            <options>
                <option name="1 Valid Data" value="0"/>
                <option name="4 Valid Data" value="1"/>
                <option name="8 Valid Data" value="2"/>
                <option name="12 Valid Data" value="3"/>
                <default/><shift/><mask/>
            </options>
        </bits>
    </reg>

</module>
</archive>
<archive relative = "spi_flash.xml">
<module name="spi_flash" category="System">

    <reg name="spi_cmd_addr" protect="rw">
		<bits access="rw" name="spi_tx_cmd" pos="7:0" rst="all0">           
			<comment> spi flash command to send. 
			</comment>
		</bits>
		<bits access="rw" name="spi_address" pos="31:8" rst="all0">           
			<comment> spi flash address to send. 
			</comment>
		</bits>
     </reg>
	 <reg name="spi_block_size" protect="rw">
		<bits access="rw" name="spi_modebit" pos="7:0" rst="all0">           
			<comment> spi flash modebit,set 0xA0 to enable continuous read. 
			</comment>
		</bits>
		<bits access="rw" name="spi_rw_blk_size" pos="16:8" rst="0x1">           
			<comment> spi flash spi read/write block size. 
			</comment>
        </bits>
		<bits access="rw" name="continuous enable" pos="24" rst="0x0">           
        </bits>
     </reg>
     <reg name="spi_data_fifo" protect="w">
		<bits access="w" name="spi_tx_data" pos="7:0" rst="all0">           
			<comment> spi flash data to send. 
			</comment>
		</bits>
		<bits access="w" name="spi_send_type" pos="8" rst="0x0">           
			<comment> spi send byte, 1: quad send 0: spi send. 
			</comment>
		</bits>
     </reg>

     <reg name="spi_fifo_status" protect="r">
		<bits access="r" name="spi_flash_busy" pos="0" rst="0x0">           
			<comment> spi flash busy. 
			</comment>
		</bits>
		<bits access="r" name="tx_fifo_empty" pos="1" rst="0x1">           
			<comment> tx fifo empty. 
			</comment>
		</bits>
		<bits access="r" name="tx_fifo_full" pos="2" rst="0x0">           
			<comment> tx fifo full. 
			</comment>
		</bits>
		<bits access="r" name="rx_fifo_empty" pos="3" rst="0x1">           
			<comment> rx fifo empty. 
			</comment>
		</bits>
		<bits access="r" name="rx_fifo_count" pos="8:4" rst="all0">           
			<comment> rx fifo data count. 
			</comment>
		</bits>
		<bits access="r" name="read_state_busy" pos="9" rst="0">           
		</bits>
		<bits access="r" name="main_fsm_idle" pos="10" rst="0">           
		</bits>
     </reg>

     <reg name="spi_read_back" protect="r">
		<bits access="r" name="spi_read_back_reg" pos="31:0" rst="all0">           
			<comment> spi flash read back data. 
			</comment>
		</bits>
     </reg>

     <reg name="spi_config" protect="rw">
		<bits access="rw" name="quad_mode" pos="0" rst="0x0">           
			<comment> spi flash read mode from AHB. 
			</comment>
			<options>
            <option name="spi read"  value ="0"></option>
            <option name="quad read" value ="1"></option>
        	</options>
		</bits>
		<bits access="rw" name="spi_wprotect_pin" pos="1" rst="0x0">           
			<comment> spi flash wprotect pin. 
			</comment>
		</bits>
		<bits access="rw" name="spi_hold_pin" pos="2" rst="0x0">           
			<comment> spi flash hold pin. 
			</comment>
		</bits>
		<bits access="rw" name="sample_delay" pos="6:4" rst="0x2">           
			<comment> spi flash read sample delay cycles. 
			</comment>
		</bits>
		<bits access="rw" name="bypass_start_cmd" pos="7" rst="0x1">           
		</bits>
		<bits access="rw" name="clk_divider" pos="15:8" rst="0x8">           
			<comment> spi flash clock divider. 
			</comment>
		</bits>
		<bits access="rw" name="cmd_quad" pos="16" rst="0x0">           
			<comment> spi flash send command using quad lines. 
			</comment>
        </bits>
		<bits access="rw" name="tx_rx_size" pos="18:17" rst="0x0">           
        </bits>
     </reg>

     <reg name="spi_fifo_control" protect="w">
		<bits access="w" name="rx_fifo_clr" pos="0" rst="0x0">           
			<comment> rx fifo_clr,self clear. 
			</comment>
		</bits>
		<bits access="w" name="tx_fifo_clr" pos="1" rst="0x0">           
			<comment> tx fifo_clr,self clear. 
			</comment>
		</bits>
     </reg>

     <reg name="spi_cs_size" protect="rw">
		<bits access="rw" name="spi_cs_num" pos="0" rst="0x0">           
			<comment> spi flash cs num. 
			</comment>
			<options>
            <option name="1 spiflash"  value ="0"></option>
            <option name="2 spiflash"  value ="1"></option>
        	</options>
		</bits>
		<bits access="rw" name="spi size" pos="2:1" rst="all0">           
			<comment> single chip spi flash size. 
			</comment>
			<options>
            <option name="32m"  value ="0"></option>
            <option name="64m"  value ="1"></option>
            <option name="16m"  value ="2"></option>
            <option name="8m"   value ="3"></option>
        	</options>
		</bits>
		<bits access="rw" name="spi_128m" pos="3" rst="0x0">           
			<comment> spi flash is 128m flash. 
			</comment>
			<options>
            <option name="other spiflash"  value ="0"></option>
            <option name="128m  spiflash"  value ="1"></option>
        	</options>
		</bits>
		<bits access="rw" name="ahb_read_disable" pos="4" rst="0x0">           
			<comment> disable read from ahb. 
			</comment>
			<options>
            <option name="enable ahb read"  value ="0"></option>
            <option name="disable ahb read" value ="1"></option>
        	</options>
		</bits>
		<bits access="rw" name="SEL_FLASH_1_SEL" pos="5" rst="0x0">           
		<options>
            <option name="flash 0"  value ="0"></option>
            <option name="flash 1" value ="1"></option>
        	</options>
		</bits>
		<bits access="rw" name="spi_cs1_sel1" pos="6" rst="0x0">           
		</bits>
		<bits access="rw" name="diff_128m_diff_cmd_en" pos="7" rst="0x0">           
		</bits>
    </reg>

    <reg name="spi_read_cmd" protect="rw">
		<bits access="rw" name="qread_cmd" pos="7:0" rst="8'heb">           
			<comment> quad read command. 
			</comment>
		</bits>
		<bits access="rw" name="fread_cmd" pos="15:8" rst="8'h0b">           
			<comment> fast read command. 
			</comment>
		</bits>
		<bits access="rw" name="read_cmd" pos="23:16" rst="8'h03">           
			<comment> read command. 
			</comment>
		</bits>
		<bits access="w" name="protect_byte" pos="31:24" rst="all0">           
			<comment> protect_byte, must be 0x55 when program this register. 
			</comment>
		</bits>
    </reg>
    
    <reg name="spi_flash_24" protect="rw">
		<bits access="rw" name="nand_sel" pos="0" rst="all0">           
		</bits>
		<bits access="rw" name="nand_addr" pos="2:1" rst="all0">           
		</bits>
		<bits access="rw" name="page_read_cmd" pos="15:8" rst="8'h13">           
        </bits>
		<bits access="rw" name="get_sts_cmd" pos="23:16" rst="8'h0f">           
        </bits>
		<bits access="rw" name="ram_read_cmd" pos="31:24" rst="8'h03">           
        </bits>
    </reg>

    <reg name="spi_flash_28" protect="rw">
		<bits access="rw" name="get_sts_addr" pos="7:0" rst="8'hc0">           
		</bits>
		<bits access="rw" name="program_exe_cmd" pos="15:8" rst="8'h10">           
        </bits>
		<bits access="rw" name="sts_qip" pos="23:16" rst="8'h01">           
        </bits>
    </reg>

    <reg name="spi_flash_2c" protect="rw">
		<bits access="rw" name="four_byte_addr" pos="0" rst="all0">           
		</bits>
		<bits access="rw" name="dummy_cycle_en" pos="1" rst="all0">           
		</bits>
		<bits access="rw" name="dummy_cycle" pos="11:8" rst="8'h08">           
        </bits>
    </reg>

    <reg name="spi_flash_30" protect="rw">
		<bits access="rw" name="first_128m_cmd" pos="7:0" rst="0x8c">           
		</bits>
		<bits access="rw" name="second_128m_cmd" pos="15:8" rst="0x8d">           
        </bits>
		<bits access="rw" name="third_128m_cmd" pos="23:16" rst="8'h0">           
        </bits>
		<bits access="rw" name="fourth_128m_cmd" pos="31:24" rst="8'h0">           
        </bits>
    </reg>
     
    <reg name="spi_flash_34" protect="rw">
		<bits access="rw" name="timeout_value" pos="31:0" rst="32'h4000">           
		</bits>
    </reg>
     
</module>


</archive>
<archive relative = "sys_ctrl.xml">

<module name="sys_ctrl" category="System">
  <var name="SYS_CTRL_PROTECT_LOCK" value="0xa50000" ><comment>For REG_DBG protect lock/unlock value for backward compatible. Unlock is not needed.</comment></var>
  <var name="SYS_CTRL_PROTECT_UNLOCK" value="0xa50001" />

  <reg name="chip_id" protect="r">
    <bits access="r" name="major_id" pos="31:18" rst="0x22CD">
    </bits>
    <bits access="r" name="minor_id" pos="17:13" rst="0x0">
    </bits>
    <bits access="r" name="metal_id" pos="11:0" rst="0x0">
    </bits>
  </reg>

  <reg name="reg_dbg" protect="rw">
    <bits access="rw" name="scratch" pos="15:0" rst="0x0">
    </bits>
  </reg>

  <reg name="sys_rst_set0" protect="rw">
    <bits access="w1s" name="set_rst_global" pos="31:31" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_iomux" pos="29:29" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_pwm" pos="28:28" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_gpio" pos="27:27" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_i2c3" pos="26:26" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_i2c2" pos="25:25" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_i2c1" pos="24:24" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_spi3" pos="23:23" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_spi2" pos="22:22" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_spi1" pos="21:21" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_uart2" pos="20:20" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_uart1" pos="19:19" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_dbg" pos="18:18" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sys_mailbox" pos="17:17" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sys_comregs" pos="16:16" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_nb_rf_spi" pos="15:15" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_gsm_rf_spi" pos="14:14" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_nb_tcu" pos="13:13" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_gsm_tcu" pos="12:12" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sci2" pos="11:11" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sci1" pos="10:10" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_usbc" pos="9:9" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sdmmc" pos="8:8" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_psram" pos="7:7" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_flash" pos="6:6" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sys_wdt" pos="5:5" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sys_timer" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sys_irq" pos="3:3" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sys_ifc" pos="2:2" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sys_dma" pos="1:1" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_xcpu" pos="0:0" rst="0x1">
    </bits>
  </reg>

  <reg name="sys_rst_clr0" protect="rw">
    <bits access="rw1c" name="clr_rst_iomux" pos="29:29" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_pwm" pos="28:28" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_gpio" pos="27:27" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_i2c3" pos="26:26" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_i2c2" pos="25:25" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_i2c1" pos="24:24" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_spi3" pos="23:23" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_spi2" pos="22:22" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_spi1" pos="21:21" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_uart2" pos="20:20" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_uart1" pos="19:19" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_dbg" pos="18:18" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sys_mailbox" pos="17:17" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sys_comregs" pos="16:16" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_nb_rf_spi" pos="15:15" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_gsm_rf_spi" pos="14:14" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_nb_tcu" pos="13:13" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_gsm_tcu" pos="12:12" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sci2" pos="11:11" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sci1" pos="10:10" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_usbc" pos="9:9" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sdmmc" pos="8:8" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_psram" pos="7:7" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_flash" pos="6:6" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sys_wdt" pos="5:5" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sys_timer" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sys_irq" pos="3:3" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sys_ifc" pos="2:2" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sys_dma" pos="1:1" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_xcpu" pos="0:0" rst="0x1">
    </bits>
  </reg>

  <reg name="sys_rst_set1" protect="rw">
    <bits access="rw1s" name="set_rst_jtag" pos="27:27" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_lvds" pos="26:26" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_rf_dig" pos="25:25" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_wcn_dig" pos="24:24" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_abb_dig" pos="23:23" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_aif" pos="22:22" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_aud_codec" pos="21:21" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_aud_ifc" pos="20:20" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_camera" pos="19:19" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_gouda" pos="18:18" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_lzma" pos="17:17" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_voc" pos="16:16" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_gea3" pos="11:11" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_f8" pos="10:10" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_page_spy" pos="9:9" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_cau_dig" pos="8:8" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_flash_ext" pos="5:5" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_sdmmc2" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_uart4" pos="3:3" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_uart3" pos="2:2" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_seg_scan" pos="1:1" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_keypad" pos="0:0" rst="0x1">
    </bits>
  </reg>

  <reg name="sys_rst_clr1" protect="rw">
    <bits access="rw1c" name="clr_rst_jtag" pos="27:27" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_lvds" pos="26:26" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_rf_dig" pos="25:25" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_wcn_dig" pos="24:24" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_abb_dig" pos="23:23" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_aif" pos="22:22" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_aud_codec" pos="21:21" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_aud_ifc" pos="20:20" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_camera" pos="19:19" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_gouda" pos="18:18" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_lzma" pos="17:17" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_voc" pos="16:16" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_gea3" pos="11:11" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_f8" pos="10:10" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_page_spy" pos="9:9" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_cau_dig" pos="8:8" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_flash_ext" pos="5:5" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_sdmmc2" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_uart4" pos="3:3" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_uart3" pos="2:2" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_seg_scan" pos="1:1" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_keypad" pos="0:0" rst="0x1">
    </bits>
  </reg>

  <reg name="bb_rst_set" protect="rw">
    <bits access="rw1s" name="set_rst_nbiot" pos="19:19" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_a53" pos="18:18" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_cipher" pos="17:17" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_cholk" pos="16:16" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_excor" pos="15:15" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_vitac" pos="14:14" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_itlv" pos="13:13" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_cordic" pos="12:12" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_xcor" pos="11:11" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_dfe" pos="8:8" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_rf_if" pos="7:7" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_bb_mailbox" pos="6:6" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_bb_comregs" pos="5:5" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_bb_rom" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_bb_irq" pos="3:3" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_bb_dma" pos="2:2" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_cp2" pos="1:1" rst="0x1">
    </bits>
    <bits access="rw1s" name="set_rst_bcpu" pos="0:0" rst="0x1">
    </bits>
  </reg>

  <reg name="bb_rst_clr" protect="rw">
    <bits access="rw1c" name="clr_rst_nbiot" pos="19:19" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_a53" pos="18:18" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_cipher" pos="17:17" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_cholk" pos="16:16" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_excor" pos="15:15" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_vitac" pos="14:14" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_itlv" pos="13:13" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_cordic" pos="12:12" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_xcor" pos="11:11" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_dfe" pos="8:8" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_rf_if" pos="7:7" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_bb_mailbox" pos="6:6" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_bb_comregs" pos="5:5" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_bb_rom" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_bb_irq" pos="3:3" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_bb_dma" pos="2:2" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_cp2" pos="1:1" rst="0x1">
    </bits>
    <bits access="rw1c" name="clr_rst_bcpu" pos="0:0" rst="0x1">
    </bits>
  </reg>

  <reg name="clk_sys_enable0" protect="rw">
    <bits access="rw1s" name="enable_iomux" pos="29:29" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_pwm" pos="28:28" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_gpio" pos="27:27" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_i2c3" pos="26:26" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_i2c2" pos="25:25" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_i2c1" pos="24:24" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_spi3" pos="23:23" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_spi2" pos="22:22" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_spi1" pos="21:21" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_uart2" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_uart1" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_dbg" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sys_mailbox" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sys_comregs" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_nb_rf_spi" pos="15:15" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_gsm_rf_spi" pos="14:14" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_nb_tcu" pos="13:13" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_gsm_tcu" pos="12:12" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sci2" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sci1" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_usbc" pos="9:9" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sdmmc" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_psram" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_flash" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sys_wdt" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sys_timer" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sys_irq" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sys_ifc" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sys_dma" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_xcpu" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="clk_sys_disable0" protect="rw">
    <bits access="rw1c" name="disable_iomux" pos="29:29" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_pwm" pos="28:28" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_gpio" pos="27:27" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_i2c3" pos="26:26" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_i2c2" pos="25:25" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_i2c1" pos="24:24" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_spi3" pos="23:23" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_spi2" pos="22:22" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_spi1" pos="21:21" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_uart2" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_uart1" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_dbg" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sys_mailbox" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sys_comregs" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_nb_rf_spi" pos="15:15" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_gsm_rf_spi" pos="14:14" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_nb_tcu" pos="13:13" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_gsm_tcu" pos="12:12" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sci2" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sci1" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_usbc" pos="9:9" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sdmmc" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_psram" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_flash" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sys_wdt" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sys_timer" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sys_irq" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sys_ifc" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sys_dma" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_xcpu" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="clk_sys_enable1" protect="rw">
    <bits access="rw1s" name="enable_jtag" pos="27:27" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_lvds" pos="26:26" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_rf_dig" pos="25:25" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_wcn_dig" pos="24:24" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_abb_dig" pos="23:23" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_aif" pos="22:22" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_aud_codec" pos="21:21" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_aud_ifc" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_camera" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_gouda" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_lzma" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_voc" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_gea3" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_f8" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_page_spy" pos="9:9" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_cau_dig" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_flash_ext" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_sdmmc2" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_uart4" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_uart3" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_seg_scan" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_keypad" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="clk_sys_disable1" protect="rw">
    <bits access="rw1c" name="disable_jtag" pos="27:27" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_lvds" pos="26:26" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_rf_dig" pos="25:25" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_wcn_dig" pos="24:24" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_abb_dig" pos="23:23" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_aif" pos="22:22" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_aud_codec" pos="21:21" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_aud_ifc" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_camera" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_gouda" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_lzma" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_voc" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_gea3" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_f8" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_page_spy" pos="9:9" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_cau_dig" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_flash_ext" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_sdmmc2" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_uart4" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_uart3" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_seg_scan" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_keypad" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="clk_bb_enable" protect="rw">
    <bits access="rw1s" name="enable_nbiot" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_a53" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_cipher" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_cholk" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_excor" pos="15:15" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_vitac" pos="14:14" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_itlv" pos="13:13" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_cordic" pos="12:12" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_xcor" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_dfe" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_rf_if" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_bb_mailbox" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_bb_comregs" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_bb_rom" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_bb_irq" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_bb_dma" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_cp2" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1s" name="enable_bcpu" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="clk_bb_disable" protect="rw">
    <bits access="rw1c" name="disable_nbiot" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_a53" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_cipher" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_cholk" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_excor" pos="15:15" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_vitac" pos="14:14" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_itlv" pos="13:13" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_cordic" pos="12:12" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_xcor" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_dfe" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_rf_if" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_bb_mailbox" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_bb_comregs" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_bb_rom" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_bb_irq" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_bb_dma" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_cp2" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1c" name="disable_bcpu" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="pll_ctrl" protect="rw">
    <bits access="r" name="au_pll_locked" pos="13:13" rst="0x0">
    </bits>
    <bits access="rw1c" name="au_pll_pd" pos="12:12" rst="0x0">
    </bits>
    <bits access="rw1s" name="au_pll_pu" pos="11:11" rst="0x0">
    </bits>
    <bits access="r" name="nb_pll_locked" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw1c" name="nb_pll_pd" pos="9:9" rst="0x0">
    </bits>
    <bits access="rw1s" name="nb_pll_pu" pos="8:8" rst="0x0">
    </bits>
    <bits access="r" name="gsm_pll_locked" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw1c" name="gsm_pll_pd" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw1s" name="gsm_pll_pu" pos="4:4" rst="0x0">
    </bits>
    <bits access="r" name="mcu_pll_locked" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1c" name="mcu_pll_pd" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1s" name="mcu_pll_pu" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="sel_clock" protect="rw">
    <bits access="rw" name="sel_clk_usbc" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw" name="sel_clk_usbc_backup" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw" name="sel_clk_dbg" pos="18:18" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_uart4" pos="17:17" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_uart3" pos="16:16" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_uart2" pos="15:15" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_uart1" pos="14:14" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_rf" pos="13:13" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_wcn" pos="12:12" rst="0x1">
    </bits>
    <bits access="rw" name="sel_aif_stb" pos="11:10" rst="0x0">
    </bits>
    <bits access="rw" name="sel_clk_cam_out" pos="9:9" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_voc" pos="8:8" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_nb_tcu" pos="7:7" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_gsm_tcu" pos="6:6" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_spiflash_ext" pos="5:5" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_spiflash" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_psram" pos="3:3" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_bb" pos="2:2" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_sys" pos="1:1" rst="0x1">
    </bits>
    <bits access="rw" name="sel_clk_slow" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="cfg_clk_sys" protect="rw">
    <bits access="rw" name="sys_freq" pos="3:0" rst="0xb">
      <options>
      <option name="div1"   value="15"/>
      <option name="div1p5" value="14"/>
      <option name="div2"   value="13"/>
      <option name="div2p5" value="12"/>
      <option name="div3"   value="11"/>
      <option name="div3p5" value="10"/>
      <option name="div4"   value="9 "/>
      <option name="div4p5" value="8 "/>
      <option name="div5"   value="7 "/>
      <option name="div5p5" value="6 "/>
      <option name="div6"   value="5 "/>
      <mask/>
      <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_clk_bb" protect="rw">
    <bits access="rw" name="bb_freq" pos="3:0" rst="0xb">
      <options>
      <option name="div1p5" value="14"/>
      <option name="div2"   value="13"/>
      <option name="div2p5" value="12"/>
      <option name="div3"   value="11"/>
      <option name="div3p5" value="10"/>
      <option name="div4"   value="9 "/>
      <option name="div4p5" value="8 "/>
      <option name="div5"   value="7 "/>
      <option name="div5p5" value="6 "/>
      <option name="div6"   value="5 "/>
      <mask/>
      <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_clk_psram" protect="rw">
    <bits access="rw" name="psram_freq" pos="3:0" rst="0xd">
      <options>
      <option name="div1"   value="15"/>
      <option name="div1p5" value="14"/>
      <option name="div2"   value="13"/>
      <option name="div2p5" value="12"/>
      <option name="div3"   value="11"/>
      <option name="div3p5" value="10"/>
      <option name="div4"   value="9 "/>
      <option name="div4p5" value="8 "/>
      <option name="div5"   value="7 "/>
      <option name="div5p5" value="6 "/>
      <option name="div6"   value="5 "/>
      <mask/>
      <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_clk_spiflash" protect="rw">
    <bits access="rw" name="spiflash_ext_freq" pos="11:8" rst="0xd">
    </bits>
    <bits access="rw" name="spiflash_freq" pos="3:0" rst="0xd">
      <options>
      <option name="div1p5" value="14"/>
      <option name="div2"   value="13"/>
      <option name="div2p5" value="12"/>
      <option name="div3"   value="11"/>
      <option name="div3p5" value="10"/>
      <option name="div4"   value="9 "/>
      <option name="div4p5" value="8 "/>
      <option name="div5"   value="7 "/>
      <option name="div5p5" value="6 "/>
      <option name="div6"   value="5 "/>
      <mask/>
      <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_clk_dbg" protect="rw">
    <bits access="rw" name="dbg_div_denom" pos="23:10" rst="0xE">
    </bits>
    <bits access="rw" name="dbg_div_num" pos="9:0" rst="0x1">
    </bits>
  </reg>

  <reg name="cfg_clk_uart" protect="rw" count="4">
    <bits access="rw" name="uart_div_denom" pos="23:10" rst="0xE">
    </bits>
    <bits access="rw" name="uart_div_num" pos="9:0" rst="0x1">
    </bits>
  </reg>

  <reg name="cfg_clk_rfdig" protect="rw">
    <bits access="rw" name="rfdig_div_denom" pos="5:0" rst="0x3">
    </bits>
  </reg>

  <reg name="cfg_clk_pwm" protect="rw">
    <bits access="rw" name="pwm_div_denom" pos="7:0" rst="0xff">
    </bits>
  </reg>

  <reg name="cfg_clk_out" protect="rw">
    <bits access="rw" name="clkout_en" pos="31:31" rst="0x0">
    </bits>
    <bits access="rw" name="clkout_sel" pos="4:0" rst="0x0">
      <options>
        <option name="sel_clk_32k        " value=" 0"/>
        <option name="sel_clk_rc26m      " value=" 1"/>
        <option name="sel_clk_xtal6p5m   " value=" 2"/>
        <option name="sel_clk_xtal       " value=" 3"/>
        <option name="sel_clk_xtal2x     " value=" 4"/>
        <option name="sel_clk_phy_nb     " value=" 5"/>
        <option name="sel_clk_phy_gsm    " value=" 6"/>
        <option name="sel_clk_slow       " value=" 7"/>
        <option name="sel_clk_codec_div4 " value=" 8"/>
        <option name="sel_clk_fm         " value=" 9"/>
        <option name="sel_i2s_bck        " value="10"/>
        <option name="sel_aif_tx_stb     " value="11"/>
        <option name="sel_clk_rf_tx_dft  " value="12"/>
        <option name="sel_clk_rf_rx_dft  " value="13"/>
        <option name="sel_clk_nbiot_dft  " value="14"/>
        <option name="sel_clk_usbc_backup" value="15"/>

        <option name="sel_clk_pll_div_hclk_sys     " value="16"/>
        <option name="sel_clk_pll_div_hclk_bb      " value="17"/>
        <option name="sel_clk_pll_div_hclk_wcn     " value="18"/>
        <option name="sel_clk_pll_div_hclk_rf      " value="19"/>
        <option name="sel_clk_pll_div_clk_psram    " value="20"/>
        <option name="sel_clk_pll_div_clk_flash    " value="21"/>
        <option name="sel_clk_pll_div_clk_flash_ext" value="22"/>
        <option name="sel_clk_pll_div_clk_voc      " value="23"/>
        <option name="sel_clk_pll_div_clk_cam_out  " value="24"/>
        <option name="sel_clk_pll_div_clk_bck      " value="25"/>
        <option name="sel_clk_pll_div_clk_usbc     " value="26"/>
        <option name="sel_clk_xtal2x_div_clk_dbg   " value="27"/>
        <option name="sel_clk_xtal2x_div_clk_uart1 " value="28"/>
        <option name="sel_clk_xtal2x_div_clk_uart2 " value="29"/>
        <option name="sel_clk_xtal2x_div_clk_uart3 " value="30"/>
        <option name="sel_clk_xtal2x_div_clk_uart4 " value="31"/>
        <mask/>
        <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_clk_voc" protect="rw">
    <bits access="rw" name="voc_freq" pos="3:0" rst="0xd">
      <options>
      <option name="div1p5" value="14"/>
      <option name="div2"   value="13"/>
      <option name="div2p5" value="12"/>
      <option name="div3"   value="11"/>
      <option name="div3p5" value="10"/>
      <option name="div4"   value="9 "/>
      <option name="div4p5" value="8 "/>
      <option name="div5"   value="7 "/>
      <option name="div5p5" value="6 "/>
      <option name="div6"   value="5 "/>
      <mask/>
      <shift/>
      </options>
    </bits>
  </reg>

  <reg name="cfg_clk_cam" protect="rw">
    <bits access="rw" name="cam_out_en" pos="6:6" rst="0x1">
    </bits>
    <bits access="rw" name="cam_out_mode" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw" name="cam_out_pol" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="cam_div_denom" pos="3:0" rst="0xc">
    </bits>
  </reg>

  <reg name="cfg_clk_usbc" protect="rw">
    <bits access="rw" name="usbc_div_denom" pos="3:0" rst="0x7">
    </bits>
  </reg>

  <reg name="cfg_clk_wcn" protect="rw">
    <bits access="rw" name="wcn_div_denom" pos="5:0" rst="0x6">
    </bits>
  </reg>

  <reg name="cfg_clk_bck" protect="rw">
    <bits access="rw" name="bck_div_denom" pos="15:0" rst="0xffff">
    </bits>
  </reg>

  <reg name="cfg_aif_stb" protect="rw">
    <bits access="rw" name="aif_stb_div_denom" pos="15:0" rst="0xffff">
    </bits>
  </reg>

  <reg name="reset_cause" protect="rw">
    <bits access="rw" name="sw_boot_mode" pos="23:20" rst="0x0">
    </bits>
    <bits access="rw" name="boot_mode" pos="19:16" rst="0x0">
        <options><mask/><shift/></options>
    </bits>
    <bits access="r" name="ac_on_wakeup" pos="7:7" rst="0x0">
    </bits>
    <bits access="r" name="pin_wakeup" pos="6:6" rst="0x0">
    </bits>
    <bits access="r" name="lps_wakeup" pos="5:5" rst="0x0">
    </bits>
    <bits access="r" name="rtc_wakeup" pos="4:4" rst="0x0">
    </bits>
    <bits access="r" name="pin_reset" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw1c" name="hostdebug_reset" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw1c" name="globalsoft_reset" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw1c" name="watchdog_reset" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="dbg_disable_acg0" protect="rw">
    <bits access="rw" name="dbg_disable_hclk_sys_matrix   " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_xcpu         " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_xcpu_int     " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_sys   " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_dma      " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_decoder  " pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc      " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_chdbg" pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch0  " pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch1  " pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch2  " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch3  " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch4  " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch5  " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch6  " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch7  " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch8  " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_ifc_ch9  " pos="17" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_f8           " pos="18" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_gea3         " pos="19" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_page_spy     " pos="20" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_usbc         " pos="21" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_voc          " pos="22" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_voc   " pos="23" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_lzma         " pos="24" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_gouda        " pos="25" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_aud_ifc      " pos="26" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_aud_ifc_ch0  " pos="27" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_aud_ifc_ch1  " pos="28" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_aud_ifc_ch2  " pos="29" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_aud_ifc_ch3  " pos="30" rst="0x0"> </bits>
  </reg>

  <reg name="dbg_disable_acg1" protect="rw">
    <bits access="rw" name="dbg_disable_hclk_sys_mailbox     " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_sys2bb      " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_flash           " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_flash_ext       " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_psram       " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_sys_psram" pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_wcn_psram       " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_wcn_psram" pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_jtag            " pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_wcn             " pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_wcn      " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_sys2wcn     " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_wcn_wcn2sys     " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_wcn_wcn2intmem  " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_rf              " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_rf       " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_sys_sys2rf      " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_rf_rf2sys       " pos="17" rst="0x0"> </bits>
  </reg>

  <reg name="dbg_disable_acg2" protect="rw">
    <bits access="rw" name="dbg_disable_pclk_xcpu          " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sys_dma       " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sys_ifc       " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sys_irq       " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_sys_irq   " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sys_timer     " pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_sys_timer " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sys_timer_per " pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_sys_wdt" pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_sys_dbg" pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_dbghost   " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_dbguart   " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_dbguart       " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_uart1         " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_uart1     " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_uart1  " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_uart2         " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_uart2     " pos="17" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_uart2  " pos="18" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_spi1          " pos="19" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_spi1   " pos="20" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_spi1_per      " pos="21" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_spi2          " pos="22" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_spi2   " pos="23" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_spi2_per      " pos="24" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_spi3          " pos="25" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_spi3   " pos="26" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_spi3_per      " pos="27" rst="0x0"> </bits>
  </reg>

  <reg name="dbg_disable_acg3" protect="rw">
    <bits access="rw" name="dbg_disable_pclk_gpio         " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_gpio     " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_pwm          " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_pwl          " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_pwt          " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_lpg          " pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_pwm   " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_i2c1         " pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_i2c1     " pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_i2c2         " pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_i2c2     " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_i2c3         " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_i2c3     " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sci1         " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_sci1     " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sci1_per     " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sci2         " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_sci2     " pos="17" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sci2_per     " pos="18" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sdmmc        " pos="19" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_sdmmc " pos="20" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sdmmc_per    " pos="21" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sdmmc2       " pos="22" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_sdmmc2" pos="23" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sdmmc2_per   " pos="24" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_seg_scan     " pos="25" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_keypad       " pos="26" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_keypad" pos="27" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_keypad_per   " pos="28" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_page_spy     " pos="29" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_cau_dig      " pos="30" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_iomux        " pos="31" rst="0x0"> </bits>
  </reg>

  <reg name="dbg_disable_acg4" protect="rw">
    <bits access="rw" name="dbg_disable_pclk_nb_tcu            " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_nb_tcu        " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_gsm_tcu           " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_gsm_tcu       " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_gsm_rf_spi        " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_gsm_rf_spi " pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_gsm_rf_spi_per    " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_nb_rf_spi         " pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_nb_rf_spi  " pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_nb_rf_spi_per     " pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_lzma              " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_gouda             " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_camera            " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_camera     " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_camera        " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_aud_ifc           " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_aif               " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_aif           " pos="17" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_aif        " pos="18" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_aud_codec  " pos="19" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_sys_comregs       " pos="20" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_sys_comregS" pos="21" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_psram             " pos="22" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_uart3             " pos="23" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_uart3         " pos="24" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_uart3      " pos="25" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_uart4             " pos="26" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_uart4         " pos="27" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_uart4      " pos="28" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_lvds              " pos="29" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_abb               " pos="30" rst="0x0"> </bits>
  </reg>

  <reg name="dbg_disable_acg5" protect="rw">
    <bits access="rw" name="dbg_disable_hclk_bb_matrix      " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bcpu           " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bcpu_int       " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_bb      " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_cp2_reg        " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_cp2            " pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bb_dma         " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bb_rom         " pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_rf_if          " pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bb_decoder     " pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_xcor           " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_itlv           " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_vitac          " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_excor          " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_evitac         " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_cholk          " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_a53            " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_nbiot          " pos="17" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bb_mailbox     " pos="18" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bb_bb2sys      " pos="19" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_bb_psram       " pos="20" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_hclk_always_bb_psram" pos="21" rst="0x0"> </bits>
  </reg>

  <reg name="dbg_disable_acg6" protect="rw">
    <bits access="rw" name="dbg_disable_pclk_bcpu             " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_cp2              " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_bb_dma           " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_bb_rom       " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_bb_comregs       " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_bb_comregs" pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_bb_irq           " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_bb_irq       " pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_rf_if            " pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_rf_if        " pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_rf_if     " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_xcor             " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_cordic           " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_itlv             " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_vitac            " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_excor            " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_excor     " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_cholk            " pos="17" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_cholk     " pos="18" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_cipher           " pos="19" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_mod_cipher       " pos="20" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_nbiot            " pos="21" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_bb_dbg    " pos="22" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_bb_nb_tcu " pos="23" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_pclk_always_bb_gsm_tcu" pos="24" rst="0x0"> </bits>
  </reg>

  <reg name="dbg_disable_acg7" protect="rw">
    <bits access="rw" name="dbg_disable_clk_sys_timer   " pos="0 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_sys_wdt     " pos="1 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_dbg         " pos="2 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_uart1       " pos="3 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_uart2       " pos="4 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_uart3       " pos="5 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_uart4       " pos="6 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_26m_wcn     " pos="7 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_52m_wcn     " pos="8 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_32k_wcn     " pos="9 " rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_gpio        " pos="10" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_nb_tcu      " pos="11" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_gsm_tcu     " pos="12" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_usbc        " pos="13" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_adp         " pos="14" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_voc         " pos="15" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_voc_always  " pos="16" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_voc_core    " pos="17" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_bck         " pos="18" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_aud_codec   " pos="19" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_rf_tx       " pos="20" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_rf_rx       " pos="21" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_phy_rf_if   " pos="22" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_nbiot       " pos="23" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_psram       " pos="24" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_psram_always" pos="25" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_flash       " pos="26" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_flash_ext   " pos="27" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_cam_out     " pos="28" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_26m_rf      " pos="29" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_32k_rf      " pos="30" rst="0x0"> </bits>
    <bits access="rw" name="dbg_disable_clk_26m_abb     " pos="31" rst="0x0"> </bits>
  </reg>

  <reg name="lp_sys_cg0" protect="rw">
    <bits access="rw" name="lp_cg_iomux" pos="29:29" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_pwm" pos="28:28" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_gpio" pos="27:27" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_i2c3" pos="26:26" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_i2c2" pos="25:25" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_i2c1" pos="24:24" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_spi3" pos="23:23" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_spi2" pos="22:22" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_spi1" pos="21:21" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_uart2" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_uart1" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_dbg" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sys_mailbox" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sys_comregs" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_nb_rf_spi" pos="15:15" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_gsm_rf_spi" pos="14:14" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_nb_tcu" pos="13:13" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_gsm_tcu" pos="12:12" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sci2" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sci1" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_usbc" pos="9:9" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sdmmc" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_psram" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_flash" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sys_wdt" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sys_timer" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sys_irq" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sys_ifc" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sys_dma" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_xcpu" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="lp_sys_cg1" protect="rw">
    <bits access="rw" name="lp_cg_jtag" pos="27:27" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_lvds" pos="26:26" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_rf_dig" pos="25:25" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_wcn_dig" pos="24:24" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_abb_dig" pos="23:23" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_aif" pos="22:22" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_aud_codec" pos="21:21" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_aud_ifc" pos="20:20" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_camera" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_gouda" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_lzma" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_voc" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_gea3" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_f8" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_page_spy" pos="9:9" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_cau_dig" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_flash_ext" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_sdmmc2" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_uart4" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_uart3" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_seg_scan" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_keypad" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="lp_bb_cg" protect="rw">
    <bits access="rw" name="lp_cg_nbiot" pos="19:19" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_a53" pos="18:18" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_cipher" pos="17:17" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_cholk" pos="16:16" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_excor" pos="15:15" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_vitac" pos="14:14" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_itlv" pos="13:13" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_cordic" pos="12:12" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_xcor" pos="11:11" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_dfe" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_rf_if" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_bb_mailbox" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_bb_comregs" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_bb_rom" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_bb_irq" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_bb_dma" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_cp2" pos="1:1" rst="0x0">
    </bits>
    <bits access="rw" name="lp_cg_bcpu" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="misc_ctrl" protect="rw">
    <bits access="rw" name="dbg_trig_sel" pos="23:20" rst="0x0">
    </bits>
    <bits access="rw" name="dbg_clk_sel" pos="19:16" rst="0x0">
      <options>
      <option name="sel_dbg_clk_sys"   value="0"/>
      <option name="sel_dbg_clk_wcn"   value="1"/>
      <option name="sel_dbg_clk_codec" value="4"/>
      <mask/>
      <shift/>
      </options>
    </bits>
    <bits access="rw" name="dbg_out_sel" pos="15:12" rst="0x0">
    </bits>
    <bits access="rw" name="wcn_uart_sel" pos="10:10" rst="0x0">
    </bits>
    <bits access="rw" name="dbg_hresp_err_mask" pos="9:9" rst="0x1">
    </bits>
    <bits access="rw" name="xcpu_cache_rams_disable" pos="8:8" rst="0x0">
    </bits>
    <bits access="rw" name="xcpu_autodisable_cache" pos="7:7" rst="0x0">
    </bits>
    <bits access="rw" name="bcpu_cache_rams_disable" pos="6:6" rst="0x0">
    </bits>
    <bits access="rw" name="bcpu_autodisable_cache" pos="5:5" rst="0x0">
    </bits>
    <bits access="rw" name="lvds_en" pos="4:4" rst="0x0">
    </bits>
    <bits access="rw" name="lvds_mode" pos="3:3" rst="0x0">
    </bits>
    <bits access="rw" name="lvds_src_sel" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw" name="rfspi_mux_mode" pos="1:0" rst="0x2">
    </bits>
  </reg>

  <reg name="mem_ctrl" protect="rw">
    <bits access="rw" name="ret1n" pos="7:7" rst="0x1">
    </bits>
    <bits access="rw" name="emaw" pos="4:3" rst="0x0">
    </bits>
    <bits access="rw" name="ema" pos="2:0" rst="0x2">
    </bits>
  </reg>

  <reg name="pad_ctrl" protect="rw">
    <bits access="rw" name="ibit_simio1" pos="19:18" rst="0x0">
    </bits>
    <bits access="rw" name="ibit_simio0" pos="17:16" rst="0x0">
    </bits>
    <bits access="rw" name="ibit_keyio" pos="15:14" rst="0x0">
    </bits>
    <bits access="rw" name="ibit_gpio" pos="13:12" rst="0x0">
    </bits>
    <bits access="rw" name="ibit_cam" pos="11:10" rst="0x0">
    </bits>
    <bits access="rw" name="ibit_lcd" pos="9:8" rst="0x0">
    </bits>
    <bits access="rw" name="ibit_sdmmc" pos="7:6" rst="0x0">
    </bits>
    <bits access="rw" name="ibit_flash" pos="5:3" rst="0x4">
    </bits>
    <bits access="rw" name="ibit_psram" pos="2:0" rst="0x4">
    </bits>
  </reg>

  <reg name="wcn_ctrl" protect="rw">
    <bits access="rw" name="sys2wcn_reserved" pos="19:4" rst="0x0">
    </bits>
    <bits access="rw" name="sys2wcn_wakeup" pos="2:2" rst="0x0">
    </bits>
    <bits access="rw" name="sys2wcn_int" pos="1:1" rst="0x0">
    </bits>
    <bits access="r" name="wcn2sys_sleep" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="xcpu_dbg_bkp" protect="rw">
    <bits access="rw1c" name="xcpu_stalled" pos="31:31" rst="0x0">
    </bits>
    <bits access="rw" name="xcpu_bkpt_en" pos="30:30" rst="0x0">
    </bits>
    <bits access="rw" name="xcpu_bkpt_mode" pos="29:28" rst="0x3">
    </bits>
    <bits access="rw" name="xcpu_bkpt_addr" pos="27:0" rst="0x0">
    </bits>
  </reg>

  <reg name="bcpu_dbg_bkp" protect="rw">
    <bits access="rw1c" name="bcpu_stalled" pos="31:31" rst="0x0">
    </bits>
    <bits access="rw" name="bcpu_bkpt_en" pos="30:30" rst="0x0">
    </bits>
    <bits access="rw" name="bcpu_bkpt_mode" pos="29:28" rst="0x3">
    </bits>
    <bits access="rw" name="bcpu_bkpt_addr" pos="27:0" rst="0x0">
    </bits>
  </reg>

</module>
</archive>

<archive relative = "sys_ifc.xml">

<include file="globals.xml"/>



<var name="SYS_IFC_ADDR_ALIGN" value="0" />

<var name="SYS_IFC_TC_LEN" value="23" />

<var name="SYS_IFC_STD_CHAN_NB" value="SYS_IFC_NB_STD_CHANNEL" /> 

<var name="SYS_IFC_RFSPI_CHAN" value="2" />

<module name="sys_ifc" category="System">
  

  <reg protect="" name="get_ch">
    <bits access="r" name="ch_to_use" pos="3:0" rst="0">
      <comment>This field indicates which standard channel to use.
      <br /> Before using a channel, the CPU read this register to know which channel must be used.
      After reading this registers, the channel is to be regarded as
      busy.
      <br /> After reading this register, if the CPU doesn't want to use
      the specified channel, the CPU must write a disable in the control
      register of the channel to release the channel.
      <br />0000 = use Channel0
      <br />0001 = use Channel1
      <br />0010 = use Channel2 
      <br /> ...
      <br />0111 = use Channel7
      <br />1111 = all channels are busy</comment>
      <options><mask/><shift/><default/></options>
    </bits>
  </reg>

  <reg protect="r" name="dma_status">
    <bits access="r" name="ch_enable" pos="SYS_IFC_STD_CHAN_NB+SYS_IFC_RFSPI_CHAN-1:0" rst="0">
      <comment>This register indicates which channel is enabled. It is a copy
      of the enable bit of the control register of each channel. One bit per
      channel, for example:
      <br />0000_0000 = All channels disabled 
      <br />0000_0001 = Ch0 enabled 
      <br />0000_0010 = Ch1 enabled 
      <br />0000_0100 = Ch2 enabled 
      <br />0000_0101 = Ch0 and Ch2 enabled 
      <br />0000_0111 = Ch0, Ch1 and Ch2 enabled 
      <br />1111_1111 = all channels enabled</comment>
    </bits>

    <bits access="r" name="ch_busy" pos="SYS_IFC_STD_CHAN_NB-1+16:16" rst="0">
      <comment>This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel</comment>
    </bits>
  </reg>

  <reg protect="r" name="debug_status">
    <bits access="r" name="dbg_status" pos="0" rst="1">
      <comment>Debug Channel Status .<br />0= The debug channel is running
      (not idle) <br />1= The debug channel is in idle mode</comment>
    </bits>
  </reg>

  <hole size="32" />

  

  <struct count="SYS_IFC_STD_CHAN_NB" name="std_ch">
    <reg protect="rw" name="control">
      <bits access="w" name="enable" pos="0" rst="no">
        <comment>Channel Enable, write one in this bit enable the channel.
        <br />When the channel is enabled, for a peripheral to memory transfer
        the DMA wait request from peripheral to start transfer. </comment>
      </bits>

      <bits access="w" name="disable" pos="1" rst="no">
        <comment>Channel Disable, write one in this bit disable the channel.
        <br />When writing one in this bit, the current AHB transfer and
        current APB transfer (if one in progress) is completed and the channel
        is then disabled. </comment>
      </bits>


      <bits access="rw" name="ch_rd_hw_exch" pos="2" rst="0">
        <comment>Exchange the read data from fifo halfword MSB or LSB
        <br />
    </comment>
      </bits>

      <bits access="rw" name="ch_wr_hw_exch" pos="3" rst="0">
        <comment>Exchange the write data to fifo  halfword MSB or LSB
        <br />
    </comment>
      </bits>


      <bits access="rw" name="autodisable" pos="4" rst="1">
        <comment>Set Auto-disable mode<br /> 0 = when TC reach zero the
        channel is not automatically released.<br /> 1 = At the end of the
        transfer when TC reach zero the channel is automatically disabled. the
        current channel is released.</comment>
      </bits>
      
      <bits access="rw" name="Size" pos="5" rst="0">
        <comment>Peripheral Size
            <br /> 0= 8-bit peripheral
            <br /> 1= 32-bit peripheral
        </comment>
      </bits>

      <bits access="rw" name="req_src" pos="12:8" rst="0x7" display="hex">
        <options linkenum="Sys_Ifc_Request_IDs"> 
        
          <shift/><mask/><default/>
        </options>

        <comment>Select DMA Request source</comment>
      </bits>

        <bits access="rw" name="flush" pos="16" rst="0">
        <comment>When one, flush the internal FIFO channel. 
        <br />This bit must be used only in case of Rx transfer. Until this bit is 1, the APB
              request is masked. The flush doesn't release the channel. 
        <br /> Before writting back this bit to zero the internal fifo must empty.
        </comment>
      </bits>

        <bits access="rw" name="max_burst_length" pos="18:17" rst="00">
        <comment>Set the MAX burst length for channel 0,1. 
                 This bit field is only used in channel 0~1, for channel 2~6, it is reserved.  
        <br /> The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. 
        <br /> .
        </comment>



        
      </bits>
    </reg>

    <reg protect="r" name="status">
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>Enable bit, when '1' the channel is running  </comment>
      </bits>

      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>The internal channel fifo is empty </comment>
      </bits>
    </reg>

    <reg protect="rw" name="start_addr">
      <bits access="rw" name="start_addr"
            pos="NB_BITS_ADDR-1:SYS_IFC_ADDR_ALIGN" rst="0xFFFFFFF" display="hex">
        <comment>AHB Address. This field represent the start address of the
        transfer.
        <br />For a 32-bit peripheral, this address must be aligned 32-bit.
        </comment>
      </bits>
    </reg>

    <reg protect="rw" name="tc">
      <bits access="rw" name="tc" pos="SYS_IFC_TC_LEN-1:0" rst="0x7FFFFF" display="hex">
        <comment>Transfer Count, this field indicated the transfer size in bytes to perform.
        <br />During a transfer a write in this register add the new value to the current TC. 
        <br />A read of this register return the current current transfer count.
        </comment>
      </bits>
    </reg>
  </struct>
  
  

  <struct count="SYS_IFC_RFSPI_CHAN" name="rfspi_ch">
  <reg protect="rw" name="ch_rfspi_control">
      <bits access="s" name="enable" pos="0" rst="no">
        <comment>Channel Enable, write one in this bit enable the channel.
        <br />This channel works only in fifo mode. </comment>
      </bits>

      <bits access="c" name="disable" pos="1" rst="no">
        <comment>Channel Disable, write one in this bit to disable the channel.
        </comment>
      </bits>
    </reg>

    <reg protect="r" name="ch_rfspi_status">
      <bits access="r" name="enable" pos="0" rst="0">
        <comment>Enable bit, when '1' the channel is running  </comment>
      </bits>

      <bits access="r" name="fifo_empty" pos="4" rst="1">
        <comment>The internal channel fifo is empty </comment>
      </bits>
      
      <bits access="r" name="fifo_level" pos="12:8" rst="0">
        <comment>Internal fifo level </comment>
      </bits>
    </reg>

    <reg protect="rw" name="ch_rfspi_start_addr">
      <bits access="rw" name="start_AHB_addr"
            pos="NB_BITS_ADDR-1:SYS_IFC_ADDR_ALIGN" rst="0xFFFFFFF" display="hex">
        <comment>AHB Start Address. <br />This field represent the start address of the fifo.
                 The start address must 32-bit aligned.
        </comment>
      </bits>
    </reg>
    
    <reg protect="rw" name="ch_rfspi_end_addr">
      <bits access="rw" name="end_AHB_addr"
            pos="NB_BITS_ADDR-1:SYS_IFC_ADDR_ALIGN" rst="0xFFFFFFF" display="hex">
        <comment>AHB End Address. <br />This field represent the last address of the fifo (it is the first address not used in the fifo). <br />The end address must 32-bit aligned.
        </comment>
      </bits>
    </reg>


    <reg protect="rw" name="ch_rfspi_tc">
      <bits access="rw" name="tc" pos="13:0" rst="0x0" display="hex">
        <comment>Transfer Count, transfer size in bytes. <br />This bit
        indicated the transfer size in bytes to perform. Up to 16kbytes per
        transfer. <br />During a transfer a write in this register add the new
        value to the current TC. A read of this register return the current
        current transfer count.</comment>
      </bits>
    </reg>
  </struct>
</module>

</archive>
<archive relative = "sys_irq.xml">

<include file="globals.xml"/>

<module name="sys_irq" category="System">
    
    
    <enum name="XCPU_Irq_Lines">
        <entry name="XCpu_Main_Irq_Line"><comment>XCPU Irq Lines</comment></entry>
        <entry name="XCpu_Wdt_Irq_Line" value="1"/>
        
        <entry name="XCpu_Page_Spy_Irq_Line" value="3"/>
        <entry name="XCpu_Debug_Irq_Line" value="4"/>
        <entry name="XCpu_Host_Irq_Line"/>
    </enum>


    <reg name="Cause" protect="r">
        <comment>If cause is not null and interrupt are enabled then the interrupt line 0 is driven on the system CPU.
            <br/>The cause for the Irq sources, one bit for each module's irq source.
            <br/>The cause is the actual Irq source masked by the mask register.
        </comment>
        <bits name="Cause" pos="31:0" access="r" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Cause_Extra" protect="r">
        <comment>If cause is not null and interrupt are enabled then the interrupt line 0 is driven on the system CPU.
            <br/>The cause for the Irq sources, one bit for each module's irq source.
            <br/>The cause is the actual Irq source masked by the mask register.
        </comment>
        <bits name="Cause_Extra" pos="SYS_NB_IRQ-33:0" access="r" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="32"/>
    </reg>
    <reg name="Status" protect="r">
        <comment>The status for the level Irq sources, one bit for each module's irq source.
            <br/>The status reflect the actual Irq source.
        </comment>
        <bits name="Status" pos="31:0" access="r" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Status_Extra" protect="r">
        <comment>The status for the level Irq sources, one bit for each module's irq source.
            <br/>The status reflect the actual Irq source.
        </comment>
        <bits name="Status_Extra" pos="SYS_NB_IRQ-33:0" access="r" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="32"/>
    </reg>
    <reg name="Mask_Set" protect="rw">
        <comment>Writing '1' sets the corresponding bit in the mask register to '1'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Mask_Set" pos="31:0" access="rs" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Mask_Set_Extra" protect="rw">
        <comment>Writing '1' sets the corresponding bit in the mask register to '1'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Mask_Set_Extra" pos="SYS_NB_IRQ-33:0" access="rs" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="32"/>
    </reg>
    <reg name="Mask_Clear" protect="rw">
        <comment>Writing '1' clears the corresponding bit in the mask register to '0'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Mask_Clr" pos="31:0" access="rc" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Mask_Clear_Extra" protect="rw">
        <comment>Writing '1' clears the corresponding bit in the mask register to '0'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Mask_Clr_Extra" pos="SYS_NB_IRQ-33:0" access="rc" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="32"/>
    </reg>
    <reg name="NonMaskable" protect="rw">
        <bits name="Main_IRQ" pos="10" access="r" rst="0">
            <comment>This is the Main Irq source it drive the system CPU interrupt line 0.
                <br/>This bit comes from the modules irq and is masked by the Mask and SC registers.
            </comment>
        </bits>
        <bits name="WDT_IRQ" pos="11" access="r" rst="0">
            <comment>This is the WDT Irq source it drive the system CPU interrupt line 1.
                <br/>This bit comes from watchdog module.
            </comment>
        </bits>
        <bits name="Page_Spy_IRQ" pos="13" access="r" rst="0">
            <comment>This is the Page Spy Irq source it drive the system CPU interrupt line 3.
                <br/>This bit is controlled by the page spy module.
            </comment>
        </bits>
        <bits name="Debug_IRQ" pos="14" access="rw" rst="0">
            <comment>This is the debug Irq source, the value written here drives the system CPU interrupt line 4.
            </comment>
        </bits>
        <bits name="Host_IRQ" pos="15" access="r" rst="0">
            <comment>This is the Host Irq source it drive the system CPU interrupt line 5.
                <br/>This bit is controlled by the host internal register.
            </comment>
        </bits>
        <bits name="IntEnable_Status" pos="31" access="r" rst="1">
            <comment>Status of the Interrupt enable semaphore bit.
            </comment>
        </bits>
   </reg>
    <reg name="SC" protect="">
        <bits name="IntEnable" pos="0" access="rw" rst="1">
            <comment>Interrupt enable semaphore, used for critical section.
                <br/>Read returns its value and then clears it to '0' disabling interrupts.
                <br/>Write the read value to restore the previous state, this will exit the critical section.
            </comment>
        </bits>
    </reg>
    <reg name="WakeUp_Mask" protect="rw">
        <comment>Each bit to '1' in that registers allows the correcponding interrupt to wake up the System CPU (i.e.: Reenable it's clock, see CLOCK_SYS_ENABLE and CLOCK_SYS_DISABLE registers in sys_ctrl registers section)
        </comment>
        <bits name="WakeUp_Mask" pos="31:0" access="rw" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="WakeUp_Mask_Extra" protect="rw">
        <comment>Each bit to '1' in that registers allows the correcponding interrupt to wake up the System CPU (i.e.: Reenable it's clock, see CLOCK_SYS_ENABLE and CLOCK_SYS_DISABLE registers in sys_ctrl registers section)
        </comment>
        <bits name="WakeUp_Mask_Extra" pos="SYS_NB_IRQ-33:0" access="rw" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="32"/>
    </reg>
    <reg name="Cpu_Sleep" protect="w">
        <bits name="Sleep" pos="0" access="w" rst="0">
            <comment>Writing '1' to this bit will put the XCPU to sleep (i.e.: Disable it's clock, see CLOCK_SYS_ENABLE and CLOCK_SYS_DISABLE registers in sys_ctrl registers section)
            </comment>
        </bits>
    </reg>
    <reg name="Pulse_Mask_Set" protect="rw">
        <comment>Writing '1' sets the corresponding bit in the mask register to '1'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Pulse_Mask_Set" pos="SYS_NB_IRQ_PULSE-1:0" access="rs" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Pulse_Mask_Clr" protect="rw">
        <comment>Writing '1' clears the corresponding bit in the mask register to '0'.
            <br/>Reading gives the value of the mask register.
        </comment>
        <bits name="Pulse_Mask_Clr" pos="SYS_NB_IRQ_PULSE-1:0" access="rc" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Pulse_Clear" protect="rw">
        <comment>Writing '1' clears the corresponding Pulse IRQ.
            <br/>Pulse IRQ are set by the modules and cleared here.
        </comment>
        <bits name="Pulse_Clr" pos="SYS_NB_IRQ_PULSE-1:0" access="c" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>
    <reg name="Pulse_Status" protect="r">
        <comment>The status for the Pulse Irq sources, one bit for each module's irq source.
            <br/>The status reflect the actual Irq source.
        </comment>
        <bits name="Status" pos="SYS_NB_IRQ_PULSE-1:0" access="r" rst="0" cut="1" cutprefix="" cutenum="Sys_Irq_Id" cutstart="0"/>
    </reg>

</module>

</archive>
<archive relative = "sys_mem.xml">
  <var name="SYS_ROM_SIZE"   value="40*1024" />       
  <var name="SYS_RAM_SIZE"   value="64*1024" />       
  <var name="PSRAM_SIZE"     value="4*1024*1024" />   
  <var name="FLASH_SIZE"     value="4*1024*1024" />   

  
  <module name="sys_rom" category="System">
    <memory name="rom_array" size="SYS_ROM_SIZE">
      <comment>System Rom Space
        <br/>This rom is used for XCPU boot code.
      </comment>
    </memory>
  </module>

  
  <module name="sys_ram" category="System">
    <memory name="ram_array" size="SYS_RAM_SIZE">
      <comment>System Ram Space
        <br/>
      </comment>
    </memory>
  </module>

  
  <module name="psram" category="System">
    <memory name="ram_array" size="PSRAM_SIZE">
      <comment>PSRAM Space
        <br/> In-package PSRAM
      </comment>
    </memory>
  </module>

  
  <module name="flash" category="System">
    <memory name="ram_array" size="FLASH_SIZE">
      <comment>FLASH Space
        <br/> In-package FLASH
      </comment>
    </memory>
  </module>




</archive>
<archive relative = "tcu.xml">

<module name="tcu" category="Modem">

    
    <var name="NB_TCO" value="12"/> 
    <var name="NB_TCU_PROG_EVENTS" value="60"/>

    <enum name="Internal_TCO_mapping">
        <entry name="TCO_GMSK_ON" value="6"><comment>Internal TCO mapping</comment></entry>
        <entry name="TCO_TX_OEN"/>
        <entry name="TCO_TX_ON"/>
        <entry name="TCO_RX_ON"/>
        <entry name="TCO_RX_DEC_ON"/>
        <entry name="TCO_PDN"/>
    </enum>

    <enum name="TCU_Event">
        
        <entry name="Clr_TCO_0" value="0"><comment>Clear TCO 0 : set the TCO 0 to the inactive state<br/>To clear TCO n, use event 2*n</comment></entry>
        <entry name="Set_TCO_0" value="1"><comment>Set TCO 0 : set the TCO 0 to the active state<br/>To set TCO n, use event 2*n+1</comment></entry>
        <entry name="Clr_TCO_1"><comment>...</comment></entry>
        <entry name="Set_TCO_1"/>
        <entry name="Clr_TCO_2"/>
        <entry name="Set_TCO_2"/>
        <entry name="Clr_TCO_3"/>
        <entry name="Set_TCO_3"/>
        <entry name="Clr_TCO_4"/>
        <entry name="Set_TCO_4"/>
        <entry name="Clr_TCO_5"/>
        <entry name="Set_TCO_5"/>
        
        
        <entry name="Stop_GMSK" value="TCO_GMSK_ON*2"><comment>stop modulation</comment></entry>
        <entry name="Start_GMSK" value="TCO_GMSK_ON*2+1"><comment>starts modulation and output on IQ DAC</comment></entry>
        <entry name="HighZ_IQ_DAC" value="TCO_TX_OEN*2"/>
        <entry name="Drive_IQ_DAC" value="TCO_TX_OEN*2+1"/>
        <entry name="disable_IQ_DAC" value="TCO_TX_ON*2"/>
        <entry name="enable_IQ_DAC" value="TCO_TX_ON*2+1"/>
        <entry name="disable_IQ_ADC" value="TCO_RX_ON*2"><comment>disable IQ ADC</comment></entry>
        <entry name="enable_IQ_ADC" value="TCO_RX_ON*2+1"><comment>enable IQ ADC</comment></entry>
        <entry name="stop_RFin_record" value="TCO_RX_DEC_ON*2"><comment>stop recording IQ samples</comment></entry>
        <entry name="start_RFin_record" value="TCO_RX_DEC_ON*2+1"><comment>start recording IQ samples</comment></entry>
        <entry name="Clr_PDN" value="TCO_PDN*2"><comment>Clear RF_PDN</comment></entry>
        <entry name="Set_PDN" value="TCO_PDN*2+1"><comment>Set RF_PDN</comment></entry>
        
        <entry name="SEND_SPI_CMD" value="NB_TCO*2"><comment>Send RF spi command</comment></entry>
        <entry name="NEXT_GAIN"/>
        <entry name="FIRST_GAIN"/>
        
        <entry name="NEXT_FC"/>
        
        <entry name="PA_RAMP0"><comment>Start Ramp 0</comment></entry>
        <entry name="PA_RAMP1"><comment>Start Ramp 1</comment></entry>
        <entry name="PA_RAMP2"><comment>Start Ramp 2</comment></entry>
        <entry name="PA_RAMP3"><comment>Start Ramp 3</comment></entry>
        <entry name="PA_RAMP4"><comment>Start Ramp 4</comment></entry>
        <entry name="RX_SOC"/>
        <entry name="DIGRF_STB"/>
        
        <entry name="BCPU_TCU_IRQ0"><comment>Trigger BCPU TCU irq 0</comment></entry>
        <entry name="BCPU_TCU_IRQ1"><comment>Trigger BCPU TCU irq 1</comment></entry>
        
        <entry name="XCPU_TCU_IRQ0"><comment>Trigger XCPU TCU irq 0</comment></entry>
        <entry name="XCPU_TCU_IRQ1"><comment>Trigger XCPU TCU irq 1</comment></entry>
        
        <entry name="WAKEUP_DONE"><comment>End of the WakeUp Mode</comment></entry>
        
        <entry name="RFSPI_START"><comment>Start of Rf_spi Transfer</comment></entry>
        <entry name="RFSPI_END"><comment>End of Rf_spi Transfer</comment></entry>
        <entry name="NO_EVENT" value="63"/> 
    </enum>

    
    <reg name="Ctrl" protect="rw">
        <bits name="Load_Val" pos="13:0" access="rw" rst="all1" display="hex">
            <comment>Value loaded into the TCU counter when the Load bit is set to 1
            </comment>
        </bits>
        <bits name="Enable" pos="16" access="rw" rst="0">
            <options>
                <option name="Disabled" value="0"/>
                <option name="Enabled" value="1"/>
            </options>
        </bits>
        <bits name="Load" pos="20" access="w" rst="0">
            <comment>Writing a 1 to this bit will load the TCU with the TCU loadval value
                <br/>Writing a 0 has no effect
            </comment>
        </bits>
        <bits name="NoLatch" pos="28" access="rw" rst="0">
            <options>
                <option name="Normal" value="0"><comment>Normal Behavior, The programmation area is copied to the active area when the tcu wraps</comment></option>
                <option name="Force_Only" value="1"><comment>The programmation area is copied into the active area only when force latch is used</comment></option>
            </options>
        </bits>
        <bits name="Wakeup_En" pos="30" access="rw" rst="0">
            <comment>Writing a 1 to enable run tcu wakeup function in lowpower skip frame
                <br/>Writing a 0 to disable 
            </comment>
        </bits>
    </reg>
    <reg name="Wrap_Val" protect="rw">
        <bits name="Wrap_Val" pos="13:0" access="rw" rst="all1" display="hex">
            <comment>TCU counter wrap value.
                <br/>The TCU counter returns to 0 when this value is reached
            </comment>
        </bits>
    </reg>
    <reg name="Cur_Val" protect="rw">
        <bits name="Cur_Val" pos="13:0" access="r" display="hex" rst="0">
            <comment>TCU counter current value
            </comment>
        </bits>
    </reg>
    <reg name="Latch" protect="rw">
        <bits name="ForceLatch" pos="7:0" access="w" cut="1" cutprefix="ForceLatch_Area" rst="0">
            <comment>Writing 1 transfer the programmed events to the active area.
            </comment>
        </bits>
        <bits name="Force_NoEvent" pos="16" access="w" rst="0">
            <comment>Writing 1 to this bit with one of the ForceLatch bit will force the corresponding Active Area to receive no events (i.e. clear it) instead of transfering the programmed area.
            </comment>
        </bits>
        <bits name="ClearProgArea" pos="31" access="w" rst="0">
            <comment>Writing 1 clears the Program Area
            </comment>
        </bits>
    </reg>
    <reg name="Setup" protect="rw">
        <bits name="TCO_Polarity" pos="NB_TCO-1:0" access="rw" rst="0" cut="1" cutprefix="POL_TCO">
            <comment>Configure the TCO polarity
            </comment>
            <options>
                <option name="Active High" value="0"/>
                <option name="Active Low" value="1"/>
            </options>
        </bits>
        <bits name="Write_Error" pos="28" access="rc" rst="0">
            <comment>Error Status: become 1 when writing to Program Area while the TCU is coping the Program Area to the Active Area. In this case the write is ignored.
                <br/>Write 1 to clear it.
            </comment>
        </bits>
        <bits name="Debug_Active" pos="31" access="rw" rst="0">
            <comment>This bit allows to access directly the active area for debug purposes
            </comment>
            <options>
                <option name="Normal" value="0"/>
                <option name="Debug" value="1"><comment>the active area is directly mapped instead of the program area.</comment></option>
            </options>
        </bits>
    </reg>
    <reg name="Disable_Event" protect="rw">
        <bits name="Disable_TCO" pos="5:0" access="rw" rst="all1" cut='1' cutprefix="Disable_TCO">
            <comment>Writing 1 disable the events that affect corresponding TCO.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Internal_TCO" pos="11:6" access="rw" rst="all1" cut='1' cutprefix="Disable" cutenum="Internal_TCO_mapping">
            <comment>Writing 1 disable the events that affect corresponding TCO.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Send_Spi_Cmd" pos="12" access="rw" rst="1">
            <comment>Writing 1 disable the events SEND_SPI_CMD.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Next_Gain" pos="13" access="rw" rst="1">
            <comment>Writing 1 disable the events NEXT_GAIN.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_First_Gain" pos="14" access="rw" rst="1">
            <comment>Writing 1 disable the events FIRST_GAIN.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Next_Fc" pos="15" access="rw" rst="1">
            <comment>Writing 1 disable the events NEXT_FC.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Ramp" pos="20:16" access="rw" rst="all1" cut='1' cutprefix="Disable_Ramp">
            <comment>Writing 1 disable the corresponding Ramp event.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Rx_SOC" pos="21" access="rw" rst="1">
            <comment>Writing 1 disable the events RX_SOC.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_DigRF_Strobe" pos="22" access="rw" rst="1">
            <comment>Writing 1 disable the events DIGRF_STB.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Bcpu_Irq" pos="24:23" access="rw" rst="all1" cut='1' cutprefix="Disable_Bcpu_Irq">
            <comment>Writing 1 disable the corresponding BCPU TCU irq event.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Xcpu_Irq" pos="26:25" access="rw" rst="all1" cut='1' cutprefix="Disable_Xcpu_Irq">
            <comment>Writing 1 disable the corresponding XCPU TCU irq event.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_RfSpi_Start" pos="28" access="rw" rst="1">
            <comment>Writing 1 disable the events RFSPI_START.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_RfSpi_End" pos="29" access="rw" rst="1">
            <comment>Writing 1 disable the events RFSPI_END.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Disable_Rf_Spi_Marked_Cmd" pos="31" access="rw" rst="1">
            <comment>Writing 1 disable the marked rf spi commands (cf RF SPI).
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
    </reg>
    <reg name="Enable_Event" protect="rw">
        <bits name="Enable_TCO" pos="5:0" access="rs" rst="all1" cut='1' cutprefix="Enable_TCO">
            <comment>Writing 1 enable the events that affect corresponding TCO.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Internal_TCO" pos="11:6" access="rs" rst="all1" cut='1' cutprefix="Enable" cutenum="Internal_TCO_mapping">
            <comment>Writing 1 enable the events that affect corresponding TCO.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Send_Spi_Cmd" pos="12" access="rs" rst="1">
            <comment>Writing 1 enable the events SEND_SPI_CMD.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Next_Gain" pos="13" access="rs" rst="1">
            <comment>Writing 1 enable the events NEXT_GAIN.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_First_Gain" pos="14" access="rs" rst="1">
            <comment>Writing 1 enable the events FIRST_GAIN.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Next_Fc" pos="15" access="rs" rst="1">
            <comment>Writing 1 enable the events NEXT_FC.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Ramp" pos="20:16" access="rs" rst="all1" cut='1' cutprefix="Enable_Ramp">
            <comment>Writing 1 enable the corresponding Ramp event.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Rx_SOC" pos="21" access="rs" rst="1">
            <comment>Writing 1 enable the events RX_SOC.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_DigRF_Strobe" pos="22" access="rs" rst="1">
            <comment>Writing 1 enable the events DIGRF_STB.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Bcpu_Irq" pos="24:23" access="rs" rst="all1" cut='1' cutprefix="Enable_Bcpu_Irq">
            <comment>Writing 1 enable the corresponding BCPU TCU irq event.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Xcpu_Irq" pos="26:25" access="rs" rst="all1" cut='1' cutprefix="Enable_Xcpu_Irq">
            <comment>Writing 1 enable the corresponding XCPU TCU irq event.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_RfSpi_Start" pos="28" access="rw" rst="1">
            <comment>Writing 1 enable the events RFSPI_START.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_RfSpi_End" pos="29" access="rw" rst="1">
            <comment>Writing 1 enable the events RFSPI_END.
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
        <bits name="Enable_Rf_Spi_Marked_Cmd" pos="31" access="rs" rst="1">
            <comment>Writing 1 enable the marked rf spi commands (cf RF SPI).
                <br/>Reading return the actual enable state.
            </comment>
        </bits>
    </reg>
    <reg name="Set_TCO" protect="rw">
        <bits name="Set_TCO" pos="NB_TCO-1:0" access="s" cut='1' cutprefix="Set_TCO" rst="0">
            <comment>Writing 1 set corresponding TCO to the active state (The actual line state also depends on TCO_Polarity).
                <br/>Reading returns the actual state of all TCOs.
            </comment>
        </bits>
    </reg>
    <reg name="Clr_TCO" protect="rw">
        <bits name="Clr_TCO" pos="NB_TCO-1:0" access="c" cut='1' cutprefix="Clr_TCO" rst="0">
            <comment>Writing 1 set corresponding TCO to the inactive state (The actual line state also depends on TCO_Polarity).
                <br/>Reading returns the actual state of all TCOs.
            </comment>
        </bits>
    </reg>

    <reg name="Cfg_Clk_Div" protect="rw">
        <bits name="TCU_Clk_Same_Sys" pos="29" access="rw" rst="0">
            <comment>Enable Clk_TCU same with Clk_Sys.
            </comment>
            <options>
                <option name="Disabled" value="0"/>
                <option name="Enabled" value="1"/>
            </options>
        </bits>
        <bits name="Enable_DAI_Simple_208K" pos="30" access="rw" rst="0">
            <comment>Enable the 208kHz pulse generation for DAI Simple. (!) When enabling the clock field Enable_Qbit should also be enabled.
            </comment>
            <options>
                <option name="Disabled" value="0"/>
                <option name="Enabled" value="1"/>
            </options>
        </bits>
        <bits name="Enable_Qbit" pos="31" access="rw" rst="0">
            <comment>Enable the Quarter bit generation (required for normal TCU operation)
            </comment>
            <options>
                <option name="Disabled" value="0"/>
                <option name="Enabled" value="1"/>
            </options>
        </bits>
    </reg>
    <reg name="TCU_IRQ" protect="rw">
        <bits name="TCU_Sync_Done_Cause" pos="0" access="rc" rst="0">
            <comment>1 when the IRQ was triggered because the tcu counter synchronization is done.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bitgroup name="TCU_IRQ_Cause">
            <entry ref="TCU_Sync_Done_Cause"/>
        </bitgroup>

        <bits name="TCU_Sync_Done_Status" pos="16" access="rc" rst="0">
            <comment>1 when the tcu counter synchronization is done.
                <br/>Write 1 in cause or status bit to clear.
            </comment>
        </bits>
        <bitgroup name="TCU_IRQ_Status">
            <entry ref="TCU_Sync_Done_Status"/>
        </bitgroup>
    </reg>
    <reg name="TCU_IRQ_Mask" protect="rw">
        <bits name="TCU_Sync_Done_Mask" pos="0" access="rw" rst="0">
            <comment>when 1 the LPS_IRQ_TCU_Sync_Done is enabled.
            </comment>
        </bits>
        <bitgroup name="TCU_IRQ_Mask">
            <entry ref="TCU_Sync_Done_Mask"/>
        </bitgroup>
    </reg>
    <reg name="GLOBAL_SYNC_CTRL" protect="rw">
        <bits name="TCU_Sync_Enable" pos="0" access="rw" rst="0">
            <comment>enable sync tcu counter to global counter function.
            </comment>
        </bits>
        <bits name="TCU_Sync_Value" pos="15:2" access="rw" rst="0">
            <comment>tcu counter load value when synchronized.
            </comment>
        </bits>
    </reg> 
    <reg name="TCO_DBG_SEL" protect="rw">
        <bits name="tco_dbg0_sel" pos="3:0" access="rw" rst="0">
        </bits>
        <bits name="tco_dbg1_sel" pos="7:4" access="rw" rst="0">
        </bits>
    </reg>
    <reg name="Rfspi_Conflict_Val" protect="rw">
        <bits name="Rfspi_Conflict_Val" pos="13:0" access="r" display="hex" rst="0">
            <comment>TCU counter value when rfspi conflict happen
            </comment>
        </bits>

    </reg>
    <hole size="1568"/>
    <reg name="Event" protect="rw" count="NB_TCU_PROG_EVENTS">
        <bits name="Event_Time" pos="13:0" access="rw" rst="all1">
            <comment>The event Id will be executed when the TCU counter reaches the value programmed in Event time field of this register.
            </comment>
        </bits>
        <bits name="Event_Id" pos="21:16" access="rw" rst="all1">
            <comment>Event to be executed when the TCU counter reaches the programmed event time.
                <br/>
            </comment>
            <options linkenum="TCU_Event">
                <default />
            </options>
        </bits>
    </reg>

</module>

</archive>
<archive relative = "timer.xml">

<module name="timer" category="System">
    <var name = "NB_INTERVAL" value="1"/>
    <var name = "INT_TIMER_NB_BITS" value="24"/>
    <var name = "WD_TIMER_NB_BITS" value="24"/>
    <var name = "HW_TIMER_NB_BITS" value="32"/>
    <var name = "TIM_MAXVAL" value="0xffffff"/>

    <reg name="OSTimer_Ctrl" protect="rw">
        <bits name="LoadVal" pos="23:0" access="rw" rst="0">
            <comment>Value loaded to OS timer.
            </comment>
            <options>
                <mask/>
                <shift/>
            </options>
        </bits>
        <bits name="Enable" pos="24" access="rw" rst="0">
            <comment>Write '1' to this bit will enable OS timer.
                <br/>When read, the value is what we have written to this bit, it changes immediately  after been written.
            </comment>
        </bits>
        <bits name="Enabled" pos="25" access="r" rst="0">
            <comment>Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock.
                <br/>
                <br/>'1' indicates OS timer enabled.
                <br/>'0' indicates OS timer not enabled.
            </comment>
        </bits>
        <bits name="Cleared" pos="26" access="r" rst="0">
            <comment>Read this bit will get the information if OS timer interruption clear operation is finished or not.
                <br/>
                <br/>'1' indicates OS timer interruption clear operation is on going.
                <br/>'0' indicates no OS timer interruption clear operation is on going.
            </comment>
        </bits>
        <bits name="Repeat" pos="28" access="rw" rst="0">
            <comment>Write '1' to this bit will set OS timer to repeat mode.
                <br/>When read, get the information if OS timer is in repeat mode.
                <br/>
                <br/>'1' indicates OS timer in repeat mode.
                <br/>'0' indicates OS timer not in repeat mode.
            </comment>
        </bits>
        <bits name="Wrap" pos="29" access="rw" rst="0">
            <comment>Write '1' to this bit will set OS timer to wrap mode.
                <br/>When read, get the information if OS timer is in wrap mode.
                <br/>
                <br/>'1' indicates OS timer in wrap mode.
                <br/>'0' indicates OS timer not in wrap mode.
            </comment>
        </bits>
        <bits name="Load" pos="30" access="rw" rst="0">
            <comment>Write '1' to this bit will load the initial value to OS timer.
            </comment>
        </bits>
    </reg>
    <reg name="OSTimer_CurVal" protect="rw">
        <bits name="CurVal" pos="31:0" access="r" rst="-">
            <comment>Current value of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped.
            </comment>
        </bits>
    </reg>
    <reg name="WDTimer_Ctrl" protect="rw">
        <bits name="Start" pos="0" access="s" rst="0">
            <comment>Write '1' to this bit will enable watchdog timer and Load it with WDTimer_LoadVal.
            </comment>
        </bits>
        <bits name="Stop" pos="4" access="c" rst="0">
            <comment>Write '1' to this bit will stop watchdog timer.
            </comment>
        </bits>
        <bits name="ReLoad" pos="16" access="w" rst="0">
            <comment>Write '1' to this bit will load WDTimer_LoadVal value to watchdog timer.
                <br/>Use this bit to implement the watchog keep alive.
            </comment>
        </bits>

        <bits name="WDEnabled" pos="8" access="r" rst="0">
            <comment>Read this bit will get the information if watchdog timer is really enabled or not. This bit will change only after the next front of 32 KHz system clock.
                <br/>
                <br/>'1' indicates watchdog timer is enabled, if current watchdog timer value reaches 0, the system will be reseted.
                <br/>'0' indicates watchdog timer is not enabled.
            </comment>
        </bits>
    </reg>
    <reg name="WDTimer_LoadVal" protect="rw">
        <bits name="LoadVal" pos="WD_TIMER_NB_BITS-1:0" access="rw" rst="-">
            <comment>Load value of watchdog timer. Number of 32kHz Clock before Reset.
                <br/>
            </comment>
        </bits>
    </reg>
    <reg name="HWTimer_Ctrl" protect="rw">
        <bits name="Interval_En" pos="8" access="rw" rst="0">
            <comment>This bit enables interval IRQ mode.
                <br/>
                <br/>'0': hw delay timer does not generate interval IRQ.
                <br/>'1': hw delay timer generate an IRQ each interval.
            </comment>
        </bits>
        <bits name="Interval" pos="1:0" access="rw" rst="00">
            <comment> interval of generating an HwTimer IRQ. 
                <br/>
                <br/>"00": interval of 1/8 second.
                <br/>"01": interval of 1/4 second.
                <br/>"10": interval of 1/2 second.
                <br/>"11": interval of 1 second.
            </comment>
        </bits>
    </reg>
    <reg name="HWTimer_CurVal" protect="rw">
        <bits name="CurVal" pos="31:0" access="r" rst="0">
            <comment>Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF.
            </comment>
        </bits>
    </reg>
    <reg name="Timer_Irq_Mask_Set" protect="rw">
        <bits name="OSTimer_Mask" pos="0" access="rs" rst="0">
            <comment>Set mask for OS timer IRQ.
            </comment>
        </bits>
        <bits name="HWTimer_Wrap_Mask" pos="1" access="rs" rst="0">
            <comment>Set mask for hardwre delay timer wrap IRQ.
            </comment>
        </bits>
        <bits name="HWTimer_Itv_Mask" pos="2" access="rs" rst="0">
            <comment>Set mask for hardwre delay timer interval IRQ.
            </comment>
        </bits>
    </reg>
    <reg name="Timer_Irq_Mask_Clr" protect="rw">
        <bits name="OSTimer_Mask" pos="0" access="rc" rst="0">
            <comment>Clear mask for OS timer IRQ.
            </comment>
        </bits>
        <bits name="HWTimer_Wrap_Mask" pos="1" access="rc" rst="0">
            <comment>Clear mask for hardwre delay timer wrap IRQ.
            </comment>
        </bits>
        <bits name="HWTimer_Itv_Mask" pos="2" access="rc" rst="0">
            <comment>Clear mask for hardwre delay timer interval IRQ.
            </comment>
        </bits>
    </reg>
    <reg name="Timer_Irq_Clr" protect="rw">
        <bits name="OSTimer_Clr" pos="0" access="c" rst="0">
            <comment>Clear OS timer IRQ.
            </comment>
        </bits>
        <bits name="HWTimer_Wrap_Clr" pos="1" access="c" rst="0">
            <comment>Clear hardware delay timer wrap IRQ.
            </comment>
        </bits>
        <bits name="HWTimer_Itv_Clr" pos="2" access="c" rst="0">
            <comment>Clear hardware delay timer interval IRQ.
            </comment>
        </bits>
    </reg>
    <reg name="Timer_Irq_Cause" protect="rw">
        <bits name="OSTimer_Cause" pos="0" access="r" rst="0">
            <comment>OS timer IRQ cause.
            </comment>
        </bits>
        <bits name="HWTimer_Wrap_Cause" pos="1" access="r" rst="0">
            <comment>hardware delay timer wrap IRQ cause.
            </comment>
        </bits>
        <bits name="HWTimer_Itv_Cause" pos="2" access="r" rst="0">
            <comment>hardware delay timer interval IRQ cause.
            </comment>
        </bits>
        <bits name="OSTimer_Status" pos="16" access="r" rst="0">
            <comment>OS timer IRQ status.
            </comment>
        </bits>
        <bits name="HWTimer_Wrap_Status" pos="17" access="r" rst="0">
            <comment>hardware delay timer wrap IRQ status.
            </comment>
        </bits>
        <bits name="HWTimer_Itv_Status" pos="18" access="r" rst="0">
            <comment>hardware delay timer interval IRQ status.
            </comment>
        </bits>
        <bitgroup name="Other_Tims_irq">
            <entry ref="HWTimer_Wrap_Cause"/>
            <entry ref="HWTimer_Itv_Cause"/>
        </bitgroup>
    </reg>
</module>

</archive>

<archive relative = "uart.xml">
<module name="uart" category="Periph">
  <var  name="UART_RX_FIFO_SIZE"    value="32"  />
  <var  name="UART_TX_FIFO_SIZE"    value="16"  />
  <var  name="NB_RX_FIFO_BITS"      value="5"   />
  <var  name="NB_TX_FIFO_BITS"      value="4"   />

  
  <reg protect="rw" name="ctrl">
    <bits access="rw" name="Enable" pos="0" rst="0">
      <options>
        <option name="DISABLE" value="0" />

        <option name="ENABLE" value="1" />

        <default />
      </options>

      <comment>Allows to turn off the UART:<br />0 = Disable<br />1 = Enable
      </comment>
    </bits>

    <bits access="rw" name="Data Bits" pos="1" rst="0">
      <options>
        <option name="7_BITS" value="0" />

        <option name="8_BITS" value="1" />

        <default />
      </options>

      <comment>Number of data bits per character (least significant bit
      first):<br />0 = 7 bits<br />1 = 8 bits </comment>
    </bits>

    <bits access="rw" name="Tx Stop Bits" pos="2" rst="0">
      <options>
        <option name="1_BIT" value="0" />

        <option name="2_BITS" value="1" />

        <default />
      </options>

      <comment>Stop bits controls the number of stop bits transmitted. Can
      receive with one stop bit (more inaccuracy can be compensated with two
      stop bits when divisor mode is set to 0).<br />0 = one stop bit is
      transmitted in the serial data.<br />1 = two stop bits are generated and
      transmitted in the serial data out. </comment>
    </bits>

    <bits access="rw" name="Parity Enable" pos="3" rst="0">
      <options>
        <option name="NO" value="0" />

        <option name="YES" value="1" />

        <default />
      </options>

      <comment> Parity is enabled when this bit is set. </comment>
    </bits>

    <bits access="rw" name="Parity Select" pos="5:4" rst="0">
      <options>
        <option name="ODD" value="0" />

        <option name="EVEN" value="1" />

        <option name="SPACE" value="2" />

        <option name="MARK" value="3" />

        <default />
      </options>

      <comment> Controls the parity format when parity is enabled:<br />00 =
      an odd number of received 1 bits is checked, or transmitted (the parity
      bit is included).<br />01 = an even number of received 1 bits is checked
      or transmitted (the parity bit is included).<br />10 = a space is
      generated and received as parity bit.<br />11 = a mark is generated and
      received as parity bit. </comment>
    </bits>

    <bits access="rw" name="auto_enable" pos="8" rst="0">
      <comment> Controls whether enable or disable auto baud rate function. <br />0 = disable auto baud rate function 
      <br />1 = enable auto baud rate function </comment>
    </bits>

    <bits access="rw" name="sync_char_sel" pos="11" rst="0">
      <comment> Controls auto baud rate char is AT or at . <br />0 = char is AT 
      <br />1 = char is at </comment>
    </bits>

    <bits access="rw" name="Divisor Mode" pos="20" rst="0">
      <comment>Selects the divisor value used to generate the baud rate
      frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA
      is enable, this bit is ignored and the divisor used will be 16.<br />0 =
      (BCLK = SCLK / 4)<br />1 = (BCLK = SCLK / 16) </comment>
    </bits>

    <bits access="rw" name="IrDA Enable" pos="21" rst="0">
      <comment>When set, the UART is in IrDA mode and the baud rate divisor
      used is 16 (see UART Operation for details). </comment>
    </bits>

    <bits access="rw" name="DMA Mode" pos="22" rst="0">
      <options>
        <option name="DISABLE" value="0" />

        <option name="ENABLE" value="1" />

        <default />
      </options>

      <comment>Enables the DMA signaling for the Uart_Dma_Tx_Req_H and
      Uart_Dma_Rx_Req_H to the IFC. </comment>
    </bits>
    
    <bits access="rw" name="Auto Flow Control" pos="23" rst="0">
      <options>
        <option name="ENABLE" value="1" />
        
        <option name="DISABLE" value="0" />
        
        <default />
      </options>
      <comment>Enables the auto flow control. Uart_RTS is controlled by the Rx
      RTS bit and the UART Auto Control Flow System. If Uart_CTS
      become inactive high, the Tx data flow is stopped. </comment>
    </bits>

    <bits access="rw" name="Loop Back Mode" pos="24" rst="0">
      <comment>When set, data on the Uart_Tx line is held high, while the
      serial output is looped back to the serial input line, internally. In
      this mode all the interrupts are fully functional. This feature is used
      for diagnostic purposes. Also, in loop back mode, the modem control
      input Uart_CTS is disconnected and the modem control output Uart_RTS are
      looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is
      inverted (see IrDA SIR Mode Support). </comment>
    </bits>

    <bits access="rw" name="Rx Lock Err" pos="25" rst="0">
      <comment>Allow to stop the data receiving when an error is detected
      (framing, parity or break). The data in the fifo are kept. </comment>
    </bits>

    <bits access="rw" name="Rx Break Length" pos="31:28" rst="0xF">
      <comment>Length of a break, in number of bits. </comment>
    </bits>
  </reg>

  <reg protect="r" name="status">
    <bits access="r" name="Rx Fifo Level" pos="NB_RX_FIFO_BITS:0" rst="0">
       <options>
            <mask/>
            <shift/>
        </options>
        <comment>Those bits indicate the number of data available in the Rx
      Fifo. Those data can be read. </comment>
    </bits>

    <bits access="r" name="character_miscompare" pos="6" rst="0">
      <comment> character miscompare flag
            <br/> '0' = AT or at compare failed. 
            <br/> '1' = AT or at compare successfully. 
            When auto_enable is 0,this bit is cleared to 0.
       </comment>
    </bits>

    <bits access="r" name="auto_baud_locked" pos="7" rst="0">
      <comment> auto baud locked flag
            <br/> '0' = baud rate is detected failed. 
            <br/> '1' = baud rate is detected successfully. 
            When auto_enable is 0,this bit is cleared to 0.
       </comment>
    </bits>

    <bits access="r" name="Tx Fifo space" pos="NB_TX_FIFO_BITS+8:8" rst="5'h10">
        <options>
            <mask/>
            <shift/>
        </options>
        <comment>Those bits indicate the number of space available in the Tx
      Fifo. </comment>
    </bits>

    <bits access="r" name="Tx Active" pos="14" rst="0">
      <comment>This bit indicates that the UART is sending data. If no data is
      in the fifo, the UART is currently sending the last one through the
      serial interface. </comment>
    </bits>

    <bits access="r" name="Rx Active" pos="15" rst="0">
      <comment>This bit indicates that the UART is receiving a byte.
      </comment>
    </bits>

    <bits access="r" name="Rx Overflow Err" pos="16" rst="0">
      <comment>This bit indicates that the receiver received a new character
      when the fifo was already full. The new character is discarded. This bit
      is cleared when the UART_STATUS register is written with any value.
      </comment>
    </bits>

    <bits access="r" name="Tx Overflow Err" pos="17" rst="0">
      <comment>This bit indicates that the user tried to write a character when fifo was
          already full. The written data will not be kept. This bit is cleared when 
          the UART_STATUS register is written with any value. </comment>
    </bits>

    <bits access="r" name="Rx Parity Err" pos="18" rst="0">
      <comment>This bit is set if the parity is enabled and a parity error
      occurred in the received data. This bit is cleared when the UART_STATUS
      register is written with any value. </comment>
    </bits>

    <bits access="r" name="Rx Framing Err" pos="19" rst="0">
      <comment>This bit is set whenever there is a framing error occured. A
      framing error occurs when the receiver does not detect a valid STOP bit
      in the received data. This bit is cleared when the UART_STATUS register
      is written with any value. </comment>
    </bits>

    <bits access="r" name="Rx Break Int" pos="20" rst="0">
      <comment>This bit is set whenever the serial input is held in a logic 0
      state for longer than the length of x bits, where x is the value
      programmed Rx Break Length. A null word will be written in the Rx Fifo.
      This bit is cleared when the UART_STATUS register is written with any
      value. </comment>
    </bits>

    <bits access="r" name="DCTS" pos="24" rst="1">
      <comment>This bit is set when the Uart_CTS line changed since the last
      time this register has been written. This bit is cleared when the
      UART_STATUS register is written with any value. </comment>
    </bits>

    <bits access="r" name="CTS" pos="25" rst="0">
        <comment>current value of the Uart_CTS line. 
            <br/> '1' = Tx not allowed. 
            <br/> '0' = Tx allowed. 
      </comment>
    </bits>

    <bits access="r" name="DTR" pos="28" rst="0">
      <comment>Current value of the DTR line.
      </comment>
    </bits>
    
    <bits access="r" name="Clk Enabled" pos="31" rst="0">
      <comment>This bit is set when Uart Clk has been enabled and received by
      UART after Need Uart Clock becomes active. It serves to avoid enabling
      RTS too early.</comment>
    </bits>
  </reg>

  <reg protect="--" name="rxtx_buffer">
    <bits access="r" name="Rx Data" pos="7:0" rst="no">
      <comment>The UART_RECEIVE_BUFFER register is a read-only register that
      contains the data byte received on the serial input port. This register
      accesses the head of the receive FIFO. If the receive FIFO is full and
      this register is not read before the next data character arrives, then
      the data already in the FIFO will be preserved but any incoming data
      will be lost. An overflow error will also occur. </comment>
    </bits>

    <bits access="w" name="Tx Data" pos="7:0" rst="no">
      <comment>The UART_TRANSMIT_HOLDING register is a write-only register
      that contains data to be transmitted on the serial output port. 16
      characters of data may be written to the UART_TRANSMIT_HOLDING register
      before the FIFO is full. Any attempt to write data when the FIFO is full
      results in the write data being lost. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="irq_mask">
    <bits access="rw" name="Tx Modem Status" pos="0" rst="0">
      <comment>Clear to send signal change detected. </comment>
    </bits>

    <bits access="rw" name="Rx Data Available" pos="1" rst="0">
      <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx
      Fifo trigger level). </comment>
    </bits>

    <bits access="rw" name="Tx Data Needed" pos="2" rst="0">
      <comment>Tx Fifo at or below threshold level (current level &lt;= Tx
      Fifo trigger level). </comment>
    </bits>

    <bits access="rw" name="Rx Timeout" pos="3" rst="0">
      <comment>No characters in or out of the Rx Fifo during the last 4
      character times and there is at least 1 character in it during this
      time. </comment>
    </bits>

    <bits access="rw" name="Rx Line Err" pos="4" rst="0">
      <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break
      Interrupt. </comment>
    </bits>

    <bits access="rw" name="Tx Dma Done" pos="5" rst="0">
      <comment>Pulse detected on Uart_Dma_Tx_Done_H signal. </comment>
    </bits>

    <bits access="rw" name="Rx Dma Done" pos="6" rst="0">
      <comment>Pulse detected on Uart_Dma_Rx_Done_H signal. </comment>
    </bits>

    <bits access="rw" name="Rx Dma Timeout" pos="7" rst="0">
        <comment>In DMA mode, there is at least 1 character that has been read 
            in or out the Rx Fifo. Then before received Rx DMA Done, No characters
            in or out of the Rx Fifo during the last 4 character times.
        </comment>
    </bits>

    <bits access="rw" name="DTR RISE" pos="8" rst="0">
      <comment>Rising edge detected on the UART_DTR signal. 
      </comment>
    </bits>

    <bits access="rw" name="DTR FALL" pos="9" rst="0">
      <comment>Falling edge detected on the UART_DTR signal. 
      </comment>
    </bits>
  
    <bits access="rw" name="Auto Fail" pos="10" rst="0">
      <comment>Auto function fail. 
      </comment>
    </bits>
  
  </reg>

  <reg protect="rw" name="irq_cause">
    <bits access="r" name="Tx Modem Status" pos="0" rst="0">
      <comment>Clear to send signal detected. Reset control: This bit is
      cleared when the UART_STATUS register is written with any value.
      </comment>
    </bits>

    <bits access="r" name="Rx Data Available" pos="1" rst="0">
      <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx
      Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER
      until the Fifo drops below the trigger level. </comment>
    </bits>

    <bits access="r" name="Tx Data Needed" pos="2" rst="0">
      <comment>Tx Fifo at or below threshold level (current level &lt;= Tx
      Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING
      register above threshold level. </comment>
    </bits>

    <bits access="r" name="Rx Timeout" pos="3" rst="0">
      <comment>No characters in or out of the Rx Fifo during the last 4
      character times and there is at least 1 character in it during this
      time. Reset control: Reading from the UART_RECEIVE_BUFFER register.
      </comment>
    </bits>

    <bits access="r" name="Rx Line Err" pos="4" rst="0">
      <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break
      Interrupt. Reset control: This bit is cleared when the UART_STATUS
      register is written with any value. </comment>
    </bits>

    <bits access="rw" name="Tx Dma Done" pos="5" rst="0">
      <comment>This interrupt is generated when a pulse is detected on the
      Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register.
      </comment>
    </bits>

    <bits access="rw" name="Rx Dma Done" pos="6" rst="0">
      <comment>This interrupt is generated when a pulse is detected on the
      Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register.
      </comment>
    </bits>

    <bits access="rw" name="Rx Dma Timeout" pos="7" rst="0">
        <comment>In DMA mode, there is at least 1 character that has been read 
            in or out the Rx Fifo. Then before received Rx DMA Done, No characters 
            in or out of the Rx Fifo during the last 4 character times.
            Reset control: Write one in this register.
        </comment>    
    </bits>

    <bits access="rw" name="DTR RISE" pos="8" rst="0">
      <comment>This interrupt is generated when a rising edge is detected on the
      UART_DTR signal. Reset control: Write one in this register.
      </comment>
    </bits>

    <bits access="rw" name="DTR FALL" pos="9" rst="0">
      <comment>This interrupt is generated when a falling edge is detected on the
      UART_DTR signal. Reset control: Write one in this register.
      </comment>
    </bits>
    
    <bits access="rw" name="Auto Fail" pos="10" rst="0">
      <comment>This interrupt is generated when auto function fail.
      Reset control: Write  0 in auto_enable.
      </comment>
    </bits>
    
    <bits access="r" name="Tx Modem Status U" pos="16" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Data Available U" pos="17" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Tx Data Needed U" pos="18" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Timeout U" pos="19" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Line Err U" pos="20" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Tx Dma Done U" pos="21" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Dma Done U" pos="22" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Rx Dma Timeout U" pos="23" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="DTR RISE U" pos="24" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="DTR FALL U" pos="25" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>

    <bits access="r" name="Auto fail U" pos="26" rst="0">
      <comment>Same as previous, not masked. </comment>
    </bits>
    
  </reg>

  <reg protect="rw" name="triggers">
    <bits access="rw" name="Rx Trigger" pos="NB_RX_FIFO_BITS-1:0" rst="0">
      <comment>Defines the empty threshold level at which the Data Available
      Interrupt will be generated. <br />The Data Available interrupt is
      generated when quantity of data in Rx Fifo &gt; Rx Trigger.</comment>
    </bits>

    <bits access="rw" name="Tx Trigger" pos="NB_TX_FIFO_BITS-1+8:8" rst="0">
      <comment>Defines the empty threshold level at which the Data Needed
      Interrupt will be generated.<br />The Data Needed Interrupt is generated
      when quantity of data in Tx Fifo &lt;= Tx Trigger.</comment>
    </bits>

    <bits access="rw" name="AFC Level" pos="NB_RX_FIFO_BITS-1+16:16" rst="0">
      <comment>Controls the Rx Fifo level at which the Uart_RTS Auto Flow
      Control will be set inactive high (see UART Operation for more details
      on AFC).<br />The Uart_RTS Auto Flow Control will be set inactive high
      when quantity of data in Rx Fifo &gt; AFC Level.</comment>
    </bits>
  </reg>

  <reg protect="rw" name="CMD_Set">
    <bits access="rs" name="RI" pos="0" rst="0">
        <comment>Ring indicator. When write '1', set RI bit. When read, get RI bit 
            value.
        </comment>
    </bits>
    
    <bits access="rs" name="DCD" pos="1" rst="0">
        <comment>Data carrier detect. When write '1', set DCD bit. When read, get DCD
            bit value.
        </comment>
    </bits>
    
    <bits access="rs" name="DSR" pos="2" rst="0">
        <comment>Data set ready. When write '1', set RI bit. When read, get RI bit 
            value.
        </comment>
    </bits>
    
    <bits access="rs" name="Tx Break Control" pos="3" rst="0">
      <comment> Sends a break signal by holding the Uart_Tx line low until
      this bit is cleared. </comment>
    </bits>
    
    <bits access="rs" name="Tx Finish n Wait" pos="4" rst="0">
      <comment>When this bit is set the Tx engine terminates to send the
      current byte and then it stops to send data.</comment>
    </bits>  

    <bits access="rs" name="RTS" pos="5" rst="0">
        <comment>Controls the Uart_RTS output.
            <br />0 = the Uart_RTS will be inactive high (Rx not allowed).
            <br />1 = the Uart_RTS will be active low (Rx allowed).
        </comment>
    </bits>
    
    <bits access="r" name="Rx Fifo Reset" pos="6" rst="0">
      <comment> Writing a 1 to this bit resets and flushes the Receive Fifo.
      This bit does not need to be cleared. </comment>
    </bits>
    
    <bits access="r" name="Tx Fifo Reset" pos="7" rst="0">
      <comment> Writing a 1 to this bit resets and flushes the Transmit Fifo.
      This bit does not need to be cleared. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="CMD_Clr">
    <bits access="rc" name="RI" pos="0" rst="0">
        <comment>Ring indicator. When write '1', clear RI bit. When read, get RI bit 
            value.
        </comment>
    </bits>

    <bits access="rc" name="DCD" pos="1" rst="0">
        <comment>Data carrier detect. When write '1', clear DCD bit. When read, get DCD
            bit value.
        </comment>
    </bits>

    <bits access="rc" name="DSR" pos="2" rst="0">
        <comment>Data set ready. When write '1', clear RI bit. When read, get RI bit 
            value.
        </comment>
    </bits>

    <bits access="rc" name="Tx Break Control" pos="3" rst="0">
      <comment> Sends a break signal by holding the Uart_Tx line low until
      this bit is cleared. </comment>
    </bits>
    
    <bits access="rc" name="Tx Finish n Wait" pos="4" rst="0">
      <comment>When this bit is set the Tx engine terminates to send the
      current byte and then it stops to send data.</comment>
    </bits>  

    <bits access="rc" name="RTS" pos="5" rst="0">
        <comment>Controls the Uart_RTS output.
            <br />0 = the Uart_RTS will be inactive high.
            <br />1 = the Uart_RTS will be active low.
        </comment>
    </bits>
    
  </reg>
  
</module>


</archive>
<archive relative="usbc.xml">
  <module name="usbc" category="Periph">
    <reg protect="rw" name="GOTGCTL">
      <bits access="rc" name="GOTGCTL_reserved_2" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="CurMod" pos="21" rst="0">
      </bits>
      <bits access="rw" name="OTGVer" pos="20" rst="0">
      </bits>
      <bits access="r" name="BSesVld" pos="19" rst="1">
      </bits>
      <bits access="rw" name="ASesVld" pos="18" rst="1">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
      <bits access="r" name="DbncTime" pos="17" rst="0">
      </bits>
      <bits access="r" name="ConIDSts" pos="16" rst="1">
      </bits>
      <bits access="rw" name="DbnceFltrBypass" pos="15" rst="0">
      </bits>
      <bits access="rc" name="GOTGCTL_reserved_1" pos="14:8" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BvalidOvVal" pos="7" rst="0">
      </bits>
      <bits access="rw" name="BvalidOvEn" pos="6" rst="0">
      </bits>
      <bits access="rw" name="AvalidOvVal" pos="5" rst="0">
      </bits>
      <bits access="rw" name="AvalidOvEn" pos="4" rst="0">
      </bits>
      <bits access="rw" name="VbvalidOvVal" pos="3" rst="0">
      </bits>
      <bits access="rw" name="VbvalidOvEn" pos="2" rst="0">
      </bits>
      <bits access="rc" name="GOTGCTL_reserved_0" pos="1:0" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GOTGINT">
      <bits access="rc" name="GOTGINT_reserved_3" pos="31:20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DbnceDone" pos="19" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ADevTOUTChg" pos="18" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="HstNegDet" pos="17" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="GOTGINT_reserved_2" pos="16:10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="HstNegSucStsChng" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SesReqSucStsChng" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="GOTGINT_reserved_1" pos="7:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="SesEndDet" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="GOTGINT_reserved_0" pos="1:0" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GAHBCFG">
      <bits access="rc" name="GAHBCFG_reserved_2" pos="31:25" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="InvDescEndianess" pos="24" rst="0">
      </bits>
      <bits access="rw" name="AHBSingle" pos="23" rst="0">
      </bits>
      <bits access="rw" name="NotiAllDmaWrit" pos="22" rst="0">
      </bits>
      <bits access="rw" name="RemMemSupp" pos="21" rst="0">
      </bits>
      <bits access="rc" name="GAHBCFG_reserved_1" pos="20:8" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="NPTxFEmpLvl" pos="7" rst="0">
      </bits>
      <bits access="rc" name="GAHBCFG_reserved_0" pos="6" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DMAEn" pos="5" rst="0">
      </bits>
      <bits access="rw" name="HBstLen" pos="4:1" rst="0">
      </bits>
      <bits access="rw" name="GlblIntrMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="GUSBCFG">
      <bits access="rw" name="CorruptTxPkt" pos="31" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="ForceDevMode" pos="30" rst="0">
      </bits>
      <bits access="rw" name="ForceHstMode" pos="29" rst="0">
      </bits>
      <bits access="rw" name="TxEndDelay" pos="28" rst="0">
      </bits>
      <bits access="rc" name="GUSBCFG_reserved_4" pos="27" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="IC_USBCap" pos="26" rst="0">
      </bits>
      <bits access="rc" name="GUSBCFG_reserved_3" pos="25:23" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="TermSelDLPulse" pos="22" rst="0">
      </bits>
      <bits access="rc" name="GUSBCFG_reserved_2" pos="21:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="USBTrdTim" pos="13:10" rst="5">
      </bits>
      <bits access="rc" name="GUSBCFG_reserved_1" pos="9:7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="PHYSel" pos="6" rst="1">
      </bits>
      <bits access="rw" name="FSIntf" pos="5" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="GUSBCFG_reserved_0" pos="4" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PHYIf" pos="3" rst="0">
      </bits>
      <bits access="rw" name="TOutCal" pos="2:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="GRSTCTL">
      <bits access="r" name="AHBIdle" pos="31" rst="1">
      </bits>
      <bits access="r" name="DMAReq" pos="30" rst="0">
      </bits>
      <bits access="rc" name="GRSTCTL_reserved_1" pos="29:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="TxFNum" pos="10:6" rst="0">
      </bits>
      <bits access="rw" name="TxFFlsh" pos="5" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="RxFFlsh" pos="4" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="GRSTCTL_reserved_0" pos="3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="FrmCntrRst" pos="2" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="PIUFSSftRst" pos="1" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="CSftRst" pos="0" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GINTSTS">
      <bits access="rc" name="WkUpInt" pos="31" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SessReqInt" pos="30" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DisconnInt" pos="29" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rw" name="ConIDStsChng" pos="28" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="GINTSTS_reserved_2" pos="27:26" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="HChInt" pos="25" rst="0">
      </bits>
      <bits access="r" name="PrtInt" pos="24" rst="0">
      </bits>
      <bits access="rc" name="ResetDet" pos="23" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FetSusp" pos="22" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="incomplP" pos="21" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="incompISOIN" pos="20" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="OEPInt" pos="19" rst="0">
      </bits>
      <bits access="r" name="IEPInt" pos="18" rst="0">
      </bits>
      <bits access="rc" name="EPMis" pos="17" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="GINTSTS_reserved_1" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="EOPF" pos="15" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ISOOutDrop" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EnumDone" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="USBRst" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="USBSusp" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ErlySusp" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="GINTSTS_reserved_0" pos="9:8" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="GOUTNakEff" pos="7" rst="0">
      </bits>
      <bits access="r" name="GINNakEff" pos="6" rst="0">
      </bits>
      <bits access="r" name="NPTxFEmp" pos="5" rst="1">
      </bits>
      <bits access="r" name="RxFLvl" pos="4" rst="0">
      </bits>
      <bits access="rw" name="Sof" pos="3" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OTGInt" pos="2" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
      <bits access="rc" name="ModeMis" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="CurMod" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="GINTMSK">
      <bits access="rw" name="WkUpIntMsk" pos="31" rst="0">
      </bits>
      <bits access="rw" name="SessReqIntMsk" pos="30" rst="0">
      </bits>
      <bits access="rw" name="DisconnIntMsk" pos="29" rst="0">
      </bits>
      <bits access="rw" name="ConIDStsChngMsk" pos="28" rst="0">
      </bits>
      <bits access="rc" name="GINTMSK_reserved_4" pos="27:26" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="HChIntMsk" pos="25" rst="0">
      </bits>
      <bits access="rw" name="PrtIntMsk" pos="24" rst="0">
      </bits>
      <bits access="rw" name="ResetDetMsk" pos="23" rst="0">
      </bits>
      <bits access="rw" name="FetSuspMsk" pos="22" rst="0">
      </bits>
      <bits access="rw" name="incomplPMsK" pos="21" rst="0">
      </bits>
      <bits access="rc" name="GINTMSK_reserved_3" pos="20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="OEPIntMsk" pos="19" rst="0">
      </bits>
      <bits access="rw" name="IEPIntMsk" pos="18" rst="0">
      </bits>
      <bits access="rw" name="EPMisMsk" pos="17" rst="0">
      </bits>
      <bits access="rc" name="GINTMSK_reserved_2" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EOPFMsk" pos="15" rst="0">
      </bits>
      <bits access="rw" name="ISOOutDropMsk" pos="14" rst="0">
      </bits>
      <bits access="rw" name="EnumDoneMsk" pos="13" rst="0">
      </bits>
      <bits access="rw" name="USBRstMsk" pos="12" rst="0">
      </bits>
      <bits access="rw" name="USBSuspMsk" pos="11" rst="0">
      </bits>
      <bits access="rw" name="ErlySuspMsk" pos="10" rst="0">
      </bits>
      <bits access="rc" name="GINTMSK_reserved_1" pos="9:8" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="GOUTNakEffMsk" pos="7" rst="0">
      </bits>
      <bits access="rw" name="GINNakEffMsk" pos="6" rst="0">
      </bits>
      <bits access="rw" name="NPTxFEmpMsk" pos="5" rst="0">
      </bits>
      <bits access="rw" name="RxFLvlMsk" pos="4" rst="0">
      </bits>
      <bits access="rw" name="SofMsk" pos="3" rst="0">
      </bits>
      <bits access="rw" name="OTGIntMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ModeMisMsk" pos="1" rst="0">
      </bits>
      <bits access="rc" name="GINTMSK_reserved_0" pos="0" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GRXSTSR">
      <bits access="rc" name="GRXSTSR_reserved_0" pos="31:25" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="FN" pos="24:21" rst="0">
      </bits>
      <bits access="rw" name="PktSts" pos="20:17" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
      <bits access="r" name="DPID" pos="16:15" rst="0">
      </bits>
      <bits access="r" name="BCnt" pos="14:4" rst="0">
      </bits>
      <bits access="rw" name="ChNum" pos="3:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GRXSTSP">
      <bits access="rc" name="GRXSTSP_reserved_0" pos="31:25" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="FN" pos="24:21" rst="0">
      </bits>
      <bits access="rw" name="PktSts" pos="20:17" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
      <bits access="r" name="DPID" pos="16:15" rst="0">
      </bits>
      <bits access="r" name="BCnt" pos="14:4" rst="0">
      </bits>
      <bits access="rw" name="ChNum" pos="3:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="GRXFSIZ">
      <bits access="rc" name="GRXFSIZ_reserved_0" pos="31:9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="RxFDep" pos="8:0" rst="297">
      </bits>
    </reg>
    <reg protect="rw" name="GNPTXFSIZ">
      <bits access="rc" name="GNPTXFSIZ_reserved_1" pos="31:25" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="NPTXFDep" pos="24:16" rst="297">
      </bits>
      <bits access="rc" name="GNPTXFSIZ_reserved_0" pos="15:9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="NPTXFStAddr" pos="8:0" rst="297">
      </bits>
    </reg>
    <reg protect="rw" name="GNPTXSTS">
      <bits access="rc" name="GNPTXSTS_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="NPTxQTop" pos="30:24" rst="0">
      </bits>
      <bits access="r" name="NPTxQSpcAvail" pos="23:16" rst="8">
      </bits>
      <bits access="r" name="NPTxFSpcAvail" pos="15:0" rst="297">
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="GGPIO">
      <bits access="rw" name="GPO" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="GPI" pos="15:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="GUID">
      <bits access="rw" name="GUID" pos="31:0" rst="3221291008">
      </bits>
    </reg>
    <reg protect="r" name="GSNPSID">
      <bits access="r" name="SynopsysID" pos="31:0" rst="1330921482">
      </bits>
    </reg>
    <reg protect="r" name="GHWCFG1">
      <bits access="r" name="EpDir" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="GHWCFG2">
      <bits access="rc" name="GHWCFG2_reserved_1" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="TknQDepth" pos="30:26" rst="8">
      </bits>
      <bits access="r" name="PTxQDepth" pos="25:24" rst="2">
      </bits>
      <bits access="r" name="NPTxQDepth" pos="23:22" rst="2">
      </bits>
      <bits access="rc" name="GHWCFG2_reserved_0" pos="21" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="MultiProcIntrpt" pos="20" rst="0">
      </bits>
      <bits access="r" name="DynFifoSizing" pos="19" rst="1">
      </bits>
      <bits access="r" name="PerioSupport" pos="18" rst="0">
      </bits>
      <bits access="r" name="NumHstChnl" pos="17:14" rst="11">
      </bits>
      <bits access="r" name="NumDevEps" pos="13:10" rst="5">
          <options><mask/><shift/></options>
      </bits>
      <bits access="r" name="FSPhyType" pos="9:8" rst="1">
      </bits>
      <bits access="r" name="HSPhyType" pos="7:6" rst="0">
      </bits>
      <bits access="r" name="SingPnt" pos="5" rst="0">
      </bits>
      <bits access="r" name="OtgArch" pos="4:3" rst="2">
      </bits>
      <bits access="r" name="OtgMode" pos="2:0" rst="2">
      </bits>
    </reg>
    <reg protect="r" name="GHWCFG3">
      <bits access="r" name="DfifoDepth" pos="31:16" rst="285">
      </bits>
      <bits access="r" name="LPMMode" pos="15" rst="0">
      </bits>
      <bits access="r" name="BCSupport" pos="14" rst="0">
      </bits>
      <bits access="r" name="HSICMode" pos="13" rst="0">
      </bits>
      <bits access="r" name="ADPSupport" pos="12" rst="0">
      </bits>
      <bits access="r" name="RstType" pos="11" rst="0">
      </bits>
      <bits access="r" name="OptFeature" pos="10" rst="0">
      </bits>
      <bits access="r" name="VndctlSupt" pos="9" rst="0">
      </bits>
      <bits access="r" name="I2CIntSel" pos="8" rst="0">
      </bits>
      <bits access="r" name="OtgEn" pos="7" rst="1">
      </bits>
      <bits access="r" name="PktSizeWidth" pos="6:4" rst="6">
      </bits>
      <bits access="r" name="XferSizeWidth" pos="3:0" rst="8">
      </bits>
    </reg>
    <reg protect="rw" name="GHWCFG4">
      <bits access="r" name="DescDMA" pos="31" rst="0">
      </bits>
      <bits access="r" name="DescDMAEnabled" pos="30" rst="0">
      </bits>
      <bits access="r" name="INEps" pos="29:26" rst="5">
      </bits>
      <bits access="r" name="DedFifoMode" pos="25" rst="1">
      </bits>
      <bits access="r" name="SessEndFltr" pos="24" rst="0">
      </bits>
      <bits access="r" name="BValidFltr" pos="23" rst="0">
      </bits>
      <bits access="r" name="AValidFltr" pos="22" rst="0">
      </bits>
      <bits access="r" name="VBusValidFltr" pos="21" rst="0">
      </bits>
      <bits access="r" name="IddgFltr" pos="20" rst="1">
      </bits>
      <bits access="r" name="NumCtlEps" pos="19:16" rst="0">
      </bits>
      <bits access="r" name="PhyDataWidth" pos="15:14" rst="2">
      </bits>
      <bits access="r" name="EnhancedLPMSupt" pos="13" rst="1">
      </bits>
      <bits access="r" name="ACGSupt" pos="12" rst="0">
      </bits>
      <bits access="rc" name="GHWCFG4_reserved_0" pos="11:8" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="ExtendedHibernation" pos="7" rst="0">
      </bits>
      <bits access="r" name="Hibernation" pos="6" rst="0">
      </bits>
      <bits access="r" name="AhbFreq" pos="5" rst="1">
      </bits>
      <bits access="r" name="PartialPwrDn" pos="4" rst="0">
      </bits>
      <bits access="r" name="NumDevPerioEps" pos="3:0" rst="0">
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="GDFIFOCFG">
      <bits access="rw" name="EPInfoBaseAddr" pos="31:16" rst="285">
      </bits>
      <bits access="rw" name="GDFIFOCfg" pos="15:0" rst="297">
      </bits>
    </reg>
    <hole size="1280"/>
    <reg protect="rw" name="HPTXFSIZ">
      <bits access="rc" name="HPTXFSIZ_reserved_1" pos="31:27" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PTxFSize" pos="26:16" rst="1024">
      </bits>
      <bits access="rc" name="HPTXFSIZ_reserved_0" pos="15:10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PTxFStAddr" pos="9:0" rst="594">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPTXF1">
      <bits access="rc" name="DIEPTXF1_reserved_1" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFDep" pos="21:16" rst="32">
      </bits>
      <bits access="rc" name="DIEPTXF1_reserved_0" pos="15:9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFStAddr" pos="8:0" rst="329">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPTXF2">
      <bits access="rc" name="DIEPTXF2_reserved_1" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFDep" pos="21:16" rst="32">
      </bits>
      <bits access="rc" name="DIEPTXF2_reserved_0" pos="15:9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFStAddr" pos="8:0" rst="361">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPTXF3">
      <bits access="rc" name="DIEPTXF3_reserved_1" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFDep" pos="21:16" rst="32">
      </bits>
      <bits access="rc" name="DIEPTXF3_reserved_0" pos="15:9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFStAddr" pos="8:0" rst="393">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPTXF4">
      <bits access="rc" name="DIEPTXF4_reserved_1" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFDep" pos="21:16" rst="32">
      </bits>
      <bits access="rc" name="DIEPTXF4_reserved_0" pos="15:9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFStAddr" pos="8:0" rst="425">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPTXF5">
      <bits access="rc" name="DIEPTXF5_reserved_1" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFDep" pos="21:16" rst="32">
      </bits>
      <bits access="rc" name="DIEPTXF5_reserved_0" pos="15:9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPnTxFStAddr" pos="8:0" rst="457">
      </bits>
    </reg>
    <hole size="5952"/>
    <reg protect="rw" name="HCFG">
      <bits access="rw" name="ModeChTimEn" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCFG_reserved_2" pos="30:27" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PerSchedEna" pos="26" rst="0">
      </bits>
      <bits access="rw" name="FrListEn" pos="25:24" rst="0">
      </bits>
      <bits access="rw" name="DescDMA" pos="23" rst="0">
      </bits>
      <bits access="rc" name="HCFG_reserved_1" pos="22:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="ResValid" pos="15:8" rst="2">
      </bits>
      <bits access="rw" name="Ena32KHzS" pos="7" rst="0">
      </bits>
      <bits access="rc" name="HCFG_reserved_0" pos="6:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="FSLSSupp" pos="2" rst="0">
      </bits>
      <bits access="rw" name="FSLSPclkSel" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HFIR">
      <bits access="rc" name="HFIR_reserved_0" pos="31:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="HFIRRldCtrl" pos="16" rst="0">
      </bits>
      <bits access="rw" name="FrInt" pos="15:0" rst="60000">
      </bits>
    </reg>
    <reg protect="r" name="HFNUM">
      <bits access="r" name="FrRem" pos="31:16" rst="0">
      </bits>
      <bits access="r" name="FrNum" pos="15:0" rst="16383">
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="HAINT">
      <bits access="rc" name="HAINT_reserved_0" pos="31:12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="HAINT" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HAINTMSK">
      <bits access="rc" name="HAINTMSK_reserved_0" pos="31:12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="HAINTMsk" pos="11:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HFLBAddr">
      <bits access="rw" name="HFLBAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="256"/>
    <reg protect="rw" name="HPRT">
      <bits access="rc" name="HPRT_reserved_1" pos="31:19" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="PrtSpd" pos="18:17" rst="0">
      </bits>
      <bits access="rw" name="PrtTstCtl" pos="16:13" rst="0">
      </bits>
      <bits access="rw" name="PrtPwr" pos="12" rst="0">
      </bits>
      <bits access="r" name="PrtLnSts" pos="11:10" rst="0">
      </bits>
      <bits access="rc" name="HPRT_reserved_0" pos="9" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PrtRst" pos="8" rst="0">
      </bits>
      <bits access="rw" name="PrtSusp" pos="7" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="PrtRes" pos="6" rst="0">
      </bits>
      <bits access="rc" name="PrtOvrCurrChng" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="PrtOvrCurrAct" pos="4" rst="0">
      </bits>
      <bits access="rc" name="PrtEnChng" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PrtEna" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PrtConnDet" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="PrtConnSts" pos="0" rst="0">
      </bits>
    </reg>
    <hole size="1504"/>
    <reg protect="rw" name="HCCHAR0">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR0_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
          <options><mask/><shift/></options>
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT0">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT0_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT0">
      <bits access="rc" name="HCINT0_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK0">
      <bits access="rc" name="HCINTMSK0_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK0_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK0_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ0">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA0">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB0">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR1">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR1_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT1">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT1_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT1">
      <bits access="rc" name="HCINT1_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK1">
      <bits access="rc" name="HCINTMSK1_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK1_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK1_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ1">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA1">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB1">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR2">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR2_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT2">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT2_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT2">
      <bits access="rc" name="HCINT2_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK2">
      <bits access="rc" name="HCINTMSK2_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK2_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK2_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ2">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA2">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB2">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR3">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR3_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT3">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT3_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT3">
      <bits access="rc" name="HCINT3_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK3">
      <bits access="rc" name="HCINTMSK3_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK3_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK3_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ3">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA3">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB3">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR4">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR4_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT4">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT4_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT4">
      <bits access="rc" name="HCINT4_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK4">
      <bits access="rc" name="HCINTMSK4_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK4_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK4_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ4">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA4">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB4">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR5">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR5_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT5">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT5_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT5">
      <bits access="rc" name="HCINT5_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK5">
      <bits access="rc" name="HCINTMSK5_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK5_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK5_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ5">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA5">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB5">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR6">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR6_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT6">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT6_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT6">
      <bits access="rc" name="HCINT6_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK6">
      <bits access="rc" name="HCINTMSK6_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK6_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK6_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ6">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA6">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB6">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR7">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR7_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT7">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT7_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT7">
      <bits access="rc" name="HCINT7_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK7">
      <bits access="rc" name="HCINTMSK7_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK7_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK7_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ7">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA7">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB7">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR8">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR8_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT8">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT8_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT8">
      <bits access="rc" name="HCINT8_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK8">
      <bits access="rc" name="HCINTMSK8_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK8_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK8_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ8">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA8">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB8">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR9">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR9_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT9">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT9_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT9">
      <bits access="rc" name="HCINT9_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK9">
      <bits access="rc" name="HCINTMSK9_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK9_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK9_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ9">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA9">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB9">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR10">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR10_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT10">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT10_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT10">
      <bits access="rc" name="HCINT10_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK10">
      <bits access="rc" name="HCINTMSK10_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK10_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK10_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ10">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA10">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB10">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCCHAR11">
      <bits access="rw" name="ChEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="ChDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="OddFrm" pos="29" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="28:22" rst="0">
      </bits>
      <bits access="rw" name="EC" pos="21:20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="rw" name="LSpdDev" pos="17" rst="0">
      </bits>
      <bits access="rc" name="HCCHAR11_reserved_0" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPDir" pos="15" rst="0">
      </bits>
      <bits access="rw" name="EPNum" pos="14:11" rst="0">
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCSPLT11">
      <bits access="rw" name="SpltEna" pos="31" rst="0">
      </bits>
      <bits access="rc" name="HCSPLT11_reserved_0" pos="30:17" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="CompSplt" pos="16" rst="0">
      </bits>
      <bits access="rw" name="XactPos" pos="15:14" rst="0">
      </bits>
      <bits access="rw" name="HubAddr" pos="13:7" rst="0">
      </bits>
      <bits access="rw" name="PrtAddr" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCINT11">
      <bits access="rc" name="HCINT11_reserved_0" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="DESC_LST_ROLLIntr" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XCS_XACT_ERR" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DataTglErr" pos="10" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="FrmOvrun" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BblErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XactErr" pos="7" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYET" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ACK" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAK" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="STALL" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="ChHltd" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="HCINTMSK11">
      <bits access="rc" name="HCINTMSK11_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DESC_LST_ROLLIntrMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK11_reserved_1" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAIntrMsk" pos="11" rst="0">
      </bits>
      <bits access="rc" name="HCINTMSK11_reserved_0" pos="10:3" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="ChHltdMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCTSIZ11">
      <bits access="rw" name="DoPng" pos="31" rst="0">
      </bits>
      <bits access="rw" name="Pid" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="HCDMA11">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="r" name="HCDMAB11">
      <bits access="r" name="HCDMAB" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="3072"/>
    <reg protect="rw" name="DCFG">
      <bits access="rw" name="ResValid" pos="31:26" rst="2">
      </bits>
      <bits access="rw" name="PerSchIntvl" pos="25:24" rst="0">
      </bits>
      <bits access="rw" name="DescDMA" pos="23" rst="0">
      </bits>
      <bits access="rc" name="DCFG_reserved_0" pos="22:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="ErraticIntMsk" pos="15" rst="0">
      </bits>
      <bits access="rw" name="XCVRDLY" pos="14" rst="0">
      </bits>
      <bits access="rw" name="EnDevOutNak" pos="13" rst="0">
      </bits>
      <bits access="rw" name="PerFrInt" pos="12:11" rst="0">
      </bits>
      <bits access="rw" name="DevAddr" pos="10:4" rst="0">
      </bits>
      <bits access="rw" name="Ena32KHzSusp" pos="3" rst="0">
      </bits>
      <bits access="rw" name="NZStsOUTHShk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="DevSpd" pos="1:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DCTL">
      <bits access="rc" name="DCTL_reserved_1" pos="31:18" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EnContOnBNA" pos="17" rst="0">
      </bits>
      <bits access="rw" name="NakOnBble" pos="16" rst="0">
      </bits>
      <bits access="rw" name="IgnrFrmNum" pos="15" rst="0">
      </bits>
      <bits access="rw" name="GMC" pos="14:13" rst="0">
      </bits>
      <bits access="rc" name="DCTL_reserved_0" pos="12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PWROnPrgDone" pos="11" rst="0">
      </bits>
      <bits access="rw" name="CGOUTNak" pos="10" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SGOUTNak" pos="9" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CGNPInNak" pos="8" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SGNPInNak" pos="7" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="TstCtl" pos="6:4" rst="0">
      </bits>
      <bits access="r" name="GOUTNakSts" pos="3" rst="0">
      </bits>
      <bits access="r" name="GNPINNakSts" pos="2" rst="0">
      </bits>
      <bits access="rw" name="SftDiscon" pos="1" rst="1">
      </bits>
      <bits access="rw" name="RmtWkUpSig" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DSTS">
      <bits access="rc" name="DSTS_reserved_1" pos="31:24" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="DevLnSts" pos="23:22" rst="0">
      </bits>
      <bits access="rw" name="SOFFN" pos="21:8" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
      <bits access="rc" name="DSTS_reserved_0" pos="7:4" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="ErrticErr" pos="3" rst="0">
      </bits>
      <bits access="r" name="EnumSpd" pos="2:1" rst="1">
      </bits>
      <bits access="r" name="SuspSts" pos="0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPMSK">
      <bits access="rc" name="DIEPMSK_reserved_2" pos="31:14" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="NAKMsk" pos="13" rst="0">
      </bits>
      <bits access="rc" name="DIEPMSK_reserved_1" pos="12:10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BNAInIntrMsk" pos="9" rst="0">
      </bits>
      <bits access="rw" name="TxfifoUndrnMsk" pos="8" rst="0">
      </bits>
      <bits access="rc" name="DIEPMSK_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="INEPNakEffMsk" pos="6" rst="0">
      </bits>
      <bits access="rw" name="INTknEPMisMsk" pos="5" rst="0">
      </bits>
      <bits access="rw" name="INTknTXFEmpMsk" pos="4" rst="0">
      </bits>
      <bits access="rw" name="TimeOUTMsk" pos="3" rst="0">
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="EPDisbldMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DOEPMSK">
      <bits access="rc" name="DOEPMSK_reserved_2" pos="31:15" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="NYETMsk" pos="14" rst="0">
      </bits>
      <bits access="rw" name="NAKMsk" pos="13" rst="0">
      </bits>
      <bits access="rw" name="BbleErrMsk" pos="12" rst="0">
      </bits>
      <bits access="rc" name="DOEPMSK_reserved_1" pos="11:10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="BnaOutIntrMsk" pos="9" rst="0">
      </bits>
      <bits access="rw" name="OutPktErrMsk" pos="8" rst="0">
      </bits>
      <bits access="rc" name="DOEPMSK_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="Back2BackSETup" pos="6" rst="0">
      </bits>
      <bits access="rw" name="StsPhseRcvdMsk" pos="5" rst="0">
      </bits>
      <bits access="rw" name="OUTTknEPdisMsk" pos="4" rst="0">
      </bits>
      <bits access="rw" name="SetUPMsk" pos="3" rst="0">
      </bits>
      <bits access="rw" name="AHBErrMsk" pos="2" rst="0">
      </bits>
      <bits access="rw" name="EPDisbldMsk" pos="1" rst="0">
      </bits>
      <bits access="rw" name="XferComplMsk" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DAINT">
      <bits access="rc" name="DAINT_reserved_1" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="OutEPInt5" pos="21" rst="0">
      </bits>
      <bits access="r" name="OutEPInt4" pos="20" rst="0">
      </bits>
      <bits access="r" name="OutEPInt3" pos="19" rst="0">
      </bits>
      <bits access="r" name="OutEPInt2" pos="18" rst="0">
      </bits>
      <bits access="r" name="OutEPInt1" pos="17" rst="0">
      </bits>
      <bits access="r" name="OutEPInt0" pos="16" rst="0">
      </bits>
      <bits access="rc" name="DAINT_reserved_0" pos="15:6" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="InEpInt5" pos="5" rst="0">
      </bits>
      <bits access="r" name="InEpInt4" pos="4" rst="0">
      </bits>
      <bits access="r" name="InEpInt3" pos="3" rst="0">
      </bits>
      <bits access="r" name="InEpInt2" pos="2" rst="0">
      </bits>
      <bits access="r" name="InEpInt1" pos="1" rst="0">
      </bits>
      <bits access="r" name="InEpInt0" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DAINTMSK">
      <bits access="rc" name="DAINTMSK_reserved_1" pos="31:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="OutEPMsk5" pos="21" rst="0">
      </bits>
      <bits access="rw" name="OutEPMsk4" pos="20" rst="0">
      </bits>
      <bits access="rw" name="OutEPMsk3" pos="19" rst="0">
      </bits>
      <bits access="rw" name="OutEPMsk2" pos="18" rst="0">
      </bits>
      <bits access="rw" name="OutEPMsk1" pos="17" rst="0">
      </bits>
      <bits access="rw" name="OutEPMsk0" pos="16" rst="0">
      </bits>
      <bits access="rc" name="DAINTMSK_reserved_0" pos="15:6" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="InEpMsk5" pos="5" rst="0">
      </bits>
      <bits access="rw" name="InEpMsk4" pos="4" rst="0">
      </bits>
      <bits access="rw" name="InEpMsk3" pos="3" rst="0">
      </bits>
      <bits access="rw" name="InEpMsk2" pos="2" rst="0">
      </bits>
      <bits access="rw" name="InEpMsk1" pos="1" rst="0">
      </bits>
      <bits access="rw" name="InEpMsk0" pos="0" rst="0">
      </bits>
    </reg>
    <hole size="64"/>
    <reg protect="rw" name="DVBUSDIS">
      <bits access="rc" name="DVBUSDIS_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DVBUSDis" pos="15:0" rst="6103">
      </bits>
    </reg>
    <reg protect="rw" name="DVBUSPULSE">
      <bits access="rc" name="DVBUSPULSE_reserved_0" pos="31:12" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DVBUSPulse" pos="11:0" rst="1464">
      </bits>
    </reg>
    <reg protect="rw" name="DTHRCTL">
      <bits access="rc" name="DTHRCTL_reserved_2" pos="31:28" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="ArbPrkEn" pos="27" rst="1">
      </bits>
      <bits access="rc" name="DTHRCTL_reserved_1" pos="26" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="RxThrLen" pos="25:17" rst="8">
      </bits>
      <bits access="rw" name="RxThrEn" pos="16" rst="0">
      </bits>
      <bits access="rc" name="DTHRCTL_reserved_0" pos="15:13" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="AHBThrRatio" pos="12:11" rst="0">
      </bits>
      <bits access="rw" name="TxThrLen" pos="10:2" rst="8">
      </bits>
      <bits access="rw" name="ISOThrEn" pos="1" rst="0">
      </bits>
      <bits access="rw" name="NonISOThrEn" pos="0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPEMPMSK">
      <bits access="rc" name="DIEPEMPMSK_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="InEpTxfEmpMsk" pos="15:0" rst="0">
      </bits>
    </reg>
    <hole size="1600"/>
    <reg protect="rw" name="DIEPCTL0">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="DIEPCTL0_reserved_3" pos="29:28" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="w" name="SNAK" pos="27" rst="0">
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="TxFNum" pos="25:22" rst="0">
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="DIEPCTL0_reserved_2" pos="20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="rc" name="DIEPCTL0_reserved_1" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="USBActEP" pos="15" rst="1">
      </bits>
      <bits access="r" name="NEXTEP" pos="14:11" rst="0">
          <options><mask/><shift/></options>
      </bits>
      <bits access="rc" name="DIEPCTL0_reserved_0" pos="10:2" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="DIEPCTL0_MPS" pos="1:0" rst="0">
          <options><mask/><shift/></options>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPINT0">
      <bits access="rc" name="DIEPINT0_reserved_1" pos="31:15" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DIEPINT0_reserved_0" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TxfifoUndrn" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="TxFEmp" pos="7" rst="1">
      </bits>
      <bits access="rc" name="INEPNakEff" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknEPMis" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknTXFEmp" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TimeOUT" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPTSIZ0">
      <bits access="rc" name="DIEPTSIZ0_reserved_1" pos="31:21" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PktCnt" pos="20:19" rst="0">
      </bits>
      <bits access="rc" name="DIEPTSIZ0_reserved_0" pos="18:7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="XferSize" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMA0">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DTXFSTS0">
      <bits access="rc" name="DTXFSTS0_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="INEPTxFSpcAvail" pos="15:0" rst="297">
      </bits>
    </reg>
    <reg protect="r" name="DIEPDMAB0">
      <bits access="r" name="DMABufferAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPCTL1">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="TxFNum" pos="25:22" rst="0">
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="DIEPCTL1_reserved_1" pos="20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DIEPCTL1_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPINT1">
      <bits access="rc" name="DIEPINT1_reserved_1" pos="31:15" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DIEPINT1_reserved_0" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TxfifoUndrn" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="TxFEmp" pos="7" rst="1">
      </bits>
      <bits access="rc" name="INEPNakEff" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknEPMis" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknTXFEmp" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TimeOUT" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPTSIZ1">
      <bits access="rc" name="DIEPTSIZ1_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MC" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMA1">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DTXFSTS1">
      <bits access="rc" name="DTXFSTS1_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="INEPTxFSpcAvail" pos="15:0" rst="297">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMAB1">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DIEPCTL2">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="TxFNum" pos="25:22" rst="0">
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="DIEPCTL2_reserved_1" pos="20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DIEPCTL2_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPINT2">
      <bits access="rc" name="DIEPINT2_reserved_1" pos="31:15" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DIEPINT2_reserved_0" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TxfifoUndrn" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="TxFEmp" pos="7" rst="1">
      </bits>
      <bits access="rc" name="INEPNakEff" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknEPMis" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknTXFEmp" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TimeOUT" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPTSIZ2">
      <bits access="rc" name="DIEPTSIZ2_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MC" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMA2">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DTXFSTS2">
      <bits access="rc" name="DTXFSTS2_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="INEPTxFSpcAvail" pos="15:0" rst="297">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMAB2">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DIEPCTL3">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="TxFNum" pos="25:22" rst="0">
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="DIEPCTL3_reserved_1" pos="20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DIEPCTL3_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPINT3">
      <bits access="rc" name="DIEPINT3_reserved_1" pos="31:15" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DIEPINT3_reserved_0" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TxfifoUndrn" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="TxFEmp" pos="7" rst="1">
      </bits>
      <bits access="rc" name="INEPNakEff" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknEPMis" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknTXFEmp" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TimeOUT" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPTSIZ3">
      <bits access="rc" name="DIEPTSIZ3_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MC" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMA3">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DTXFSTS3">
      <bits access="rc" name="DTXFSTS3_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="INEPTxFSpcAvail" pos="15:0" rst="297">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMAB3">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DIEPCTL4">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="TxFNum" pos="25:22" rst="0">
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="DIEPCTL4_reserved_1" pos="20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DIEPCTL4_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPINT4">
      <bits access="rc" name="DIEPINT4_reserved_1" pos="31:15" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DIEPINT4_reserved_0" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TxfifoUndrn" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="TxFEmp" pos="7" rst="1">
      </bits>
      <bits access="rc" name="INEPNakEff" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknEPMis" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknTXFEmp" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TimeOUT" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPTSIZ4">
      <bits access="rc" name="DIEPTSIZ4_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MC" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMA4">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DTXFSTS4">
      <bits access="rc" name="DTXFSTS4_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="INEPTxFSpcAvail" pos="15:0" rst="297">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMAB4">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DIEPCTL5">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="TxFNum" pos="25:22" rst="0">
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rc" name="DIEPCTL5_reserved_1" pos="20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DIEPCTL5_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPINT5">
      <bits access="rc" name="DIEPINT5_reserved_1" pos="31:15" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DIEPINT5_reserved_0" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TxfifoUndrn" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="r" name="TxFEmp" pos="7" rst="1">
      </bits>
      <bits access="rc" name="INEPNakEff" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknEPMis" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="INTknTXFEmp" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="TimeOUT" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DIEPTSIZ5">
      <bits access="rc" name="DIEPTSIZ5_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MC" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMA5">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DTXFSTS5">
      <bits access="rc" name="DTXFSTS5_reserved_0" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="INEPTxFSpcAvail" pos="15:0" rst="297">
      </bits>
    </reg>
    <reg protect="rw" name="DIEPDMAB5">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <hole size="2560"/>
    <reg protect="rw" name="DOEPCTL0">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="r" name="EPDis" pos="30" rst="0">
      </bits>
      <bits access="rc" name="DOEPCTL0_reserved_3" pos="29:28" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rc" name="DOEPCTL0_reserved_2" pos="25:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="Snp" pos="20" rst="0">
      </bits>
      <bits access="r" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="rc" name="DOEPCTL0_reserved_1" pos="16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="USBActEP" pos="15" rst="1">
      </bits>
      <bits access="rc" name="DOEPCTL0_reserved_0" pos="14:2" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="MPS" pos="1:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPINT0">
      <bits access="rc" name="DOEPINT0_reserved_2" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="StupPktRcvd" pos="15" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT0_reserved_1" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OutPktErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT0_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="Back2BackSETup" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="StsPhseRcvd" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OUTTknEPdis" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SetUp" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPTSIZ0">
      <bits access="rc" name="DOEPTSIZ0_reserved_2" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="SUPCnt" pos="30:29" rst="0">
      </bits>
      <bits access="rc" name="DOEPTSIZ0_reserved_1" pos="28:20" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="PktCnt" pos="19" rst="0">
      </bits>
      <bits access="rc" name="DOEPTSIZ0_reserved_0" pos="18:7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="XferSize" pos="6:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DOEPDMA0">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPDMAB0">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DOEPCTL1">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rc" name="DOEPCTL1_reserved_1" pos="25:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="Snp" pos="20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DOEPCTL1_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPINT1">
      <bits access="rc" name="DOEPINT1_reserved_2" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="StupPktRcvd" pos="15" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT1_reserved_1" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OutPktErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT1_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="Back2BackSETup" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="StsPhseRcvd" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OUTTknEPdis" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SetUp" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPTSIZ1">
      <bits access="rc" name="DOEPTSIZ1_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="RxDPID" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DOEPDMA1">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPDMAB1">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DOEPCTL2">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rc" name="DOEPCTL2_reserved_1" pos="25:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="Snp" pos="20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DOEPCTL2_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPINT2">
      <bits access="rc" name="DOEPINT2_reserved_2" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="StupPktRcvd" pos="15" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT2_reserved_1" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OutPktErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT2_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="Back2BackSETup" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="StsPhseRcvd" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OUTTknEPdis" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SetUp" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPTSIZ2">
      <bits access="rc" name="DOEPTSIZ2_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="RxDPID" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DOEPDMA2">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPDMAB2">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DOEPCTL3">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rc" name="DOEPCTL3_reserved_1" pos="25:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="Snp" pos="20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DOEPCTL3_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPINT3">
      <bits access="rc" name="DOEPINT3_reserved_2" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="StupPktRcvd" pos="15" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT3_reserved_1" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OutPktErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT3_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="Back2BackSETup" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="StsPhseRcvd" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OUTTknEPdis" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SetUp" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPTSIZ3">
      <bits access="rc" name="DOEPTSIZ3_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="RxDPID" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DOEPDMA3">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPDMAB3">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DOEPCTL4">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rc" name="DOEPCTL4_reserved_1" pos="25:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="Snp" pos="20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DOEPCTL4_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPINT4">
      <bits access="rc" name="DOEPINT4_reserved_2" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="StupPktRcvd" pos="15" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT4_reserved_1" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OutPktErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT4_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="Back2BackSETup" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="StsPhseRcvd" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OUTTknEPdis" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SetUp" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPTSIZ4">
      <bits access="rc" name="DOEPTSIZ4_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="RxDPID" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DOEPDMA4">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPDMAB4">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <reg protect="rw" name="DOEPCTL5">
      <bits access="rw" name="EPEna" pos="31" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="EPDis" pos="30" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD1PID" pos="29" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SetD0PID" pos="28" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="SNAK" pos="27" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rw" name="CNAK" pos="26" rst="0">
        <comment>
        bit type is changed from w1 to rw.

        </comment>
      </bits>
      <bits access="rc" name="DOEPCTL5_reserved_1" pos="25:22" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="Stall" pos="21" rst="0">
        <comment>
        bit type is changed from othr to rw.

        </comment>
      </bits>
      <bits access="rw" name="Snp" pos="20" rst="0">
      </bits>
      <bits access="rw" name="EPType" pos="19:18" rst="0">
      </bits>
      <bits access="r" name="NAKSts" pos="17" rst="0">
      </bits>
      <bits access="r" name="DPID" pos="16" rst="0">
      </bits>
      <bits access="rw" name="USBActEP" pos="15" rst="0">
      </bits>
      <bits access="rc" name="DOEPCTL5_reserved_0" pos="14:11" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="MPS" pos="10:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPINT5">
      <bits access="rc" name="DOEPINT5_reserved_2" pos="31:16" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="StupPktRcvd" pos="15" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NYETIntrpt" pos="14" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="NAKIntrpt" pos="13" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="BbleErr" pos="12" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="PktDrpSts" pos="11" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT5_reserved_1" pos="10" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="BNAIntr" pos="9" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OutPktErr" pos="8" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="DOEPINT5_reserved_0" pos="7" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rc" name="Back2BackSETup" pos="6" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="StsPhseRcvd" pos="5" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="OUTTknEPdis" pos="4" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="SetUp" pos="3" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="AHBErr" pos="2" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="EPDisbld" pos="1" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
      <bits access="rc" name="XferCompl" pos="0" rst="0">
        <comment>
        bit type is changed from w1c to rc.

        </comment>
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPTSIZ5">
      <bits access="rc" name="DOEPTSIZ5_reserved_0" pos="31" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="RxDPID" pos="30:29" rst="0">
      </bits>
      <bits access="rw" name="PktCnt" pos="28:19" rst="0">
      </bits>
      <bits access="rw" name="XferSize" pos="18:0" rst="0">
      </bits>
    </reg>
    <reg protect="rw" name="DOEPDMA5">
      <bits access="rw" name="DMAAddr" pos="31:0" rst="0">
      </bits>
    </reg>
    <hole size="32"/>
    <reg protect="rw" name="DOEPDMAB5">
      <bits access="rw" name="DMABufferAddr" pos="31:0" rst="0">
        <comment>
        bit type is changed from ru to rw.

        </comment>
      </bits>
    </reg>
    <hole size="4608"/>
    <reg protect="rw" name="PCGCCTL">
      <bits access="rc" name="PCGCCTL_reserved_2" pos="31:8" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="r" name="L1Suspended" pos="7" rst="0">
      </bits>
      <bits access="r" name="PhySleep" pos="6" rst="0">
      </bits>
      <bits access="rc" name="PCGCCTL_reserved_1" pos="5:4" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="RstPdwnModule" pos="3" rst="0">
      </bits>
      <bits access="rc" name="PCGCCTL_reserved_0" pos="2:1" rst="0">
        <comment>
        bit type is changed from dc to rc.

        </comment>
      </bits>
      <bits access="rw" name="StopPclk" pos="0" rst="0">
      </bits>
    </reg>
  </module>
</archive>


<archive relative = "vitac.xml">

<include file="globals.xml"/>

<module name="vitac" category="Baseband">
  <reg protect="rw" name="command">
    <bits access="rw" name="start_equ" pos="0" rst="0x0">
      <comment>Writing a '1' in this register triggers a Viterbi Equalization
      process. Ignored if any Viterbi process is already ongoing. Auto-reset.
      </comment>
    </bits>

    <bits access="rw" name="start_dec" pos="1" rst="0x0">
      <comment>Writing a '1' in this register triggers a Viterbi Decoding
      process. Ignored if any Viterbi process is already ongoing. Auto-reset.
      </comment>
    </bits>

    <bits access="rw" name="start_tb" pos="2" rst="0x0">
      <comment>Writing a '1' in this register triggers the TraceBack process.
      Ignored if any Viterbi process is already ongoing. Auto-reset.
      </comment>
    </bits>

    <bits access="rw" name="int_mask" pos="3" rst="0x0">
      <comment>When this bit is set, it enables the generation of the
      VITAC_DONE_H interrupt. </comment>
    </bits>

    <bits access="rw" name="punctured" pos="4" rst="0x0">
      <comment>Indicates whether a puncturing scheme has to be used during
      decoding. If this bit is set to '0', the code is assumed unpunctured and
      no puncturing matrix is needed. </comment>
    </bits>

    <bits access="rw" name="nb_states" pos="6:5" rst="0x0">
      <comment>This field sets the number of states of the Trellis:
      <br />"00": 16 states <br />"01": 32 states <br />"10": 64 states
      <br />"11": reserved </comment>
    </bits>

    <bits access="rw" name="bkwd_trellis" pos="7" rst="0x0">
      <comment>When this bit is set, the channel symbols are treated in the
      reverse order, i.e. CH_SYMB_ADDR represents the end of the buffer and
      the symbols are read out backward. </comment>
    </bits>

    <bits access="rw" name="code_rate" pos="10:8" rst="0x0">
      <comment>This field sets the convolutional code rate for decoding:
      <br />"010": 1/2 rate <br />"011": 1/3 rate <br />"100": 1/4 rate
      <br />"101": 1/5 rate <br />"110": 1/6 rate <br />others: reserved
      </comment>
    </bits>

    <bits access="rw" name="bm_shift_lev" pos="14:11" rst="0x0">
      <comment>This field sets the amount of shift right applied at the output
      of the equalizer BM calculation: <br />"0000": BM = OUT[30:19]
      <br />"0001": BM = OUT[29:18] <br />... <br />"1111": BM = OUT[15:4]
      </comment>
    </bits>

    <bits access="rw" name="sv_shift_lev" pos="18:15" rst="0x0">
      <comment>This field sets the amount of shift right applied to the
      difference of the two metrics arriving at a node to create a Softvalue:
      <br />"0000": SoftVal = DELTA[15:9] <br />"0001": SoftVal =
      DELTA[14:8] <br />... <br />"1101": SoftVal = DELTA[2:0]&amp;"0000" <br />others:
      reserved </comment>
    </bits>

    <bits access="rw" name="nb_symbols" pos="28:20" rst="0x0">
      <comment>Number of symbols to be Equalized / Decoded. Auto decrement.
      </comment>
    </bits>
  </reg>

  <reg protect="r" name="status">
    <bits access="r" name="equ_pending" pos="0" rst="0x0">
      <comment>This bit is high when an equalization process is ongoing. It
      stays high when the module is stalled during operation. </comment>
    </bits>

    <bits access="r" name="dec pending" pos="1" rst="0x0">
      <comment>This bit is high when an decoding process is ongoing. It stays
      high when the module is stalled during operation. </comment>
    </bits>

    <bits access="r" name="tb_pending" pos="2" rst="0x0">
      <comment>This bit is high when an traceback process is ongoing. It stays
      high when the module is stalled during operation. </comment>
    </bits>

    <bits access="r" name="nb_rescales" pos="7:4" rst="0x0">
      <comment>After a Viterbi process, this field reports the number of
      rescaling operations that have been performed along the trellis.
      <br />This field is reset at every new Viterbi process. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="ch_symb_addr">
    <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
      <comment>This is the start address of the channel symbols buffer in
      SRAM. For Equalization channel symbols are the sampled RF samples
      (2x12-bits packed complex values), and for Decoding channel symbols are
      a frame of softvalues (4x8-bits packed). <br />This address must be
      4-bytes aligned, bits[1:0] will be ignored. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="exp_symb_addr">
    <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
      <comment>For Equalization, this is the base address of the partial sum
      terms buffer in SRAM. (2x12-bits packed complex values) <br />For
      Decoding, this is the base address of the puncturing matrix. <br />This
      address must be 4-bytes aligned, bits[1:0] will be ignored. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="pm_base_addr">
    <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
      <comment>This is the base address in SRAM of the Path Metrics buffer.
      The VITAC will read and update PMs according to the scheme given in
      1.2.1.2. (2x16-bits packed values). <br />This address must be 4-bytes
      aligned, bits[1:0] will be ignored. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="out_base_addr">
    <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
      <comment>This is the start address of the output buffer in SRAM. When in
      Equalizer mode, the VITAC will output the calculated Softvalues
      according to the scheme given in 1.2.1.7. When in Decoder mode, the
      VITAC will output the trace words according to the scheme given in
      1.2.2.4. <br />This address must be 4-bytes aligned, bits[1:0] will be
      ignored. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="H0_param">
    <bits access="rw" name="H0_I_part" pos="BB_SYMBOL_SIZE-1:0" rst="0x0">
      <comment>Real part of the h0 parameter of the estimated channel
      response. </comment>
    </bits>

    <bits access="rw" name="H0_Q_part" pos="BB_SYMBOL_SIZE+15:16" rst="0x0">
      <comment>Imaginary part of the h0 parameter of the estimated channel
      response. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="HL_param">
    <bits access="rw" name="HL_I_part" pos="BB_SYMBOL_SIZE-1:0" rst="0x0">
      <comment>Real part of the hL parameter of the estimated channel
      response. </comment>
    </bits>

    <bits access="rw" name="HL_Q_part" pos="BB_SYMBOL_SIZE+15:16" rst="0x0">
      <comment>Imaginary part of the hL parameter of the estimated channel
      response. </comment>
    </bits>
  </reg>

  <reg protect="rw" name="rescale">
    <bits access="rw" name="threshold" pos="15:0" rst="0x0">
      <comment>This field indicates the threshold value to be reach by every
      PMs for triggering a rescale operation. The rescale operation consist in
      subtracting the threshold value to every PMs to avoid overflow during PM
      update. </comment>
    </bits>
  </reg>

  <reg protect="rw" count="3" name="res_poly">
    <comment>This register bank stores the less significant bit of the output
    from the coder for a particular code (see 1.2.2.1). The kth butterfly uses
    the bit k of this register. </comment>

    <bits access="rw" name="res_poly" pos="31:0" rst="0x0">
      <comment>This register stores the less significant bit of the output
      from the coder for a particular code (see 1.2.2.1). The kth butterfly
      uses the bit k of this register. </comment>
    </bits>
  </reg>

  <reg protect="r" name="int_status">
    <bits access="r" name="it_cause" pos="0" rst="0x0">
      <comment>This bit is set when the VITAC module finishes an ongoing
      operation. It can be masked by setting VITAC_CMD(IT_MASK) to '1'.
      <br />Resetting this bit is done by writing in IT_CLEAR register.
      <br />IT_CAUSE is the image of the VITAC_DONE_H interrupt line to the
      CPU. </comment>
    </bits>

    <bits access="r" name="it_status" pos="16" rst="0x0">
      <comment>This bit is the unmasked version of the IT_CAUSE bit.
      </comment>
    </bits>
  </reg>

  <reg protect="w" name="int_clear">
    <bits access="w" name="it_clear" pos="0" rst="0x0">
      <comment>Setting this bit to '1' resets the VITAC interrupt. </comment>
    </bits>
  </reg>
</module>

</archive>
<archive relative = "voc_ahb.xml">

<include file="voc_global.xml"/>

<module name="voc_ahb" category="VOC">
    <reg name="Irq_Status" protect="r">
        <bits name="XCpu_Voc_Irq_Cause" pos="0" access="r" rst="0">
            <comment>1 when Voc triggered an Irq to the XCpu.
            </comment>
        </bits>
        <bits name="XCpu_Dma_Irq_Cause" pos="1" access="r" rst="0">
            <comment>1 when the DMA triggered an Irq to the XCpu.
            </comment>
        </bits>
        <bits name="XCpu_DmaVoc_Irq_Cause" pos="2" access="r" rst="0">
            <comment>1 when the DMA programmed from Voc triggered an Irq to the XCpu.
            </comment>
        </bits>
        <bits name="XCpu_Debug_Irq_Cause" pos="3" access="r" rst="0">
            <comment>1 when a VoC stall state is reached during debugging.
            </comment>
        </bits>
        <bitgroup name="XCpu_Irq_Cause">
            <entry ref="XCpu_Voc_Irq_Cause"/>
            <entry ref="XCpu_Dma_Irq_Cause"/>
            <entry ref="XCpu_DmaVoc_Irq_Cause"/>
            <entry ref="XCpu_Debug_Irq_Cause"/>
        </bitgroup>
        <bits name="BCpu_Voc_Irq_Cause" pos="8" access="r" rst="0">
            <comment>1 when Voc triggered an Irq to the BCpu.
            </comment>
        </bits>
        <bits name="BCpu_Dma_Irq_Cause" pos="9" access="r" rst="0">
            <comment>1 when the DMA triggered an Irq to the BCpu.
            </comment>
        </bits>
        <bits name="BCpu_DmaVoc_Irq_Cause" pos="10" access="r" rst="0">
            <comment>1 when the DMA programmed from Voc triggered an Irq to the BCpu.
            </comment>
        </bits>
        <bits name="BCpu_Debug_Irq_Cause" pos="11" access="r" rst="0">
            <comment>1 when a VoC stall state is reached during debugging.
            </comment>
        </bits>
        <bitgroup name="BCpu_Irq_Cause">
            <entry ref="BCpu_Voc_Irq_Cause"/>
            <entry ref="BCpu_Dma_Irq_Cause"/>
            <entry ref="BCpu_DmaVoc_Irq_Cause"/>
            <entry ref="BCpu_Debug_Irq_Cause"/>
        </bitgroup>
        <bits name="XCpu_Voc_Irq_Status" pos="16" access="r" rst="0">
            <comment>1 when Voc triggered an Irq to the XCpu. (not masked, status only)
            </comment>
        </bits>
        <bits name="XCpu_Dma_Irq_Status" pos="17" access="r" rst="0">
            <comment>1 when the DMA triggered an Irq to the XCpu. (not masked, status only)
            </comment>
        </bits>
        <bits name="XCpu_DmaVoc_Irq_Status" pos="18" access="r" rst="0">
            <comment>1 when the DMA programmed from Voc triggered an Irq to the XCpu. (not masked, status only)
            </comment>
        </bits>
        <bits name="XCpu_Debug_Irq_Status" pos="19" access="r" rst="0">
            <comment>1 when a VoC stall state is reached during debugging. (not masked, status only)
            </comment>
        </bits>
        <bitgroup name="XCpu_Irq_Status">
            <entry ref="XCpu_Voc_Irq_Status"/>
            <entry ref="XCpu_Dma_Irq_Status"/>
            <entry ref="XCpu_DmaVoc_Irq_Status"/>
            <entry ref="XCpu_Debug_Irq_Status"/>
        </bitgroup>
        <bits name="BCpu_Voc_Irq_Status" pos="24" access="r" rst="0">
            <comment>1 when Voc triggered an Irq to the BCpu (not masked, status only).
            </comment>
        </bits>
        <bits name="BCpu_Dma_Irq_Status" pos="25" access="r" rst="0">
            <comment>1 when the DMA triggered an Irq to the BCpu. (not masked, status only)
            </comment>
        </bits>
        <bits name="BCpu_DmaVoc_Irq_Status" pos="26" access="r" rst="0">
            <comment>1 when the DMA programmed from Voc triggered an Irq to the BCpu. (not masked, status only)
            </comment>
        </bits>
        <bits name="BCpu_Debug_Irq_Status" pos="27" access="r" rst="0">
            <comment>1 when a VoC stall state is reached during debugging. (not masked, status only)
            </comment>
        </bits>
        <bitgroup name="BCpu_Irq_Status">
            <entry ref="BCpu_Voc_Irq_Status"/>
            <entry ref="BCpu_Dma_Irq_Status"/>
            <entry ref="BCpu_DmaVoc_Irq_Status"/>
            <entry ref="BCpu_Debug_Irq_Status"/>
        </bitgroup>
    </reg>
    <reg name="Irq_Mask_Set" protect="rs">
        <bits name="XCpu_Voc_Irq_Mask" pos="0" access="rs" rst="0">
            <comment>Write 1 to set the mask for Voc Irq to the XCpu.
            </comment>
        </bits>
        <bits name="XCpu_Dma_Irq_Mask" pos="1" access="rs" rst="0">
            <comment>Write 1 to set the mask for DMA Irq to the XCpu.
            </comment>
        </bits>
        <bits name="XCpu_DmaVoc_Irq_Mask" pos="2" access="rs" rst="0">
            <comment>Write 1 to set the mask for DMA Irq to the XCpu when the DMA is programmed from Voc.
            </comment>
        </bits>
        <bits name="XCpu_Debug_Irq_Mask" pos="3" access="rs" rst="0">
            <comment>Write 1 to set the mask for Debug Irq to the XCpu.
            </comment>
        </bits>
        <bitgroup name="XCpu_Irq_Mask">
            <entry ref="XCpu_Voc_Irq_Mask"/>
            <entry ref="XCpu_Dma_Irq_Mask"/>
            <entry ref="XCpu_DmaVoc_Irq_Mask"/>
            <entry ref="XCpu_Debug_Irq_Mask"/>
        </bitgroup>
        <bits name="BCpu_Voc_Irq_Mask" pos="8" access="rs" rst="0">
            <comment>Write 1 to set the mask for Voc Irq to the BCpu.
            </comment>
        </bits>
        <bits name="BCpu_Dma_Irq_Mask" pos="9" access="rs" rst="0">
            <comment>Write 1 to set the mask for DMA Irq to the BCpu.
            </comment>
        </bits>
        <bits name="BCpu_DmaVoc_Irq_Mask" pos="10" access="rs" rst="0">
            <comment>Write 1 to set the mask for DMA Irq to the BCpu when the DMA is programmed from Voc.
            </comment>
        </bits>
        <bits name="BCpu_Debug_Irq_Mask" pos="11" access="rs" rst="0">
            <comment>Write 1 to set the mask for Debug Irq to the BCpu.
            </comment>
        </bits>
        <bitgroup name="BCpu_Irq_Mask">
            <entry ref="BCpu_Voc_Irq_Mask"/>
            <entry ref="BCpu_Dma_Irq_Mask"/>
            <entry ref="BCpu_DmaVoc_Irq_Mask"/>
            <entry ref="BCpu_Debug_Irq_Mask"/>
        </bitgroup>
    </reg>
    <reg name="Irq_Mask_Clr" protect="rc">
        <bits name="XCpu_Voc_Irq_Mask" pos="0" access="rc" rst="0">
            <comment>Write 1 to clear the mask for Voc Irq to the XCpu.
            </comment>
        </bits>
        <bits name="XCpu_Dma_Irq_Mask" pos="1" access="rc" rst="0">
            <comment>Write 1 to clear the mask for DMA Irq to the XCpu.
            </comment>
        </bits>
        <bits name="XCpu_DmaVoc_Irq_Mask" pos="2" access="rc" rst="0">
            <comment>Write 1 to clear the mask for DMA Irq to the XCpu when the DMA is programmed from Voc.
            </comment>
        </bits>
        <bits name="XCpu_Debug_Irq_Mask" pos="3" access="rc" rst="0">
            <comment>Write 1 to clear the mask for Debug Irq to the XCpu.
            </comment>
        </bits>
        <bitgroup name="XCpu_Irq_Mask">
            <entry ref="XCpu_Voc_Irq_Mask"/>
            <entry ref="XCpu_Dma_Irq_Mask"/>
            <entry ref="XCpu_DmaVoc_Irq_Mask"/>
            <entry ref="XCpu_Debug_Irq_Mask"/>
        </bitgroup>
        <bits name="BCpu_Voc_Irq_Mask" pos="8" access="rc" rst="0">
            <comment>Write 1 to clear the mask for Voc Irq to the BCpu.
            </comment>
        </bits>
        <bits name="BCpu_Dma_Irq_Mask" pos="9" access="rc" rst="0">
            <comment>Write 1 to clear the mask for DMA Irq to the BCpu.
            </comment>
        </bits>
        <bits name="BCpu_DmaVoc_Irq_Mask" pos="10" access="rc" rst="0">
            <comment>Write 1 to clear the mask for DMA Irq to the BCpu when the DMA is programmed from Voc.
            </comment>
        </bits>
        <bits name="BCpu_Debug_Irq_Mask" pos="11" access="rc" rst="0">
            <comment>Write 1 to clear the mask for Debug Irq to the BCpu.
            </comment>
        </bits>
        <bitgroup name="BCpu_Irq_Mask">
            <entry ref="BCpu_Voc_Irq_Mask"/>
            <entry ref="BCpu_Dma_Irq_Mask"/>
            <entry ref="BCpu_DmaVoc_Irq_Mask"/>
            <entry ref="BCpu_Debug_Irq_Mask"/>
        </bitgroup>
    </reg>
    <reg name="DMA_Cfg" protect="rw">
        <bits name="DMA_SizeLow" pos="1:0" access="r" rst="0">
            <comment>Ignored on write, read as 0, so DMA_Size can be programmed in 15:0 as a byte size as long as the size in a multiple of 4.
            </comment>
        </bits>
        <bits name="DMA_WSize" pos="15:2" access="rw" rst="all1">
            <comment>Number of 32bits Words to transfer.
            </comment>
        </bits>
        <bitgroup name="DMA_Size">
            <entry ref="DMA_SizeLow"/>
            <entry ref="DMA_WSize"/>
        </bitgroup>
        <bits name="DMA_Run" pos="16" access="rw" rst="0">
            <comment>Start the DMA transfer
            </comment>
          </bits>
        <bits name="Dma_Single_cfg" pos="19" access="r" rst="0">
        </bits>          
        <bits name="DMA_Dir" pos="20" access="rw" rst="1">
            <comment>Set the DMA transfer direction
            </comment>
            <options>
                <option name="Read" value="0"><comment>Read from main memory to Voc Memory</comment></option>
                <option name="Write" value="1"><comment>Write to main memory from Voc Memory</comment></option>
            </options>
        </bits>
        <bits name="DMA_B2S_En" pos="21" access="rw" rst="1">
            <comment>Enable the byte to short mode (b2s). For read access : every byte read from the external memory is cast to short and written to the internal memory (twice as much data written than received). For write access : every short read from the internal memory is trunkated to byte and written to the external memory (twice less data written than read). In both cases the size corresponds to the number of words transfered on the AHB.
            </comment>
        </bits>
        <bits name="DMA_B2S_Sign" pos="22" access="rw" rst="1">
            <comment> For read access only (byte to short cast): define if the cast is signed or unsigned.
            </comment>
        </bits>        
        <bits name="DMA_Wrap" pos="27:24" access="rw" rst="all1">
            <comment>Set the DMA wrap mode, refer to Voc documentation for a description of Wrap transfers.
            </comment>
        </bits>
    </reg>
    <reg name="DMA_LAddr" protect="rw">
        <bits name="DMA_LAddr" pos="16:1" access="rw" rst="0">
            <comment>DMA Local Address: Address in the Voc memory space.
            </comment>
            <options> 
                <mask/>
            </options>
        </bits>
    </reg>
    <reg name="DMA_EAddr" protect="rw">
        <bits name="DMA_EAddr" pos="AHB_NB_BITS_ADDR-1:2" access="rw" rst="0">
            <comment>DMA External Address: Address in the main memory space.
            </comment>
            <options> 
                <mask/>
            </options>
        </bits>
        <bits name="DMA_Single_B2S_En" pos="28" access="w" rst="0">
            <comment>Same as DMA_B2S_En, but  valid only when the DMA_Single bit is enabled.
            </comment>
        </bits>
        <bits name="DMA_Single_B2S_Sign" pos="29" access="w" rst="0">
            <comment> For read access only (byte to short cast): define if the cast is signed or unsigned.
            </comment>
        </bits>          
        <bits name="DMA_Write" pos="30" access="w" rst="0">
            <comment>Set the DMA transfer direction, valid only when the DMA_Single bit is enabled.
            </comment>
            <options>
                <option name="Read" value="0"><comment>Read from main memory to Voc Memory</comment></option>
                <option name="Write" value="1"><comment>Write to main memory from Voc Memory</comment></option>
            </options>
        </bits>
        <bits name="DMA_Single" pos="31" access="w" rst="0">
            <comment>When 1 start a DMA transfer in Single mode, the data is tranfered to/from the DMA_Data_Single register.
                <br/>When 0 start a regular DMA transfer using LAddr and Size.
            </comment>
        </bits>
    </reg>
    <reg name="DMA_Status" protect="r">
        <bits name="DMA_On" pos="0" access="r" rst="0">
            <comment>1 when DMA is running.
            </comment>
        </bits>
        <bits name="DMA_Sema_Status" pos="31" access="r" rst="1">
            <comment>Read the value of the DMA Semaphore without affecting it.
            </comment>
        </bits>
    </reg>
    <reg name="DMA_Sema" protect="w">
        <bits name="DMA_Sema" pos="1" access="w" rst="1">
            <comment>Read the value of the DMA Semaphore:
                <br/>If 1 is returned the DMA was available and is know taken.
                <br/>If 0 is returned the DMA is not available, you need to try again to get it. The software can wait on any DMA Irq before retrying if Sema is never free manually.
                <br/>Write 1 to free manually (got the semaphore and want to discard it without prgrammin a transfer.)
                <br/>The end of the DMA will also free the Semaphone.
            </comment>
        </bits>
    </reg>
    <reg name="DMA_2D" protect="rw">
        <bits name="DMA_StrideLow" pos="1:0" access="r" rst="0">
            <comment>Ignored on write, read as 0, so DMA_Stride can be programmed as a byte size as long as the size in a multiple of 4.
            </comment>
        </bits>
        <bits name="DMA_WStride" pos="12:2" access="rw" rst="all0">
            <comment> Stride in Words (without the 2 lsb). The stride of the 2D transfer corresponds to the step from one line to another excluding the burst size (in bytes). Example : If the size is 12 bytes (3 words) and the stride is 20 bytes (5 words), starting from word position N, the DMA will transfer words at positions N, N+1, N+2, N+8, N+9, N+10, N+16, N+17, N+18, etc... If the number of lines is L this example will access a block with dimensions 3xL inside a block of size 8xL.
            </comment>
        </bits>
        <bitgroup name="DMA_Stride">
            <entry ref="DMA_StrideLow"/>
            <entry ref="DMA_WStride"/>
        </bitgroup>
        <bits name="DMA_Lines" pos="27:16" access="rw" rst="0">
            <comment>Number of lines of the 2D transfer. Example : this corresponds to the number L in the previous example.
            </comment>
        </bits>
    </reg>    
    <reg name="DMA_Stop" protect="w">
        <bits name="DMA_Stop" pos="0" access="w" rst="0">
            <comment>Write 1 to this register to cleanly stop the DMA. Note : a last burst may be on going when you requested the clean stop, and no more bursts will be executed after this last burst. Because of this potential last on going burst you need to poll the DMA_On field of the DMA_Status register to verify the completion of the DMA.
            </comment>
        </bits>
    </reg>

    
</module>

</archive>
<archive relative = "voc_cfg.xml">

<include file="voc_global.xml"/>

<module name="voc_cfg" category="VOC">
    <reg16 name="Ctrl" protect="rw">
        <bits name="Run" pos="2:0" access="w" rst="0">
            <options>
                <option name="Pause" value="0"><comment>Pause VoC (no pipe flush). When paused, all events that wake up VoC (start, soft wake up, or wake up on extern event) will resume the execution from where it was paused.</comment></option>
                <option name="SoftWakeUp0" value="1"><comment>CPU generated event with id=0 that can wake VoC if the coresponding bit in the Wakeup_Mask register is set to '1'.</comment></option>
                <option name="SoftWakeUp1" value="3"><comment>CPU generated event with id=1 that can wake VoC if the coresponding bit in the Wakeup_Mask register is set to '1'</comment></option>
                <option name="Stop" value="4"><comment>Stop VoC and flush pipe. Used when the current task is finished (because the next task will have a different PC start). The PC start change should mandatorily be preceeded by a Stop. This ensures that no previously executed code that is still in the pipe will modify the registry during the first two instructions of the new task execution.</comment></option>
                <option name="Start" value="5"><comment>Wake up VoC regardless of the Wakeup_Mask setting (force wake up)</comment></option>
            </options>
        </bits>
        <bits name="BCPU_irq" pos="4" access="w" rst="0">
            <comment>Writing '1' will generate an internal pulse recorded in the Irq_Status register of the voc_ahb interface (see voc_ahb registers). If the corresponding bit of the Irq_Mask vector is set to '1', a level interrupt will be generated to the BCPU. Should be configured by VoC_core only (not by a CPU)!
            </comment>
        </bits>
        <bits name="XCPU_irq" pos="5" access="w" rst="0">
            <comment>Writing '1' will generate an internal pulse recorded in the Irq_Status register of the voc_ahb interface (see voc_ahb registers). If the corresponding bit of the Irq_Mask vector is set to '1', a level interrupt will be generated to the XCPU. Should be configured by VoC_core only (not by a CPU)!
            </comment>
        </bits>
        <bits name="Running" pos="0" access="r" rst="0">
            <options>
                <option name="Yes" value="1"><comment>VoC is running</comment></option>
                <option name="No" value="0"><comment>VoC is paused or stopped</comment></option>
                <default/>
            </options>
        </bits>
        <bits name="Sema_Status" pos="1" access="r" rst="1">
            <comment>Status of the VoC semaphore (reading this bit will not modify the semaphore).
            </comment>
        </bits>
        <bits name="Status_spy_wr_err" pos="2" access="r" rst="0">
            <comment>
            </comment>
        </bits>
	</reg16>
	<reg16 name="DMA_Wrap" protect="">
        <comment>Should be configured by VoC_core only (not by a CPU)! If VoC DMA is used by the CPU the equivalent voc_ahb registers should be configured.
        </comment>
        <bits name="DMA_Wrap" pos="3:0" access="w" rst="all0">
            <comment>Wrap register. 0 : no wrap, wrap_val (other than 0): the wrap_val LSB bits of the Word wrap address are at '0'.
            </comment>
        </bits>
    </reg16>
    <reg16 name="DMA_Size" protect="">
        <comment>Should be configured by VoC_core only (not by a CPU)! If VoC DMA is used by the CPU the equivalent voc_ahb registers should be configured.
        </comment>
        <bits name="DMA_Size" pos="13:0" access="w" rst="all0">
            <comment>Word Size of the DMA Transfer (number of INT32 to transfer) 
            </comment>
        </bits>
    </reg16>
    <reg16 name="DMA_Laddr" protect="">        
        <comment>Should be configured by VoC_core only (not by a CPU)! If VoC DMA is used by the CPU the equivalent voc_ahb registers should be configured.
        </comment>
        <bits name="DMA_LAddr" pos="15:0" access="w" rst="all0">
            <comment>DMA Local Word Address: Address in the Voc memory space.
            </comment>
        </bits>
    </reg16>
    <reg name="DMA_EAddr" protect="">
        <comment>Should be configured by VoC_core only (not by a CPU)! If VoC DMA is used by the CPU the equivalent voc_ahb registers should be configured.
        </comment>
        <bits name="DMA_EAddr" pos="AHB_NB_BITS_ADDR-1:2" access="w" rst="0">
            <comment>DMA External Byte Address (aligned to Word address, the 2 lsb are always '0'): Address in the main memory space.
            </comment>
            <options> 
                <mask/>
            </options>
        </bits>
        <bits name="DMA_B2S_En" pos="28" access="w" rst="0">
            <comment>Enable the byte to short mode (b2s). For read access : every byte read from the external memory is cast to short and written to the internal memory (twice as much data written than received). For write access : every short read from the internal memory is trunkated to byte and written to the external memory (twice less data written than read). In both cases the size corresponds to the number of words transfered on the AHB.
            </comment>
        </bits>
        <bits name="DMA_B2S_Sign" pos="29" access="w" rst="0">
            <comment> For read access only (byte to short cast): define if the cast is signed or unsigned.
            </comment>
        </bits>        
        <bits name="DMA_Write" pos="30" access="w" rst="0">
            <comment>Set the DMA transfer direction
            </comment>
            <options>
                <option name="Read" value="0"><comment>Read from main memory to Voc Memory</comment></option>
                <option name="Write" value="1"><comment>Write to main memory from Voc Memory</comment></option>
            </options>
        </bits>
        <bits name="DMA_Single" pos="31" access="w" rst="0">
            <comment>When 1 start a DMA transfer in Single mode, the data is tranfered to/from the DMA_Data_Single register.
                <br/>When 0 start a regular DMA transfer using LAddr and Size.
            </comment>
        </bits>
    </reg>
    <reg name="DMA_Data_Single" protect="rw">
        <bits name="DMA_Data_Single" pos="31:0" access="rw" rst="0">
            <comment>DMA Data for Single Access (source or destination depending on direction)
            </comment>
        </bits>
    </reg>
    <reg name="DMA_2D" protect="">
        <bits name="DMA_Stride" pos="12:0" access="w" rst="0">
            <comment>Stride in bytes of the 2D transfer, corresponding to the step from one line to another excluding the burst size (in bytes). Example : If the size is 12 bytes (3 words) and the stride is 20 bytes (5 words), starting from word position N, the DMA will transfer words at positions N, N+1, N+2, N+8, N+9, N+10, N+16, N+17, N+18, etc... If the number of lines is L this example will access a block with dimensions 3xL inside a block of size 8xL.
            </comment>
        </bits>
        <bits name="DMA_Lines" pos="27:16" access="w" rst="0">
            <comment>Number of lines of the 2D transfer. Example : this corresponds to the number L in the previous example.
            </comment>
        </bits>
    </reg>        
    <hole size="32"/>
    <reg16 name="DAI_Data_In" protect="r">
        <bits name="DAI_Data_In" pos="12:0" access="r" rst="0">
            <comment>Data from DAI Simple interface.
            </comment>
        </bits>
        <bits name="DAI_Data_Ready" pos="15" access="r" rst="0">
            <comment>Data ready.
            </comment>
        </bits>       
    </reg16>
    <reg16 name="DAI_Data_Out" protect="w">
        <bits name="DAI_Data_Out" pos="12:0" access="w">
            <comment>Data for DAI Simple.
            </comment>
        </bits>
    </reg16>
    <reg16 name="ROM_Page" protect="" rst="0">
        <bits name="ROM_Page" pos="15:0" access="rw" rst="0">
           <comment>Number of the ROM page when a ROM bigger than 1 page is defined in voc_cfg_pkg.vhd. Otherwise this register does not exist.
           </comment>
        </bits>
    </reg16>
    <reg16 name="Debug" protect="rw" rst="0">
        <bits name="stall_on_bkp" pos="0" access="rw" rst="0">
           <comment>Enable or disable stall on hardware breakpoint.
           </comment>
        </bits>
        <bits name="stall_on_branch_taken" pos="1" access="rw" rst="0">
           <comment>Enable or disable stall when a branch is taken in the program.
           </comment>
        </bits>
        <bits name="step" pos="2" access="rw" rst="0">
           <comment>Enable or disable step mode (execute 1 instruction and stall).
           </comment>
        </bits>
    </reg16>
    <reg name="BIST_Ctrl"  protect="rw">
       <bits name="BIST_Run" pos="0" access="w" rst="0">
            <comment>'1' : start.
            </comment>
       </bits>
       <bits name="BIST_Running" pos="0" access="r" rst="0">
            <comment>'0' : done.
            </comment>
       </bits>
       <bits name="BIST_Status" pos="1" access="r" rst="0">
            <comment>'1' : fail. '0' : succeed. Valid when BIST_Running is at '0'.
            </comment>
       </bits>        
       <bits name="BIST_CRC" pos="31:16" access="r" rst="0">
            <comment>16-bit CRC result of the ROM. Valid when BIST_Running is at '0'.
            </comment>
       </bits>        
    </reg>
    <reg16 name="Wakeup_Mask" protect="rw">
       <bits name="IFC0_Event_Mask" pos="0" access="rw" rst="0">
            <comment>Mask enabling the IFC0 half or whole buffer event.
            </comment>
       </bits>        
       <bits name="IFC1_Event_Mask" pos="1" access="rw" rst="0">
            <comment>Mask enabling the IFC1 half or whole buffer event.
            </comment>
       </bits>
       <bits name="DMAE_Event_Mask" pos="2" access="rw" rst="0">
            <comment>Mask enabling the DMAE event (DMA configured by extern master done).
            </comment>
       </bits>
       <bits name="DMAI_Event_Mask" pos="3" access="rw" rst="0">
            <comment>Mask enabling the DMAI event (DMA configured by VoC core done).
            </comment>
       </bits>
       <bits name="SOF0_Event_Mask" pos="4" access="rw" rst="0">
            <comment>Mask enabling the SOF0 event (Soft Wake Up with Id=0 generated by writing the corresponding value in the control register).
            </comment>
       </bits>
       <bits name="SOF1_Event_Mask" pos="5" access="rw" rst="0">
            <comment>Mask enabling the SOF1 event (Soft Wake Up with Id=1 generated by writing the corresponding value in the control register).
            </comment>
       </bits>
       <bitgroup name="Wakeup_Mask">
            <entry ref="IFC0_Event_Mask"/>
            <entry ref="IFC1_Event_Mask"/>
            <entry ref="DMAE_Event_Mask"/>
            <entry ref="DMAI_Event_Mask"/>
            <entry ref="SOF0_Event_Mask"/>
            <entry ref="SOF1_Event_Mask"/>
        </bitgroup>
    </reg16>
    <hole size="16"/>
    <reg16 name="Wakeup_Status" protect="rc">
       <bits name="IFC0_Event_Status" pos="0" access="rc" rst="0">
            <comment>'1': Triggered IFC0 event. Write '1' to clear.
            </comment>
       </bits>        
       <bits name="IFC1_Event_Status" pos="1" access="rc" rst="0">
            <comment>'1': Triggered IFC1 event. Write '1' to clear.
            </comment>
       </bits>
       <bits name="DMAE_Event_Status" pos="2" access="rc" rst="0">
            <comment>'1': Triggered DMAE event. Write '1' to clear.
            </comment>
       </bits>
       <bits name="DMAI_Event_Status" pos="3" access="rc" rst="0">
            <comment>'1': Triggered DMAI event. Write '1' to clear.
            </comment>
       </bits>
       <bits name="SOF0_Event_Status" pos="4" access="rc" rst="0">
            <comment>'1': Triggered SOF0 event. Write '1' to clear.
            </comment>
       </bits>
       <bits name="SOF1_Event_Status" pos="5" access="rc" rst="0">
            <comment>'1': Triggered SOF1 event. Write '1' to clear.
            </comment>
       </bits>
       <bitgroup name="Wakeup_Status">
            <entry ref="IFC0_Event_Status"/>
            <entry ref="IFC1_Event_Status"/>
            <entry ref="DMAE_Event_Status"/>
            <entry ref="DMAI_Event_Status"/>
            <entry ref="SOF0_Event_Status"/>
            <entry ref="SOF1_Event_Status"/>
        </bitgroup>
    </reg16>
    <reg16 name="Wakeup_Cause" access="r" rst="0">
       <comment>Logical AND of Wakeup_Status and Wakeup_Mask (show only the enabled events).
       </comment>
       <bits name="IFC0_Event_Cause" pos="0" access="r" rst="0">
       </bits>        
       <bits name="IFC1_Event_Cause" pos="1" access="r" rst="0">
       </bits>
       <bits name="DMAE_Event_Cause" pos="2" access="r" rst="0">
       </bits>
       <bits name="DMAI_Event_Cause" pos="3" access="r" rst="0">
       </bits>
       <bits name="SOF0_Event_Cause" pos="4" access="r" rst="0">
       </bits>
       <bits name="SOF1_Event_Cause" pos="5" access="r" rst="0">
       </bits>
    </reg16>  
    <reg16 name="Sema" protect="w">
       <bits name="Sema" pos="0" access="w" rst="1">
            <comment>VoC semaphore. If the register is read when the field = '1', the field = '0' on the next VoC clock cycle. Can write '0' or '1' in this field.
            </comment>
       </bits>
    </reg16>
    <hole size="144"/>
    <reg name="REG01" protect="rw">
        <bits name="REG0" pos="15:0" access="rw" rst="0">
            <comment>Voc General Register REG0
            </comment>
        </bits>
        <bits name="REG1" pos="31:16" access="rw" rst="0">
            <comment>Voc General Register REG1
            </comment>
        </bits>
        <l name="REG0"/>
        <h name="REG1"/>
    </reg>
    <reg name="REG23" protect="rw">
        <bits name="REG2" pos="15:0" access="rw" rst="0">
            <comment>Voc General Register REG2
            </comment>
        </bits>
        <bits name="REG3" pos="31:16" access="rw" rst="0">
            <comment>Voc General Register REG3
            </comment>
        </bits>
        <l name="REG2"/>
        <h name="REG3"/>
    </reg>
    <reg name="REG45" protect="rw">
        <bits name="REG4" pos="15:0" access="rw" rst="0">
            <comment>Voc General Register REG4
            </comment>
        </bits>
        <bits name="REG5" pos="31:16" access="rw" rst="0">
            <comment>Voc General Register REG5
            </comment>
        </bits>
        <l name="REG4"/>
        <h name="REG5"/>
    </reg>
    <reg name="REG67" protect="rw">
        <bits name="REG6" pos="15:0" access="rw" rst="0">
            <comment>Voc General Register REG6
            </comment>
        </bits>
        <bits name="REG7" pos="31:16" access="rw" rst="0">
            <comment>Voc General Register REG7
            </comment>
        </bits>
        <l name="REG6"/>
        <h name="REG7"/>
    </reg>
    <reg name="ACC0" protect="rw">
        <bits name="ACC0_LO" pos="15:0" access="rw" rst="0">
            <comment>Voc Accumulator Register ACC0 (lo)
            </comment>
        </bits>
        <bits name="ACC0_HI" pos="31:16" access="rw" rst="0">
            <comment>Voc Accumulator Register ACC0 (hi)
            </comment>
        </bits>
        <l name="ACC0_lo"/>
        <h name="ACC0_hi"/>
    </reg>
    <reg name="ACC1" protect="rw">
        <bits name="ACC1_LO" pos="15:0" access="rw" rst="0">
            <comment>Voc Accumulator Register ACC1 (lo)
            </comment>
        </bits>
        <bits name="ACC1_HI" pos="31:16" access="rw" rst="0">
            <comment>Voc Accumulator Register ACC1 (hi)
            </comment>
        </bits>
        <l name="ACC1_lo"/>
        <h name="ACC1_hi"/>
    </reg>
    <reg name="RL6" protect="rw">
        <bits name="RL6_LO" pos="15:0" access="rw" rst="0">
            <comment>Voc General Register RL6 (lo)
            </comment>
        </bits>
        <bits name="RL6_HI" pos="31:16" access="rw" rst="0">
            <comment>Voc General Register RL6 (hi)
            </comment>
        </bits>
        <l name="RL6_lo"/>
        <h name="RL6_hi"/>
    </reg>
    <reg name="RL7" protect="rw">
        <bits name="RL7_LO" pos="15:0" access="rw" rst="0">
            <comment>Voc General Register RL7 (lo)
            </comment>
        </bits>
        <bits name="RL7_HI" pos="31:16" access="rw" rst="0">
            <comment>Voc General Register RL7 (hi)
            </comment>
        </bits>
        <l name="RL7_lo"/>
        <h name="RL7_hi"/>
    </reg>
    <reg16 name="PC" protect="rw">
        <bits name="PC" pos="15:0" access="rw" rst="0">
            <comment>Voc Program Counter Register PC
            </comment>
        </bits>
    </reg16>
    <reg16 name="RA" protect="rw">
        <bits name="RA" pos="15:0" access="rw" rst="0">
            <comment>Voc Return Address Register RA
            </comment>
        </bits>
    </reg16>
    <reg16 name="SP16" protect="rw">
        <bits name="SP16" pos="15:0" access="rw" rst="0">
            <comment>Voc Stack Register SP16
            </comment>
        </bits>
    </reg16>
    <reg16 name="SP32" protect="rw">
        <bits name="SP32" pos="15:0" access="rw" rst="0">
            <comment>Voc Stack Register SP32
            </comment>
        </bits>
    </reg16>
    <hole size="64"/>
    <reg16 name="BKP" protect="rw">
        <bits name="BKP" pos="15:0" access="rw" rst="0">
            <comment>Voc Program Breakpoint Register. Valid when the Dbg_On mode in the Ctrl register is set to '1'
            </comment>
        </bits>
    </reg16>
    <hole size="16"/>
    <reg16 name="PC_PREV" protect="r">
        <bits name="PC_PREV" pos="15:0" access="r" rst="0">
            <comment>Previous PC value. Used to track the source PC of a branch when the stall_on_branch_taken bit in the Debug register is enabled
            </comment>
        </bits>
    </reg16>
    <reg16 name="LOOP" protect="r">
        <bits name="LOOP0" pos="7:0" access="r" rst="0">
            <comment>Loop 0 counter value
            </comment>
        </bits>
        <bits name="LOOP1" pos="15:8" access="r" rst="0">
            <comment>Loop 1 counter value
            </comment>
        </bits>
    </reg16>
    
</module>

</archive>
<archive relative = "voc_ram.xml">
<module name="voc_ram" category="VOC">

    <var name="VOC_RAM_X_SIZE" value="0x5000"/>
    <var name="VOC_RAM_Y_SIZE" value="0x5000"/>
    <var name="VOC_ROM_Z_SIZE" value="0x0000"/>
    <var name="VOC_RAM_I_SIZE" value="0x5000"/>

    <var name="VOC_RAM_X_SPACE" value="0x8000"/>
    <var name="VOC_RAM_Y_SPACE" value="0x8000"/>
    <var name="VOC_ROM_Z_SPACE" value="0x10000"/>
    <var name="VOC_RAM_I_SPACE" value="0x20000"/>
    
    <memory name="voc_ram_x_base" size="VOC_RAM_X_SIZE">
        <comment>VoC RAM X space. 
        </comment>
    </memory>
    <memory name="voc_ram_x_hole" size="VOC_RAM_X_SPACE - VOC_RAM_X_SIZE">
        <comment>VoC RAM X whole. 
        </comment>
    </memory>
    <memory name="voc_ram_y_base" size="VOC_RAM_Y_SIZE">
        <comment>VoC RAM Y space. 
        </comment>
    </memory>
    <memory name="voc_ram_y_hole" size="VOC_RAM_Y_SPACE - VOC_RAM_Y_SIZE">
        <comment>VoC RAM Y whole. 
        </comment>
    </memory>
    <memory name="voc_rom_z_hole" size="VOC_ROM_Z_SPACE - VOC_ROM_Z_SIZE">
        <comment>VoC ROM Y whole. 
        </comment>
    </memory>
    <memory name="voc_ram_i_base" size="VOC_RAM_I_SIZE">
        <comment>VoC RAM I space. 
        </comment>
    </memory>
    <memory name="voc_ram_i_hole" size="VOC_RAM_I_SPACE - VOC_RAM_I_SIZE">
        <comment>VoC RAM I whole. 
        </comment>
    </memory>

</module>

</archive>
<archive relative = "wdt.xml">

<module name="wdt" category="System">

  <reg name="wdt_cvr0" protect="rw">
    <bits access="rw" name="count_value_0" pos="23:0" rst="0xffffff">
    </bits>
  </reg>

  <reg name="wdt_cvr1" protect="rw">
    <bits access="rw" name="count_value_1" pos="23:0" rst="0xffffff">
    </bits>
  </reg>

  <reg name="wdt_cr" protect="rw">
    <bits access="rw" name="mode" pos="4:4" rst="0x1">
    </bits>
    <bits access="rw" name="reset_length" pos="2:0" rst="0x0">
    </bits>
  </reg>

  <reg name="wdt_cmd" protect="rw">
    <bits access="rw" name="cmd" pos="7:0" rst="0x0">
    </bits>
  </reg>

  <reg name="wdt_icr" protect="rw">
    <bits access="rw" name="int_clr" pos="0:0" rst="0x0">
    </bits>
  </reg>

  <reg name="wdt_sr" protect="r">
    <bits access="r" name="wdt_active" pos="1:1" rst="0x0">
    </bits>
    <bits access="r" name="int_assert" pos="0:0" rst="0x0">
    </bits>
  </reg>

</module>
</archive>



<archive relative = "xcor.xml">

<include file="globals.xml"/>

<module name="xcor" category="Baseband">
  <var name="XCOR_SYMBOL_SIZE" value="VITAC_MULT_SIZE" />

  <var name="XCOR_SADDER_SIZE" value="XCOR_SYMBOL_SIZE+1 +6" />

  <reg name="command" protect="rw">
    <bits access="rw" name="biterr_en" pos="0" rst="0x0">
      <comment>Enables the Biterror calculation mode. Auto-reset. </comment>
    </bits>

    <bits access="rw" name="dco1p_en" pos="1" rst="0x0">
      <comment>Enables the DC Offset Correction (1st pass) mode. Auto-reset.
      </comment>
    </bits>

    <bits access="rw" name="dco2p_en" pos="2" rst="0x0">
      <comment>Enables the DC Offset Correction (2nd pass) mode. Auto-reset.
      </comment>
    </bits>

    <bits access="rw" name="dco3p_en" pos="3" rst="0x0">
      <comment>Enables the DC Offset Correction (3rd pass) mode. Auto-reset.
      </comment>
    </bits>

    <bits access="rw" name="tscxc_en" pos="4" rst="0x0">
      <comment>Enables the Training Sequence Cross-Correlation mode.
      Auto-reset. </comment>
    </bits>

    <bits access="rw" name="srec_en" pos="5" rst="0x0">
      <comment>Enables the Symbol Re-Construction mode. Auto-reset. </comment>
    </bits>

    <bits access="rw" name="bext_en" pos="6" rst="0x0">
      <comment>Enables the Bit Extraction mode. Auto-reset. </comment>
    </bits>

    <bits access="rw" name="sproc_en" pos="7" rst="0x0">
      <comment>Enables the Sum Of PROduCt mode. Auto-reset. </comment>
    </bits>

    <bits access="rw" name="chest_en" pos="8" rst="0x0">
      <comment>Enables the Channel Estimation mode. Auto-reset. </comment>
    </bits>

    <bits access="rw" name="fchxc_en" pos="9" rst="0x0">
      <comment>Enables the FCH Xcorrelation mode. Auto-reset. </comment>
    </bits>

    <bits access="rw" name="sldwin_en" pos="10" rst="0x0">
      <comment>Enables the Sliding window mode. Auto-reset. </comment>
    </bits>

    <bits access="rw" name="it_mask" pos="11" rst="0x0">
      <comment>Mask of the end of processing interrupt.</comment>
    </bits>

    <bits access="rw" name="pack_IQ" pos="12" rst="0x0">
      <comment>Data path setting. Pack I and Q on a single 32-bits word.
      </comment>
    </bits>

    <bits access="rw" name="derotation_en" pos="13" rst="0x0">
      <comment>Data path setting. Enables derotation for DCOC 3pass.
      </comment>
    </bits>

    <bits access="rw" name="nb_iloop" pos="23:16" rst="0x0">
      <comment>Control setting. Number of internal loop iteration. </comment>
    </bits>

    <bits access="rw" name="nb_symb" pos="31:24" rst="0x0">
      <comment>Control setting. Number of symbols to process. </comment>
    </bits>
  </reg>

  <reg name="status" protect="rw">
    <bits access="r" name="op_pending" pos="0" rst="0x0">
      <comment>This bit is high when an operation is ongoing.</comment>
    </bits>
    <bits access="r" name="it_cause" pos="16" rst="0x0">
      <comment>Masked version of it_status that goes to Interrupt controller.</comment>
    </bits>
    <bits access="rw" name="it_status" pos="31" rst="0x0">
        <comment>This bit is set high when an operation is finished. It must be reset before lauching a new operation if Xcor interrupt is enabled.</comment>
    </bits>
  </reg>

  <reg name="hv0" protect="rw">
    <comment>Multipurpose Data Register. <br /> Store Training Sequence in
    TSXC mode. <br /> Store SUM in DCOC 3rd pass mode. <br /> Store bit
    sequence in SREC mode. <br /> Store SUM in SPROC mode. <br /> Store I SUM
    in CHEST mode. <br /> Store R(k-1) in FCHXC mode. </comment>

    <bits access="rw" name="hv0" pos="31:0" rst="0x0">
      <comment>Multipurpose. </comment>
    </bits>
  </reg>

  <reg name="hv1" protect="rw">
    <comment>Multipurpose Data Register. <br /> Store Training Sequence in
    TSXC mode. <br /> Store bit sequence in SREC mode. <br /> Store Q SUM in
    CHEST mode. </comment>

    <bits access="rw" name="hv1" pos="31:0" rst="0x0">
      <comment>Multipurpose. </comment>
    </bits>
  </reg>

  <reg count="6" name="data" protect="rw">
    <comment>Multipurpose Data Registers. <br />D0 stores
    symbols/softvalues/channel taps depending on mode. Not readable. <br />D1
    stores decoded bits/IQ threshols/IQ Offsets/A terms depending on mode. Not
    readable. <br />D2 (aka A1) serves as Rd address (decoded bits, A or B
    terms) / Wr address register (I or packed IQ results, Symbols) / event
    counter depending on mode. <br />D3 (aka A2) serves as Wr address (Q
    results) / event counter depending on mode. <br />D4 stores results from
    VITAC / extracted HardValues depending on mode. Not readable.<br />D5 (aka
    A3) serves as Wr address (CQ results) Not readable. </comment>

    <bits access="rw" name="data" pos="31:0" rst="0x0">
      <comment>Multipurpose. </comment>
    </bits>
  </reg>

  <reg name="accuI" protect="r">
    <bits access="r" name="accuI" pos="XCOR_SADDER_SIZE-1:0" rst="0x0">
      <comment>I part accumulator register.</comment>
    </bits>
  </reg>

  <reg name="accuQ" protect="r">
    <bits access="r" name="accuQ" pos="XCOR_SADDER_SIZE-1:0" rst="0x0">
      <comment>I part accumulator register.</comment>
    </bits>
  </reg>

  <reg name="addr0" protect="rw">
    <comment>Address 0 Register. <br />Stores Rd address for symbols /
    SoftValues / A terms depending on mode. <br /> Auto
    increment/decrement/reset. </comment>

    <bits access="rw" name="addr0" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
      <comment>32-bit word address (bits 0 and 1 disregarded). </comment>
    </bits>
  </reg>
  
  <reg count="6" name="data_e" protect="rw">
    <comment>Multipurpose Data Edge Registers. </comment>

    <bits access="rw" name="data" pos="31:0" rst="0x0">
      <comment>Multipurpose. </comment>
    </bits>
  </reg>
  
</module>

</archive>

<archive relative = "config.xml">
<include file="globals.xml"/>

  
  
  <instance address="0x00000000" type="debug_host_internal_registers" name="INT_REG_DBG_HOST" />
  

  
  
  <instance address="0x01e00000" type="sys_rom" name="SYS_ROM" />
  <instance address="0x01c00000" type="sys_ram" name="SYS_RAM" />
  <instance address="0x02000000" type="psram" name="PSRAM" />
  <instance address="0x02000000" type="psram" name="CS1" />
  <instance address="0x08000000" type="flash" name="FLASH" />
  <instance address="0x08000000" type="flash" name="CS0" />
  <instance address="0x01a38000" type="gouda_sram" name="GOUDA_SRAM" />
  <instance address="0x01a40000" type="usbc" name="USBC" />
  <instance address="0x01b00000" type="mailbox" name="MAILBOX" />

  
  <var name="REG_VOC_BASE" value="0x01a80000"><comment>VOC AHB base</comment></var> -->
  <instance address="REG_VOC_BASE+0x00000000" type="voc_ram" name="VOC_RAM" /> -->
  <instance address="REG_VOC_BASE+0x0001ff80" type="voc_cfg" name="VOC_CFG" /> -->
  <instance address="REG_VOC_BASE+0x00030000" type="voc_ahb" name="VOC_AHB" /> -->


  
  <var name="REG_SYS_APB_BASE" value="0x01a00000"><comment>System APB base</comment></var>

  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SCI1" type="sci" name="SCI1" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SCI2" type="sci" name="SCI2" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SPI1" type="spi" name="SPI1" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SPI2" type="spi" name="SPI2" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SPI3" type="spi" name="SPI3" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_DEBUG_UART" type="debug_uart" name="DEBUG_UART" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_UART1" type="uart" name="UART1" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_UART2" type="uart" name="UART2" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_UART3" type="uart" name="UART3" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_UART4" type="uart" name="UART4" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SDMMC" type="sdmmc" name="SDMMC" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SDMMC2" type="sdmmc" name="SDMMC2" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_CAMERA" type="camera" name="CAMERA" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_GSM_RF_SPI" type="rf_spi" name="GSM_RF_SPI" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_NB_RF_SPI" type="rf_spi" name="NB_RF_SPI" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_GPIO" type="gpio" name="GPIO" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_PWM" type="pwm" name="PWM" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_KEYPAD" type="keypad" name="KEYPAD" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SEG_SCAN" type="seg_scan" name="SEG_SCAN" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_I2C1" type="i2c_master" name="I2C1" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_I2C2" type="i2c_master" name="I2C2" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_I2C3" type="i2c_master" name="I2C3" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_DMA" type="dma" name="SYS_DMA" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_GOUDA" type="gouda" name="GOUDA" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_GSM_TCU" type="tcu" name="GSM_TCU" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_NB_TCU" type="tcu" name="NB_TCU" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_COMREGS" type="comregs" name="SYS_COMREGS" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_LVDS" type="lvds" name="SYS_LVDS" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_PAGE_SPY" type="page_spy" name="PAGE_SPY" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_DEBUG_HOST" type="debug_host" name="DEBUG_HOST" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_GSM_LPS" type="lps" name="GSM_LPS" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_NB_LPS" type="lps" name="NB_LPS" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_IFC" type="sys_ifc" name="SYS_IFC" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_IRQ" type="sys_irq" name="SYS_IRQ" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SYS_CTRL" type="sys_ctrl" name="SYS_CTRL" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_TIMER" type="timer" name="TIMER" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_CALENDAR" type="calendar" name="CALENDAR" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_WDT" type="wdt" name="WDT" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_LZMA" type="lzma" name="LZMA" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_PSRAM8_CTRL" type="psram8_ctrl" name="PSRAM8_CTRL" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_IOMUX" type="iomux" name="IOMUX" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_PMUC" type="pmuc" name="PMUC" />
  
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_CAU_DIG" type="cau_dig" name="CAU_DIG" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_XCPU_CORE" type="mips32" name="XCPU_CORE" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_XCPU_DBG" type="ela" name="XCPU_DBG" />
  
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_F8" type="cipher_f8" name="CIPHER_F8" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SPIFLASH" type="spi_flash" name="SPI_FLASH" />
  <instance address="REG_SYS_APB_BASE + SYS_APB_STEP * SYS_ID_SPIFLASH_EXT" type="spi_flash" name="SPI_FLASH_EXT" />


  
  <var name="REG_AUD_APB_BASE" value="0x01980000"><comment>Audio APB base</comment></var>

  <instance address="REG_AUD_APB_BASE + SYS_APB_STEP * AUD_ID_IFC" type="aud_ifc" name="AUD_IFC" />
  <instance address="REG_AUD_APB_BASE + SYS_APB_STEP * AUD_ID_AIF" type="aif" name="AIF" />
  <instance address="REG_AUD_APB_BASE + SYS_APB_STEP * AUD_ID_CODEC" type="audio_codec" name="AUDIO_CODEC" />
  <instance address="REG_AUD_APB_BASE + SYS_APB_STEP * AUD_ID_ABB" type="abb" name="ABB" />


  
  
  <instance address="0x01e80000" type="bb_rom" name="BB_ROM" />
  <instance address="0x01d00000" type="bb2g_ram" name="BB2G_RAM" />

  
  <var name="REG_BB_APB_BASE" value="0x01900000"><comment>Baseband APB base</comment></var>

  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_XCOR" type="xcor" name="XCOR" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_CORDIC" type="cordic" name="CORDIC" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_ITLV" type="itlv" name="ITLV" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_VITAC" type="vitac" name="VITAC" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_EXCOR" type="excor" name="EXCOR" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_CHOLK" type="cholk" name="CHOLK" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_CIPHER" type="cipher" name="CIPHER" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_CP2" type="bb_cp2" name="BB_CP2" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_BCPU_CORE" type="mips32" name="BCPU_CORE" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_BCPU_DBG" type="ela" name="BCPU_DBG" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_ROM_CTRL" type="bb_rom_ctrl" name="BB_ROM_CTRL" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_RF_IF" type="rf_if" name="RF_IF" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_IRQ" type="bb_irq" name="BB_IRQ" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_COMREGS" type="comregs" name="BB_COMREGS" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_DMA" type="dma" name="BB_DMA" />

  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_CTRL" type="nb_ctrl" name="NB_CTRL" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_COMMON" type="nb_common" name="NB_COMMON" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_INTC" type="nb_intc" name="NB_INTC" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_CS" type="nb_cell_search" name="NB_CS" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_FFT" type="nb_fft_rsrp" name="NB_FFT_RSRP" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_VITERBI" type="nb_viterbi" name="NB_VITERBI" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_MEAS" type="nb_meas" name="NB_MEAS" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_DS_BSEL" type="nb_ds_bsel" name="NB_DS_BSEL" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_TX_PUSCH" type="nb_tx_pusch_encoder" name="NB_TX_PUSCH" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_TX_CHSC" type="nb_tx_chsc" name="NB_TX_CHSC" />
  <instance address="REG_BB_APB_BASE + BB_APB_STEP * NB_ID_TX_FE" type="nb_tx_frontend" name="NB_TX_FRONTEND" />

  <instance address="REG_BB_APB_BASE + BB_APB_STEP * BB_ID_A53" type="cipher_a53" name="CIPHER_A53" />


  
  
  <instance address="0x00000000" type="rf_dig_iram" name="RF_IRAM" />
  <instance address="0x00005000" type="rf_dig_dram" name="RF_DRAM" />

  
  <var name="RFDIG_APB_BASE" value="0x00030000"><comment>RF_DIG APB base</comment></var>

  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_ITFC" type="rf_interface" name="RFDIG_INTERFACE" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_DFE" type="dfe" name="RFDIG_DFE" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_CTRL" type="rf_dig_ctrl" name="RFDIG_CTRL" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_TIMER0" type="rf_dig_timer" name="RFDIG_TIMER0" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_TIMER1" type="rf_dig_timer" name="RFDIG_TIMER1" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_TIMER2" type="rf_dig_timer" name="RFDIG_TIMER2" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_UART" type="rf_dig_uart" name="RFDIG_UART" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_WDT" type="rf_dig_watchdog" name="RFDIG_WDT" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_RF_COMREGS" type="rf_dig_comregs" name="RF2SYS_COMREGS" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_SYS_COMREGS" type="rf_dig_comregs" name="SYS2RF_COMREGS" />
  <instance address="RFDIG_APB_BASE + RFDIG_APB_STEP * RFDIG_ID_RFFE" type="rf_dig_rffe" name="RFDIG_RFFE" />

  <var name="PULPCORE_APB_BASE" value="0x00080000"><comment>PULPCORE APB base</comment></var>
  <instance address="PULPCORE_APB_BASE + PULPCORE_APB_STEP * PULPCORE_ID_DBG_UNIT" type="pulp_dbg" name="pulp_dbg" />
  <instance address="PULPCORE_APB_BASE + PULPCORE_APB_STEP * PULPCORE_ID_IRQ_UNIT" type="pulp_irq" name="pulp_irq" />
  <instance address="PULPCORE_APB_BASE + PULPCORE_APB_STEP * PULPCORE_ID_SLEEP_UNIT" type="pulp_sc" name="pulp_sc" />


  
  
  <instance address="0x0c000000" type="bt_rom" name="BT_ROM" />
  <instance address="0x0c040000" type="bt_ram" name="BT_RAM" />

  
  <instance address="0x0d000000" type="bt_pulp_debug_unit" name="WCN_PULP_DBG" />
  <instance address="0x0d008000" type="bt_pulp_irq" name="WCN_PULP_IRQ" />
  <instance address="0x0d00c000" type="bt_pulp_sleep" name="WCN_PULP_SLEEP" />
  <instance address="0x0d020000" type="cache_ctrl" name="WCN_ICACHE_CTRL" />
  <instance address="0x0d040000" type="cache_ctrl" name="WCN_DCACHE_CTRL" />

  
  <instance address="0x0d100000" type="bt_link" name="BT_LINK" />
  <instance address="0x0d100200" type="ble_link" name="BLE_LINK" />
  <instance address="0x0d110000" type="bt_exchange_ram" name="BT_EXCHANGE_RAM" />

  
  <var name="WCN_APB_BASE0" value="0x0d400000"><comment>WCN_DIG Sys APB base</comment></var>
  <var name="WCN_APB_BASE1" value="0x0d500000"><comment>WCN_DIG Aud APB base</comment></var>

  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_SYS_CTRL" type="bt_sys_ctrl" name="BT_SYS_CTRL" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_DBM" type="bt_dbm" name="BT_DBM" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_SYS_IFC" type="bt_sys_ifc" name="BT_SYS_IFC" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_BT_CORE" type="bt_core" name="BT_CORE" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_BT_UART" type="bt_uart" name="BT_UART" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_RF_IF" type="bt_rf_if" name="BT_RF_IF" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_BT_MODEM" type="bt_modem" name="BT_MODEM" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_WLAN" type="wlan" name="WLAN" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_WDT" type="bt_wdt" name="BT_WDT" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_TRAP" type="bt_trap" name="BT_TRAP" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_SYSTICK" type="bt_systick" name="BT_SYSTICK" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_BT_COMREGS" type="bt_comregs" name="WCN2SYS_COMREGS" />
  <instance address="WCN_APB_BASE0 + WCN_APB_STEP * WCN_ID_SYS_COMREGS" type="bt_comregs" name="SYS2WCN_COMREGS" />
  <instance address="WCN_APB_BASE1 + WCN_APB_STEP * WCN_ID_AUD_IFC" type="bt_aud_ifc" name="BT_AUD_IFC" />
  <instance address="WCN_APB_BASE1 + WCN_APB_STEP * WCN_ID_FM_DSP" type="fm_dsp" name="FM_DSP" />


</archive>

</bigarchive>
